Digital System Design using Verilog Lab [[BEC302]

Sri Adichunchanagiri Shikshana Trust


S.J.C. INSTITUTE OF TECHNOLOGY

CHICKBALLAPUR-562101

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Digital System Design Using Verilog

SUBJECT CODE: BEC302

SEMESTER: III

YEAR: II

PREPARED BY

Dr.C Rangaswamy, Professor & Head

E.N.Srivani, Assistant Professor

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 Digital System Design using Verilog Lab [[BEC302]
||Jai Sri Gurudev||

S. J. C. INSTITUTE OF TECHNOLOGY, CHICKBALLAPUR

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING
VISION OF THE INSTITUTE

Preparing Competant Engineering and Management professionals to serve the society.

MISSION OF THE INSTITUTE

 Providing students with a sound knowledge in Fundamentals in their branch of study.

 Promoting excellence in teaching,learning Research and Consultancy.
 Exposing students to emerging frontiers in various domain making continuous learning.
 Developing Entrepreneurial acumen to venture its innovative areas.
 Imparting value based professional education with a sense of social responsibility.

VISION OF DEPARTMENT

To Achieve Academic Excellence in Electronics and Communication Engineering by Imparting

quality Technical Education and facilitating Research Activities

MISSION OF DEPARTMENT

 Establishing State of the Art Laboratory facilities and Infrastructure to develop the spirit of
Innovation and Entrepreneurship

 Nurturing the Students with Technical Expertise along with Professional Ethics to provide
solutions for Social Needs

 Encourage Life Long Learning And Research among the Students and Faculty

PROGRAM EDUCATIONAL OBJECTIVES

After successful completion of the program, the graduates will be

PEO1: Graduates of the program will have successful technical and professional career in

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 Digital System Design using Verilog Lab [[BEC302]

Engineering, Technology and multidisciplinary environments.

PEO2: Graduates of the program will utilize their knowledge, technical and communication
Skills to propose optimal solutions to problems related to society in the field of
Electronics and Communication.

PEO3: Graduates of the program will exhibit good interpersonal skills, leadership qualities
and adapt themselves for lifelong learning.

PROGRAM SPECIFIC OUTCOMES

PSO1: Professional Skills: Ability to absorb and apply fundamental knowledge of core
Electronics and Communication Engineering in the analysis, design and development of
Electronics Systems as well as to interpret and synthesize experimental data leading to valid
conclusions

PSO2: Problem-solving skills: Ability to solve complex Electronics and Communication

Engineering problems, using latest hardware and software tools, along with analytical and
managerial skills to arrive at appropriate solutions, either independently or in tea

PROGRAMME OUTCOMES:
1. Engineering Knowledge: Apply knowledge of mathematics, science, engineering fundamentals
and an engineering specialization to the solution of complex engineering problems.
2. Problem Analysis: Identify, formulate, research literature and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural sciences
and engineering sciences
3. Design/ Development of Solutions: Design solutions for complex engineering problems and
design system components or processes that meet specified needs with appropriate consideration
for public health and safety, cultural, societal and environmental considerations.
4. Conduct investigations of complex problems using research-based knowledge and research
methods including design of experiments, analysis and interpretation of data and synthesis of
information to provide valid conclusions.
5. Modern Tool Usage: Create, select and apply appropriate techniques, resources and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
under- standing of the limitations.
6. The Engineer and Society: Apply reasoning informed by contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to
professional engineering practice.

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 Digital System Design using Verilog Lab[BEC302]

7. Environment and Sustainability: Understand the impact of professional engineering solutions

in societal and environmental contexts and demonstrate knowledge of and need for sustainable
development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of engineering practice.
9. Individual and Team Work: Function effectively as an individual, and as a member or leader
in diverse teams and in multi disciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as being able to comprehend and write
effective reports and design documentation, make effective presentations and give and receive clear
instructions.
11. Life-long Learning: Recognize the need for and have the preparation and ability to engage in
independent and life- long learning in the broadest context of technological change.
12. Project Management and Finance: Demonstrate knowledge and understanding of engineering
and management principles and apply these to one’s own work, as a member and leader in a team,
to manage projects and in multidisciplinary environments.
Course Outcomes:
At the end of the course students should be able to:

CO202.1 Apply optimization techniques to simplify Boolean function.

CO202.2 Analyze and design combinational logic circuits.
CO202.3 Apply the knowledge of digital electronics to construct Combinational and
Sequential systems useful for digital system design.
CO202.4 Model Combinational (adders, subtractors, multiplexers) and sequential circuits
using Verilog
CO202.5 Develop a simple digital system using modern tool
CO-PO Mapping
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10
CO202.1 2 3
CO202.2 3 2
CO202.3 3
CO202.4 3
CO202.5 3
2.5 2.5 3 3
1: Slightly 2: Moderately 3: Substantially

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 Digital System Design using Verilog Lab[BEC302]

CO – PSO MAPPING
CO PSO1 PSO2
CO202.1:Apply optimization techniques to simplify Boolean function. 2 -
CO202.2:Analyze and design combinational logic circuits. 3 -
CO202.3:Apply the knowledge of digital electronics to construct Combinational
3 -
and Sequential systems useful for digital system design.
CO202.4:Model Combinational (adders, subtractors, multiplexers) and
3 2
sequential circuits using Verilog
CO202.5:Develop a simple digital system using modern tool 3 2
avg 2.8 2
1: Slightly 2: Moderately 3: Substantially

RUBRICS FOR LAB

 FOR 25 MARKS

Sl.No. DESCRIPTION MARKS

1. CONTINUOUS EVALUATION 15

 Observation write up & punctuality 3.0

 Conduction of experiment and output 5.0
 Viva voce 2.0
 Record write up
5.0
2. INTERNAL TEST 10

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 Digital System Design using Verilog Lab [BEC302]

Digital System Design Using Verilog LAB

Subject Code:BEC302 IA Marks: 50

40 hours Theory + 13 Lab slots Exam Marks: 50
Credits: 04

PRACTICAL COMPONENT OF IPCC

 Using suitable simulation software, demonstrate the operation of the following
circuits:
1 To simplify the given Boolean expressions and realize using Verilog program.
2 To realize Adder/Subtractor (Full/half) circuits using Verilog data flow description.
3 To realize 4-bit ALU using Verilog program.
4 To realize the following Code converters using Verilog Behavioral description
a) Gray to binary and vice versa b) Binary to excess3 and vice versa
5 To realize using Verilog Behavioral description: 8:1 mux, 8:3 encoder, Priority encoder
6 To realize using Verilog Behavioral description: 1:8 Demux, 3:8 decoder, 2-bit Comparator
7 To realize using Verilog Behavioral description:
Flip-flops: a) JK type b) SR type c) T type and d) D type
8 To realize Counters - up/down (BCD and binary) using Verilog Behavioral description.
Demonstration Experiments (For CIE only – not to be included for SEE)
 Use FPGA/CPLD kits for downloading Verilog codes and check the output for
interfacing experiments.
9 Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor in the
specified direction (by N steps).
10 Verilog programs to interface a Relay or ADC to the FPGA/CPLD and demonstrate its
working.
11 Verilog programs to interface DAC to the FPGA/CPLD for Waveform generation.
12 Verilog programs to interface Switches and LEDs to the FPGA/CPLD and demonstrate its
working.

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1) a)Realize given SOP expression using verilog program

[y=ad+bd]

module sop(y,a,b,c,d);
output y;
input a,b,c,d;
wire w1,w2;
assign w1=b&d;
assign w2=a&d;
assign y=w1|w2;
endmodule

module tb;
reg a,b,c,d;
wire y;
sop uut(y,a,b,c,d);
initial
begin
a=0;b=0;c=0;d=0;
#100 a=0;b=0;c=0;d=1;
#100 a=0;b=0;c=0;d=1;
#100 a=0;b=0;c=1;d=1;
#100 a=0;b=1;c=0;d=1;
#100 a=0;b=1;c=1;d=0;
#100 a=0;b=1;c=1;d=1;
#100 a=1;b=0;c=0;d=1;
#100 a=0;b=1;c=1;d=1;
#100 a=1;b=1;c=0;d=1;
#100 a=1;b=0;c=1;d=1;
end
endmodule

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1) b)Realize given POS expression using verilog program.

y=(a+b)d
module pos(y,a,b,c,d);input
a,b,c,d;
output y;
wire w1;
assign w1=a|b;
assign y=w1&d;
endmodule

module tb1();
wire y;
reg a,b,c,d;
pos uut(.y(y),.a(a),.b(b),.c(c),.d(d));initial
begin a=0;b=0;c=0;d=0;
#100 a=0;b=0;c=0;d=1;
#100 a=0;b=0;c=0;d=1;
#100 a=0;b=0;c=1;d=1;
#100 a=0;b=1;c=0;d=1;
#100 a=0;b=1;c=1;d=0;
#100 a=0;b=1;c=1;d=1;
#100 a=1;b=0;c=0;d=1;
#100 a=0;b=1;c=1;d=1;
#100 a=1;b=1;c=0;d=1;
#100 a=1;b=0;c=1;d=1;
end
endmodule

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2) a) Realize half adder circuit using verilog dataflow description.

module ha(a,b,sum,ca);
input a,b;
output sum,ca;
assign sum=a^b;
assign ca=a&b; endmodule
module tb2;
reg a,b;
wire sum,ca;
ha uut(.a(a),.b(b),.sum(sum),.ca(ca));
initial
begin
a=0;b=0;
#100; a=0;b=1;
#100; a=1;b=0;
#100; a=1;b=1;
end
endmodule
2)b)Realize full adder circuit using verilog dataflow description.
module fa(a,b,c,sum,ca);
input a,b,c;
output sum,ca;
assign sum=a^b^c;
assign ca=(a&b)|(b&c)|(c&a);endmodule
module tb3;
reg a,b,c;
wire sum,ca;
fa uut(a,b,c,sum,ca);
initial
begin a=0;b=0;c=0;
#100 a=0;b=0;c=1;
#100 a=0;b=1;c=0;
#100 a=0;b=1;c=1;
#100 a=1;b=0;c=0;
#100 a=1;b=0;c=1;
#100 a=1;b=1;c=0;
#100 a=1;b=1;c=1;
end
endmodule

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2)c)Realize half subtractor circuit using verilog dataflow

description.
module hs(a,b,dif,br);
input a,b;
output dif,br;
assign dif=a^b;
assign br=~a&b;
endmodule

module tb2;
reg a,b;
wire dif,br;
ha uut(.a(a),.b(b),.dif(dif),.br(br));
initial
begin a=0;b=0;
#100; a=0;b=1;
#100; a=1;b=0;
#100; a=1;b=1;
end
endmodule

2) d)Realize full subtractor circuit using verilog dataflow

description.
module fs(a,b,c,dif,br);
input a,b,c;
output dif,br;
wire w1,w2,w3;
assign dif=a^b^c;
assign br=(~a & (b^c)) |(b&c);
endmodule

module tb4;
reg a,b,c;
wire dif,br;
fs uut(a,b,c,dif,br);
initial
begin a=0;b=0;c=0;
#100 a=0;b=0;c=1;
#100 a=0;b=1;c=0;
#100 a=0;b=1;c=1;

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#100 a=1;b=0;c=0;
#100 a=1;b=0;c=1;
#100 a=1;b=1;c=0;
#100 a=1;b=1;c=1;
end
endmodule

3) To Realize 4 bit ALU using Verilog program.

module alu(a,b,opcode,enable,y);
input [3:0] a,b;
input [3:0] opcode;
input enable;
output [7:0] y;
reg [7:0] y;
always@(a,b,enable,opcode)
begin
if(enable==1'b1)
begin
case (opcode)
4'b0001 :y= a+ b;
4'b0010 :y= a-b;
4'b0011 :y= ~ a;
4'b0100 :y= a* b;
4'b0101 :y= a& b;
4'b0110 :y= a|b;
4'b0111 : y = ~(a & b);
4'b1000 :y= a^b;default: y=8'd0; endcase
end
else
begin y=8'd0;
end
end
endmodule

module tbalu;
reg [3:0]a,b,opcode;
reg enable;
wire [7:0]y;
alu uut(.a(a),.b(b),.opcode(opcode),.enable(enable),.y(y));
initial
begin a=4'b1010;b=4'b0111;opcode=4'b0001;enable=1;
#100; opcode=4'b0001; #100;opcode=4'b0010;

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#100; opcode=4'b0011; #100;opcode=4'b0100;

#100;opcode=4'b0110; #100; opcode=4'b0111;
#100;opcode=4'b1000; #100; a=4'b0110;b=4'b1111;opcode=4'b0011;
#100; opcode=4'b0100;
end
endmodule

4) To realize the following Code converters using Verilog Behavioral description

a) Binary to gray code conversion:

b3 b2 b1 b0

g3 g2 g1 g0

module bintogray(b,g);
input [3:0] b;
output [3:0] g;
reg [3:0] g;
always@(b)
begin
g[3]=b[3];
g[2]=b[3] ^ b[2];
g[1]=b[2] ^ b[1];
g[0]=b[1] ^ b[0];
end
endmodule

module btog;
reg [3:0] b;
wire [3:0] g;
bintogray uut(b,g);
initial
begin
b=4'b0101;
#100 b=4'b1100;
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#100 b=4'b1011;
#100 b=4'b1001;
#100 b=4'b0111;
end
endmodule

4) b) Gray to Binary code conversion:

g3 g2 g1 g0

+ + +

b3 b2 b1 b0

module graytobin(b,g);
input [3:0] g;
output [3:0] b;
reg [3:0] b;
always@(g)
begin
b[3]=g[3];
b[2]=g[3] ^ g[2];
b[1]=g[3] ^ g[2] ^ g[1];
b[0]=g[3] ^ g[2] ^ g[1] ^ g[0];
end
endmodule

module gtob;
reg [3:0] g;
wire [3:0] b;
graytobin uut(b,g);
initial
begin
g=4'b0101;
#100 g=4'b1100;
#100 g=4'b1011;
#100 g=4'b1001;
#100 g=4'b0111;
end
endmodule

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4) C) Binary to Excess-3 code conversion:

module btoe(b,e);
input[3:0]b;
output [3:0]e;
reg [3:0]e;
always@(b)
begin e=b+3;
end
endmodule

module tb;
reg [3:0]b;
wire [3:0]e;
btoe utt(b,e);
initial
begin
b=4'b0010; #100
b=4'b100;
#100 b=4'b1010;
#100 b=4'b1100;
end
endmodule

4) d) Excess 3 to Binary conversion:

module etob(b,e);input
[3:0]e;
output [3:0]b;
reg [3:0]b;
always@(e)
begin
b=e-3;
end
endmodule

module tb11;
reg [3:0]e;
wire [3:0]b;
etob utt(b,e);
initial
begin

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e=4'b0010; #100
e=4'b100;
#100 e=4'b1010;
#100 e=4'b1100;
end
endmodule

5) To realize using Verilog Behavioral description

a) 8:1 Mux

I0

8:1 Mux
I1 OUTPUT

I7

S2 S1 S0

module mux (d,reset,sel,y);

input [7:0] d;
input reset;
input [2:0] sel;
output y;
reg y;
always@(reset,sel,d);
begin
if(reset==1)
y= 1'b0;
else
begin
case(sel)
3'd0 : y = d[0];
3'd1 : y = d[1];
3'd2 : y = d[2];
3'd3 : y = d[3];
3'd4 : y = d[4];

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3'd5 : y = d[5];
3'd6 : y = d[6];
3'd7 : y = d[7];
endcase
end
end
endmodule
module tb;
reg [7:0]d;
reg reset;
reg [2:0]sel;
wire y;
mux uut(d,reset,sel,y);
initial
begin
reset=1’b1;
sel=0;
d=8’b110010x0;
#10 reset=0;
#10 sel=3’d1;
#10 sel=3’d2;
#10 sel=3’d3;
#10 sel=3’d4;
#10 sel=3’d5;
#10 sel=3’d6;
#10 sel=3’d7;
end
endmodule

5) b) 8:3 Encoder (without priority)

module encoder(din,reset,dout);
input [7:0] din;
input reset; output
[2:0] dout;
reg [2:0] dout;
always @(din,reset)
begin

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if (reset == 1'b1)
dout = 3'b000; else
begin
case (din)
8'b00000001 : dout=3'b000;
8'b00000010 : dout=3'b001;
8'b00000100 : dout=3'b010;
8'b00001000 : dout=3'b011;
8'b00010000 : dout=3'b100;
8'b00100000 : dout=3'b101;
8'b01000000 : dout=3'b110;
8'b10000000 : dout=3'b111;
default : dout=3'b000;
endcase
end
end
endmodule

module tb22;
reg [7:0] din;
reg reset;
wire [2:0] dout;
encoder uut(din,reset,dout);
initial
begin
reset=1;
din=8’b00000001;
#100 reset=0;
#100 din=8’b00000001;
#100 din=8’b00000010;
#100 din=8’b00000100;
#100 din=8’b00001000;
#100 din=8’b00010000;
#100 din=8’b00100000;
#100 din=8’b01000000;
#100 din=8’b10000000;
end
endmodule

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5) c) 8:3 Encoder (with priority)

module encoder(din,reset,dout);
input [7:0] din;
input reset; output
[2:0] dout;
reg [2:0] dout;
always @(din,reset)
begin
if (reset == 1'b1)
dout = 3'b000; else
begin
case (din)
8'bxxxxxxx1:dout=3'b000;
8'bxxxxxx10:dout=3'b001;
8'bxxxxx100:dout=3'b010;
8'bxxxx1000:dout=3'b011;
8'bxxx10000:dout=3'b100;
8'bxx100000:dout=3'b101;
8'bx1000000 : dout=3'b110;
8'b10000000 : dout=3'b111;
default : dout=3'b000;
endcase
end
end
endmodule

module tb22;
reg [7:0] din;
reg reset;
wire [2:0] dout;
encoder uut(din,reset,dout);
initial
begin
reset=1;
din=8’b00000001;
#100 reset=0;
#100 din=8’b11000001;
#100 din=8’b00010010;
#100 din=8’b01100100;

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#100 din=8’b11101000;
#100 din=8’b11110000;
#100 din=8’b01100000;
#100 din=8’b11000000;
#100 din=8’b10000000;
end
endmodule

6) To realize using Verilog Behavioral description

a) 1:8 Demux using behavioral description:
module demux(rst,y,sel,d);
input y;
input rst;
input [2:0]sel;
output [7:0]d;
reg [7:0]d;
always@(sel,y,rst)
begin if(rst==1'b1)
d=8'b00000000;
else
begin
case(sel)
3'b000:d[0]=y;
3'b001:d[1]=y;
3'b010:d[2]=y;
3'b011:d[3]=y;
3'b100:d[4]=y;
3'b101:d[5]=y;
3'b110:d[6]=y;
3'b111:d[7]=y;
default: begin
end
endcase
end
end
endmodule

module tb13;
reg y,rst;
reg [2:0]sel;

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wire [7:0]d;
demux ttt(.rst(rst),.y(y),.sel(sel),.d(d));
initial
begin
rst=1;sel=0;
#100;
#50 rst=0;y=1;
#50 sel=3'd0;
#50 sel=3'd1;
#50 sel=3'd2;
#50 sel=3'd3;
#50 sel=3'd4;
#50 sel=3'd5;
#50 sel=3'd6;
#50 sel=3'd7;
end
endmodule

6) b) 3:8 Decoder using behavioral description:

module decoder(ip,op,en);
input [2:0]ip;
output [7:0]op;input
en;
reg [7:0]op;
always@(ip,en)
begin
if(en==1)
op=8'b0;
else begin
case(ip)
3'd0:op=8'b00000001;
3'd1:op=8'b00000010;
3'd2:op=8'b00000100;
3'd3:op=8'b00001000;
3'd4:op=8'b00010000;
3'd5:op=8'b00100000;
3'd6:op=8'b01000000;
3'd7:op=8'b10000000;
endcase
end
end
endmodule

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module tb22;
reg en;
reg [2:0]ip;
wire [7:0]op;
decoder uut(ip,op,en);initial
begin
en=1;
#100 ip=3'b010;
#100 en=0;
#100 ip=3'd1;
#100 ip=3'd2;
#100 ip=3'd3;
#100 ip=3'd4;
#100 ip=3'd5;
#100 ip=3'd6;
#100 ip=3'd7;
end
initial
$monitor ($time,"output is %b",op);
endmodule
6) c) 2 bit comparator:
module comparator(a,b,en,aeqb,agtb,altb);input [1:0]a;
input [1:0]b;
input en;
output aeqb,agtb,altb;reg
aeqb,agtb,altb;
always@(a,b,en) begin
if(en==1)
begin
if(a==b)
begin
aeqb=1;
agtb=0;
altb=0;
end
if(a>b)
begin
aeqb=0;
agtb=1;
altb=0;
end

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if(a<b)
begin
aeqb=0;
agtb=0;
altb=1;
end
end

module tstbench();
reg [1:0]A;
reg [1:0]B;
reg EN;
wire e,g,l;
comparator n1(.a(A),.b(B),.en(EN),.aeqb(e),.agtb(g),.altb(l));
initial
begin
A=2'b00;B=2'b00;EN=0;
#100;EN=1;
#10 A=2'b00;B=2'b01;
#10 A=2'b10;B=2'b10;
#10 A=2'b11;B=2'b01;
end
endmodule

7) To realize using Verilog Behavioral description:Flip flops

a) SR Flipflop:
module srff(sr,clk,rst,q,qb);
input [1:0]sr;
input clk,rst;
output q,qb;
reg q,qb;
always@(posedge clk)
begin
if(rst==1'b1)
q=1'b0;
else begin
case(sr)
2'b00:q=q;
2'b01:q=1'd0;
2'b10:q=1'd1;
2'b11:q=1'dz;
endcase

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end
qb = ~q;
end
endmodule

module stimulus;
reg [1:0]sr;
reg clk,rst;
wire q,qb;
srff ff1(.sr(sr),.clk(clk),.rst(rst),.q(q),.qb(qb));
initial
begin
$monitor($time, "rst=%b sr=%b, clk=%b, q=%b qb=%b",rst,sr,clk,q,qb);
sr=2'b00;
clk=0;
rst=0;
#50 rst=1;
sr=2'b01;
#50 rst=0;
sr=2'b01;
#50 sr=2'b10;
#50 sr=2'b11;
#50 sr=2'b00;
#50 sr=2'b10;
#50 sr=2'b01;
#50 sr=2'b10;
#50 sr=2'b11;
#50 sr=2'b00;
#50 sr=2'b01;
#50 sr=2'b10;
end
always #5 clk=~clk;
endmodule

b) D Flipflop
module dff(d,clk,rst,q,qb);
input d;
input clk,rst;
output q,qb; reg
q,qb;
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
begin
q<=1'd0;

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qb<=1'd1;
end
else
begin
q<=d; qb<=~d;
end
end
endmodule

module stimulus1;reg
d,clk,rst;
wire q,qb;
dff d1(d,clk,rst,q,qb);
initial
begin
clk=0;
rst=1;
#10 rst=0;
d=0;
#10 d=1;
#10 d=0;
#10 rst=1;
d=0;
#10 rst=1;
d=1;
#10 rst=0;
d=1;
end
always #5 clk=~clk;
endmodule

c) T Flipflop:
module tff(t,clk,rst,q,qb);
input t;
input clk,rst;
output q,qb;
reg q,qb;
always@(posedge clk )
begin
if(rst==1'b1)
begin
q<=1'd0;

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qb<=1'd1;
end
else
begin
if(t==1'b1)
q=~q;
else q=q;
end
qb=~q;
end
endmodule

module stimulus2;
reg t,clk,rst;
wire q,qb;
tff t1(t,clk,rst,q,qb);
initial
begin
clk=0;rst=1; #10
rst=0; t=0;
#10 t=1;
#10 t=0;
#10 rst=1; t=0;
#10 rst=1; t=1;
#10 rst=0; t=1;
#100 rst=0; t=0;
end
always #10 clk=~clk;
endmodule
d) JK Flipflop:
module jkff(jk,clk,rst,q,qb);
input [1:0]jk;
input clk;
input rst;
output q,qb;
reg q,qb;
always@(posedge clk)
begin
if(rst==1'b1)
q=1'd0;
else
begin
case(jk)
2'b00:q=q;

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2'b01:q=1'd0;
2'b10:q=1'd1;
2'b11:q=~q;
endcase end
qb=~q; end
endmodule

module test;
reg [1:0]jk;
reg clk,rst;
wire q,qb;
jkff ff2(jk,clk,rst,q,qb);
initial
begin
jk=2'b01;
clk=0;
rst=0;#50
#10 jk=2'b10;
rst=1;
#30 jk=2'b01;
#30 rst=0;jk=2'b00;
#30 jk=2'b01;
#30 jk=2'b10;
#30 jk=2'b11;
#100;
#30 jk=2'b00;
#30 jk=2'b10;
end
always #10 clk=~clk;
endmodule

6) To realize Counters - up/down (BCD and binary) using Verilog

Behavioral description.
A) Synchronous reset binary up counter.
module counter1(clk,rst,qout);
input clk;
input rst;
output [3:0]qout;
reg [3:0]qout;
always@(posedge clk)

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begin
if(rst==1'b1)
qout=4'b0000;
else
qout=qout+1;
end
endmodule

module test;
reg clk,rst;
wire [3:0]qout;
counter1 uut(clk,rst,qout);
initial
begin
clk=0; rst=1;
#10 rst=0;
#200 rst=1;
end
always #5 clk=~clk;
endmodule

B) BCD up counter with synchronous reset

module counter4(rst,clk,qout);
input rst;
input clk;
output [3:0]qout;
reg [3:0]qout;
always@(posedge clk)//(posedge clk,posedge rst) for asynchronous rst bcd up counter
begin if(rst==1)
qout=4'b0000;
else
begin qout=qout+1;
if(qout==4'b1001)
qout=4'b0000;
end
end
endmodule

module stimulus;
reg rst,clk;
wire [3:0]qout;
counter4 tb(rst,clk,qout);initial
begin clk=0;
rst=1;
#10;

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#10 rst=0;
#200 rst=1;
end
always #5 clk=~clk;
endmodule

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