Jain College of Engineering, Belagavi

Department of Computer Science and Engineering

Subject
Digital Design and Computer Organization Lab

IPCC

Semester: 3rd

Course Code
BCS302

Scheme 2022
Faculty handling
Dr.Ryan Dias

Year 2023-2024

1
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

VISION
To create a centre of excellence in teaching, learning and professional environment in the
discipline of Computer Science and Engineering addressing emerging and existing challenges
striving to meet the requirement of both industry and society.

MISSION
M1:To provide value-based quality technical education and training with continuous improvement
in the discipline of Computer Science and Engineering.
M2:To develop professionals to meet the requirements of industry and society.
M3:To promote innovation, dedication, and hard work with ethically and professionally
responsible behaviour.

PROGRAM EDUCATIONAL OBJECTIVES(PEO)

PEO1:Graduates will be able to solve real-world problems and engineering problems by applying
fundamentals and recent technologies in the discipline of Computer Science and Engineering.
PEO2:Graduates will be able to perform well in design and development of software product
formulating necessary requirements through effective communication.
PEO3:Graduates will be able to take up higher studies and innovative projects.
PEO4:Graduates will behave in an ethically and professionally responsible manner.

2
PROGRAM SPECIFIC OUTCOMES(PSO)
Engineering Graduates will be able to:
PSO1: Identify the Problem, analyze, design, develop, test and implement solution using
appropriate tools and technologies
PSO2: Apply the knowledge to carry out innovative projects and transform ideas into working
modules following the professional ethics and engineering principles

PROGRAM OUTCOMES AS DEFINED BY NBA (PO)

Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with
an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to
the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.

3
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

Course outcomes (Course Skill Set):

At the end of the course, the student will be able to:
CO1: Apply the K–Map techniques to simplify various Boolean expressions.
CO2: Design different types of combinational and sequential circuits along with Verilog programs.
CO3: Describe the fundamentals of machine instructions, addressing modes and Processor
performance.
CO4: Explain the approaches involved in achieving communication between processor and I/O
devices.
CO5:Analyze internal Organization of Memory and Impact of cache/Pipelining on Processor
Performance.
CIE for the theory component of the IPCC (maximum marks 50)
● IPCC means practical portion integrated with the theory of the course.
● CIE marks for the theory component are 25 marks and that for the practical component is 25
marks.
● 25 marks for the theory component are split into 15 marks for two Internal Assessment Tests
(Two Tests, each of 15 Marks with 01-hour duration, are to be conducted) and 10 marks for other
assessment methods mentioned in 22OB4.2. The first test at the end of 40-50% coverage of the

4
syllabus and the second test after covering 85-90% of the syllabus.

● Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for
the theory component of IPCC (that is for 25 marks).

● The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of
IPCC.

CIE for the practical component of the IPCC

● 15 marks for the conduction of the experiment and preparation of laboratory record, and 10
marks for the test to be conducted after the completion of all the laboratory sessions.

● On completion of every experiment/program in the laboratory, the students shall be evaluated

including viva-voce and marks shall be awarded on the same day.

● The CIE marks awarded in the case of the Practical component shall be based on the continuous

evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks. Marks
of all experiments’ write-ups are added and scaled down to 15 marks.

● The laboratory test (duration 02/03 hours) after completion of all the experiments shall be

conducted for 50 marks and scaled down to 10 marks. Scaled-down marks of write-up evaluations
and tests added will be CIE marks for the laboratory component of IPCC for 25 marks.

● The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of
the IPCC.

SEE for IPCC

Theory SEE will be conducted by University as per the scheduled timetable, with common
question

papers for the course (duration 03 hours)

1. The question paper will have ten questions. Each question is set for 20 marks.

2. There will be 2 questions from each module. Each of the two questions under a module (with a

maximum of 3 sub-questions), should have a mix of topics under that module.

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3. The students have to answer 5 full questions, selecting one full question from each module.

4. Marks scored by the student shall be proportionally scaled down to 50 Marks

The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion will

have a CIE component only. Questions mentioned in the SEE paper may include questions from

the practical component.

Contents
Sl.No Experiments Pg.no
1. Given a 4-variable logic expression, simplify it using appropriate
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technique and simulate the same using basic gates.
2. Design a 4 bit full adder and subtractor and simulate the same using basic
12
gates.
3. Design Verilog HDL to implement simple circuits using structural, Data
15
flow and Behavioural model.
4. Design Verilog HDL to implement Binary Adder-Subtractor – Half and
26
Full Adder, Half and Full Subtractor.
5. Design Verilog HDL to implement Decimal adder. 40
6. Design Verilog program to implement Different types of multiplexer like
44
2:1, 4:1 and 8:1.
7. Design Verilog program to implement types of De-Multiplexer. 56
8. Design Verilog program for implementing various types of Flip-Flops 57
such as SR, JK and D.

6
 Experiment 1:
AIM: Given a 4-variable logic expression, simplify it using appropriate technique and
simulate the same using basic gates.
Tool used: Xilinx 13.1
̅
̅+𝒄̅.b)𝒅
1) y=(𝒂

Theory :
RTL Diagram:

Program1:

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module exp2(
input a,b,c,d,
output y
);
assign y=((~a)|((~c)|b)&(~d));

endmodule
Test Bench :
module exp2_test;
// Inputs
reg a;
reg b;
reg c;
reg d;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
exp2 uut (
.a(a),
.b(b),
.c(c),
.d(d),
.y(y)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
d = 0;

// Wait 100 ns for global reset to finish

#50;

// Add stimulus here

a = 0;
b = 0;
c = 0;
d = 1;

// Wait 100 ns for global reset to finish

#50;
a = 0;

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b = 0;
c = 1;
d = 0;

// Wait 100 ns for global reset to finish

#50;

a = 0;
b = 0;
c = 1;
d = 1;

// Wait 100 ns for global reset to finish

#50;
a = 0;
b = 1;
c = 0;
d = 0;

// Wait 100 ns for global reset to finish

#50;
a = 0;
b = 1;
c = 0;
d = 1;

// Wait 100 ns for global reset to finish

#50;
a = 0;
b = 1;
c = 1;
d = 0;

// Wait 100 ns for global reset to finish

#50;
a = 0;
b = 1;
c = 1;
d = 1;

// Wait 100 ns for global reset to finish

#50;
a = 1;
b = 0;
c = 0;
d = 0;

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// Wait 100 ns for global reset to finish
#50;
a = 1;
b = 0;
c = 0;
d = 1;

// Wait 100 ns for global reset to finish

#50;
a = 1;
b = 0;
c = 1;
d = 0;

// Wait 100 ns for global reset to finish

#50;
a = 1;
b = 0;
c = 1;
d = 1;

// Wait 100 ns for global reset to finish

#50;
a = 1;
b = 1;
c = 0;
d = 0;

// Wait 100 ns for global reset to finish

#50;
a = 1;
b = 1;
c = 0;
d = 1;
//Wait 100 ns for global reset to finish
#50;
a = 1;
b = 1;
c = 1;
d = 0;

// Wait 100 ns for global reset to finish

#50;
a = 1;
b = 1;

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 c = 1;
d = 1;

// Wait 100 ns for global reset to finish

#50;

end

endmodule

Simulation Output:

Conclusion :

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 Experiment :2
AIM:- Design a 4 bit full adder and subtractor and simulate the same using basic gates.
Verilog code:
module fadder (A, B, Cin, Sum, Cout);
input A, B;
input Cin;
output Sum;
output Cout;
wire t1,t2,t3,t4;
xor x1(t1,A,B);
xor x2(Sum,t1,Cin);
and g1(t2,A,B);
and g2(t3,B,Cin);
and g3(t4,Cin,A);
or g4(Cout,t2,t3,t4);
endmodule

module add_sub_4 (A, B, In, Res, Out);

input [3:0] A, B;
input In;
output [3:0] Res;
output Out;
wire t0,t1,t2,t3,t4,t5,t6;
xor x3(t0,B[0],In);
xor x4(t1,B[1],In);
xor x5(t2,B[2],In);
xor x6(t3,B[3],In);
fadder f5(A[0],t0,In,Res[0],t4);
fadder f6(A[1],t1,t4,Res[1],t5);
fadder f7(A[2],t2,t5,Res[2],t6);
fadder f8(A[3],t3,t6,Res[3],Out);
endmodule

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*Test bench:
module add_sub_4_tb;
reg [3:0] A,B;
reg In;
wire [3:0] Res;
wire Out;
add_sub_4 tb(A,B,In,Res,Out);
initial
begin
In=0; A=4'b1010; B=4'b0101;
#50 In=1;
#50 In=0; A=4'b0101; B=4'b1010;
#50 In=1;
#50 In=0; A=4'b0001; B=4'b0001;
end
endmodule

*RTL Diagrams:-

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*Simulation Output:

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 Experiment 3:
AIM:- Design Verilog HDL to implement simple circuits using structural, Data flow and
Behavioural model.
1)Using data flow :-
Verilog code:-
module Full_Adder(
input a,b,c,
output sum,cary
);
assign sum=(a&(~b)&(~c))|((~a)&(~b)&c)|(a&b&c)|((~a)&b&(~c));
assign cary=b&c|a&c|a&b;
endmodule

*Test bench:-
module full_test;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire sum;
wire cary;
// Instantiate the Unit Under Test (UUT)
Full_Adder uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
.cary(cary)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
// Wait 100 ns for global reset to finish
#50;

// Add stimulus here

a = 0;
b = 0;

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 c = 1;
// Wait 100 ns for global reset to finish
#50;
a = 0;
b = 1;
c = 0;
// Wait 100 ns for global reset to finish
#50;
a = 0;
b = 1;
c = 1;
// Wait 100 ns for global reset to finish
#50;
a = 1;
b = 0;
c = 0;
// Wait 100 ns for global reset to finish
#50;
a = 1;
b = 0;
c = 1;
// Wait 100 ns for global reset to finish
#50;
a = 1;
b = 1;
c = 0;
// Wait 100 ns for global reset to finish
#50;
a = 1;
b = 1;
c = 1;
// Wait 100 ns for global reset to finish
#50;
end
endmodule

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*RTL diagrams:

17
*Simulation Output:

2)Using behavioural model:

*Verilog code:
module full_adder(
input a,b,c,
output reg sum,cout
);
always @(a,b,c)
begin
if (a==0 && b==0&& c==0)
begin
sum=0; cout=0;
end
else if(a==0 && b==0 && c==1)
begin
sum=1; cout=0;
end
else if(a==0 && b==1 && c==0)
begin
sum=1; cout=0;
end
else if(a==0 && b==1 && c==1)
begin
sum=0; cout=1;
end
else if(a==1 && b==0 && c==0)
begin
sum=1; cout=0;
end
else if(a==1 && b==0 && c==1)
begin
sum=0; cout=1;

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end
else if(a==1 && b==1 && c==0)
begin
sum=0; cout=1;
end
else if(a==1 && b==1 && c==1)
begin
sum=1; cout=1;
end
end
endmodule
*Test bench:
module full_test;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire sum;
wire cout;
// Instantiate the Unit Under Test (UUT)
full_adder uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
.cout(cout)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
// Wait 100 ns for global reset to finish
#50;

// Add stimulus here

a = 0;
b = 0;
c = 1;
// Wait 100 ns for global reset to finish
#50;
a = 0;

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 b = 1;
c = 0;
// Wait 100 ns for global reset to finish
#50;
a = 0;
b = 1;
c = 1;
// Wait 100 ns for global reset to finish
#50;
a = 1;
b = 0;
c = 0;
// Wait 100 ns for global reset to finish
#50;
a = 1;
b = 0;
c = 1;
// Wait 100 ns for global reset to finish
#50;
a = 1;
b = 1;
c = 0;
// Wait 100 ns for global reset to finish
#50;
a = 1;
b = 1;
c = 1;
// Wait 100 ns for global reset to finish
#50;
end
endmodule

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*RTL diagrams:

21
*Simulation Output:

3)Using Structural model:

*Verilog code:
module full_adder(
input a,b,c,
output sum,carry
);
wire w1,w2,c1,c2;
xor x1(w1,a,b);
and a1(c1,a,b);
xor x2(sum,w1,c);
and a2(c2,w1,c);
or o1(carry,c1,c2);
endmodule

*Test bench:
module testbench_fulladder;
reg a,b,c;
wire sum,cout;
full_adder f1(a,b,c,sum,cout);
initial begin
a = 1'b0;
b = 1'b0;
c = 1'b0;
#50;
a = 1'b0;
b = 1'b0;
c = 1'b1;
#50;
a = 1'b0;
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b = 1'b1;
c = 1'b0;
#50;
a = 1'b0;
b = 1'b1;
c = 1'b1;
#50;

a = 1'b1;
b = 1'b0;
c = 1'b0;
#50;
a = 1'b1;
b = 1'b0;
c = 1'b1;
#50;
a = 1'b1;
b = 1'b1;
c = 1'b0;
#50;
a = 1'b1;
b = 1'b1;
c = 1'b1;
#50;
end
endmodule

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*RTL Diagrams:

24
*Simulation Output:-

25
 Experiment 4
AIM: Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder,
Half and Full Subtractor.
1)Half adder:
Code:
module half_adder(
input a,b,
output cary,sum
);
assign sum=((~a)&b)|((~b)&a);
assign cary=a&b;
endmodule

Test bench:
module halfAdder_test;
// Inputs
reg a;
reg b;

// Outputs
wire cary;
wire sum;

// Instantiate the Unit Under Test (UUT)

half_adder uut (
.a(a),
.b(b),
.cary(cary),
.sum(sum)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;

// Wait 50 ns for global reset to finish

#50;

// Add stimulus here

a = 0;
b = 1;

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 // Wait 50 ns for global reset to finish
#50;
a = 1;
b = 0;
// Wait 50 ns for global reset to finish
#50;
a = 1;
b = 1;

// Wait 50 ns for global reset to finish

#50;
end

endmodule

*RTL Diagram:

27
Output

2)Full Adder
Code:
module Full_Adder(
input a,b,c,
output sum,cary
);
assign sum=(a&(~b)&(~c))|((~a)&(~b)&c)|(a&b&c)|((~a)&b&(~c));
assign cary=b&c|a&c|a&b;

endmodule

Test Bench:
module full_test;
// Inputs

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reg a;
reg b;
reg c;
// Outputs
wire sum;
wire cary;
// Instantiate the Unit Under Test (UUT)
Full_Adder uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
.cary(cary)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;

// Wait 100 ns for global reset to finish

#50;

// Add stimulus here

a = 0;
b = 0;
c = 1;

// Wait 100 ns for global reset to finish

#50;
a = 0;
b = 1;
c = 0;

// Wait 100 ns for global reset to finish

#50;
a = 0;
b = 1;
c = 1;

// Wait 100 ns for global reset to finish

#50;

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 a = 1;
b = 0;
c = 0;

// Wait 100 ns for global reset to finish

#50;
a = 1;
b = 0;
c = 1;

// Wait 100 ns for global reset to finish

#50;
a = 1;
b = 1;
c = 0;

// Wait 100 ns for global reset to finish

#50;
a = 1;
b = 1;
c = 1;

// Wait 100 ns for global reset to finish

#50;

end

endmodule
RTL:

30
31
32
Simulation Output:

3)Half Subtractor:
Code:
module half_sub(
input a,b,
output dif,borrow
);
assign dif=((~a)&b)|((~b)&a);
assign borrow=(~a)&b;
endmodule

Test Bench:
module halfSub_test;
// Inputs
reg a;
reg b;
// Outputs
wire dif;
wire borrow;
// Instantiate the Unit Under Test (UUT)
half_sub uut (
.a(a),
.b(b),
.dif(dif),
.borrow(borrow)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;

// Wait 50 ns for global reset to finish

33
 #50;

// Add stimulus here

a = 0;
b = 1;

// Wait 50 ns for global reset to finish

#50;
a = 1;
b = 0;

// Wait 50 ns for global reset to finish

#50;
a = 1;
b = 1;

// Wait 50 ns for global reset to finish

#50;
end
endmodule

RTL:

34
*Simulation Output 

35
4)Full subtractor:
*code:
module Full_sub(
input a,b,c,
output diff,borrow
);
assign diff=(a&(~b)&(~c))|((~a)&(~b)&c)|(a&b&c)|((~a)&b&(~c));
assign borrow=(~a)&c|b&c|(~a)&b;
endmodule

*Test bench:-
module full_test_sub;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire diff;
wire borrow;

// Instantiate the Unit Under Test (UUT)

Full_sub uut (
.a(a),
.b(b),
.c(c),
.diff(diff),
.borrow(borrow)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;

// Wait 100 ns for global reset to finish

#50;

// Add stimulus here

a = 0;
b = 0;c = 1;

// Wait 100 ns for global reset to finish

36
 #50;
a = 0;
b = 1;
c = 0;

// Wait 100 ns for global reset to finish

#50;
a = 0;
b = 1;
c = 1;

// Wait 100 ns for global reset to finish

#50;
a = 1;
b = 0;
c = 0;

// Wait 100 ns for global reset to finish

#50;
a = 1;
b = 0;
c = 1;

// Wait 100 ns for global reset to finish

#50;
a = 1;
b = 1;
c = 0;

// Wait 100 ns for global reset to finish

#50;
a = 1;
b = 1;
c = 1;

// Wait 100 ns for global reset to finish

#50;
end
endmodule

37
*RTL :

38
*Simulation output

39
 Experiment 5

AIM:- Design Verilog HDL to implement Decimal adder.

*Verilog code:-
module bcd_adder(a,b,carry_in,sum,carry);
input [3:0] a,b;
input carry_in;
output [3:0] sum;
output carry;
//Internal variables
reg [4:0] sum_temp;
reg [3:0] sum;
reg carry;
//always block for doing the addition
always @(a,b,carry_in)
begin
sum_temp = a+b+carry_in; //add all the inputs
if(sum_temp > 9) begin
sum_temp = sum_temp+6; //add 6, if result is more than 9.
carry = 1; //set the carry output
sum = sum_temp[3:0]; end
else begin
carry = 0;
sum = sum_temp[3:0];
end
endmodule

*Test bench:-
module tb_bcdadder;

40
 // Inputs
reg [3:0] a;
reg [3:0] b;
reg carry_in;
// Outputs
wire [3:0] sum;
wire carry;
// Instantiate the Unit Under Test (UUT)
bcd_adder uut (
.a(a),
.b(b),
.carry_in(carry_in),
.sum(sum),
.carry(carry)
);
initial begin
// Apply Inputs
a = 0; b = 0; carry_in = 0; #50;
a = 6; b = 9; carry_in = 0; #50;
a = 3; b = 3; carry_in = 1; #50;
a = 4; b = 5; carry_in = 0; #50;
a = 8; b = 2; carry_in = 0; #50;
a = 9; b = 9; carry_in = 1; #50;
end
endmodule

*RTL Diagrams:-

41
42
*Simulation output:-

43
 Experiment 6:-
AIM: Design Verilog program to implement Different types of multiplexer like 2:1, 4:1
and 8:1.
1)Multiplexer 2x1
*Code:
module mux2_1(
input i0 , i1 , s,
output y
);
assign y = (~s) & i0 | s & i1 ;

endmodule

*test bench:
module mux2_1_test;
// Inputs
reg i0;
reg i1;
reg s;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux2_1 uut (
.i0(i0),
.i1(i1),
.s(s),
.y(y)
);
initial begin
// Initialize Inputs
i0 = 0;
i1 = 0;
s = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
i0 = 1;
i1 = 0;
s = 0;

44
 // Wait 100 ns for global reset to finish
#100;
i0 = 0;
i1 = 0;
s = 1;
// Wait 100 ns for global reset to finish
#100;
i0 = 0;
i1 = 1;
s = 1;
// Wait 100 ns for global reset to finish
#100;
end
endmodule

*RTL and Graphs:

45
*OUTPUT:

46
2)Multiplexer 4x1
*Code:
module mux41_dataflow(
input s0,s1,
input I0,I1,I2,I3,
output y
);
assign y=(((~s0)&(~s1)&I0)|(I1&(~s0)&s1)|(s0&(~s1)&I2)|(s0&s1&I3));

endmodule

*Test Bench:
module mux4_1test;
// Inputs
reg [2:0] select;
reg i0;
reg i1;
reg i2;
reg i3;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux4_1 uut (
.select(select),
.i0(i0),
.i1(i1),
.i2(i2),
.i3(i3),
.y(y)
);
initial begin
/*// Initialize Inputs
select[0] = 0;
select[1]=0
i0 = 1;
i1 = 0;
i2 = 0;
i3 = 0;
// Wait 100 ns for global reset to finish
#50;
// Add stimulus here
select[0] = 0;

47
 select[1]=1;
i0 = 0;
i1 = 1;
i2 = 0;
i3 = 0;
#50;
select[0] = 1;
select[1]=0;
i0 = 0;
i1 = 0;
i2 = 1;
i3 = 0;
#50;
select[0] = 1;
select[1]=1;
i0 = 0;
i1 = 0;
i2 = 0;
i3 = 1;
#50;
end
endmodule

RTL Diagram

48
49
Simulation Output :

3)Multiplexer 8x1:-
*Code:-
module mux8_1(
input [2:0] select,
input [7:0]i,
output reg y
);
always @(select,i)
case(select)
3'b111:y=i[7];
3'b110: y=i[6];
3'b101: y=i[5];
3'b100: y=i[4];
3'b011: y=i[3];
3'b010: y=i[2];
3'b001: y=i[1];
3'b000: y=i[0];
endcase
endmodule

*Test bench:-
module mux8_test;
// Inputs
reg [2:0] select;

50
reg [7:0] i;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux8_1 uut (
.select(select),
.i(i),
.y(y)
);
initial begin
// Initialize Inputs
select[0] = 0;
select[1]=0;
select[2]=0;
i[0] = 1;
i[1] = 0;
i[2] = 0;
i[3] = 0;
i[4] = 0;
i[5] = 0;
i[6] = 0;
i[7] = 0;
// Wait 100 ns for global reset to finish
#50;
select[0] = 1;
select[1]=0;
select[2]=0;
i[0] = 0;
i[1] = 1;
i[2] = 0;
i[3] = 0;
i[4] = 0;
i[5] = 0;
i[6] = 0;
i[7] = 0;
// Wait 100 ns for global reset to finish
#50;
select[0] = 0;
select[1]=1;
select[2]=0;
i[0] = 0;
i[1] = 0;
i[2] = 1;

51
i[3] = 0;
i[4] = 0;
i[5] = 0;
i[6] = 0;
i[7] = 0;
// Wait 100 ns for global reset to finish
#50;
select[0] = 1;
select[1]=1;
select[1]=0;
i[0] = 0;
i[1] = 0;
i[2] = 0;
i[3] = 1;
i[4] = 0;
i[5] = 0;
i[6] = 0;
i[7] = 0;
// Wait 100 ns for global reset to finish
#50;
select[0] = 0;
select[1]=0;
select[2]=1;
i[0] = 0;
i[1] = 0;
i[2] = 0;
i[3] = 0;
i[4] = 1;
i[5] = 0;
i[6] = 0;
i[7] = 0;
// Wait 100 ns for global reset to finish
#50;
select[0] = 1;
select[1]=0;
select[2]=1;
i[0] = 0;
i[1] = 0;
i[2] = 0;
i[3] = 0;
i[4] = 0;
i[5] = 1;
i[6] = 0;

52
 i[7] = 0;
// Wait 100 ns for global reset to finish
#50;
select[0] =0;
select[1]=1;
select[2]=1;
i[0] = 0;
i[1] = 0;
i[2] = 0;
i[3] = 0;
i[4] = 0;
i[5] = 0;
i[6] = 1;
i[7] = 0;
// Wait 100 ns for global reset to finish
#50;
select[0] = 1;
select[1]=1;
select[2]=1;
i[0] = 0;
i[1] = 0;
i[2] = 0;
i[3] = 0;
i[4] = 0;
i[5] = 0;
i[6] = 0;
i[7] = 1;
// Wait 100 ns for global reset to finish
#50;
end
endmodule

*RTL diagram

53
54
*Simulation Waveform Output

55
 Experimet 7:
AIM:Design verilog program to implement different types of de-multiplexers.
Code:
module Demux1_4(
input d,
output y0,y1,y2,y3,
input s1,s0
);
assign y0=(d&~s1&~s0);
assign y1=(d&~s1&s0);
assign y2=(d&s1&~s0);
assign y3=(d&s1&s0);
endmodule
Test bench:
module demux4_1test;
// Inputs
reg d;
reg s1;
reg s0;
// Outputs
wire y0;
wire y1;
wire y2;
wire y3;
// Instantiate the Unit Under Test (UUT)
Demux1_4 uut (
.d(d),
.y0(y0),

56
 .y1(y1),
.y2(y2),
.y3(y3),
.s1(s1),
.s0(s0)
);
initial begin
// Initialize Inputs
d = 1;
s1 = 0;
s0 = 0;
// Wait 100 ns for global reset to finish
#100; // Add stimulus here
d = 1;
s1 = 0;
s0 = 1;
// Wait 100 ns for global reset to finish
#100;
d = 1;
s1 = 1;
s0 = 0;
// Wait 100 ns for global reset to finish
#100;
d = 1;
s1 = 1;
s0 = 1;

// Wait 100 ns for global reset to finish

57
 #100;
end
endmodule
RTL:

58
Simulation Output

59
2)demux1_2:
Code:
module demux1_2(
input d,s0,E,
output y1,y2 );
assign y1=(E&d&(~s0));
assign y2=(E&d&s0);
endmodule
Test bench:-
module demux1_2_test;
// Inputs
reg d;
reg s0;
reg E;
// Outputs
wire y1;
wire y2;
// Instantiate the Unit Under Test (UUT)
demux1_2 uut (
.d(d),
.s0(s0), .E(E), .y1(y1), .y2(y2)
);

initial begin
#000 E=1'b0; d=1'bx; s0=1'bx;
#100 E=1'b1; d=1'b0; s0=1'b0;
#100 E=1'b1; d=1'b1; s0=1'b0;
#100 E=1'b1; d=1'b0; s0=1'b1;

60
 #100 E=1'b1; d=1'b1; s0=1'b1;
end
endmodule
RTL and graph:

61
*Simulation Output:

3)demux 8x1:-
Code:
62
module Demux8(
input s0,s1,s2,D,
output y0,y1,y2,y3,y4,y5,y6,y7
);
assign y0=(~s0)&(~s1)&(~s2)&(D);
assign y1=(~s0)&(~s1)&(s2)&(D);
assign y2=(~s0)&(s1)&(~s2)&(D);
assign y3=(~s0)&(s1)&(s2)&(D);
assign y4=(s0)&(~s1)&(~s2)&(D);
assign y5=(s0)&(~s1)&(s2)&(D);
assign y6=(s0)&(s1)&(~s2)&(D);
assign y7=(s0)&(s1)&(s2)&(D);
endmodule

Test bench:
module Demuxt8;
// Inputs
reg s0;
reg s1;
reg s2;
reg D;
// Outputs
wire y0;
wire y1;
wire y2;
wire y3;
wire y4;
wire y5;
wire y6;
wire y7;

// Instantiate the Unit Under Test (UUT)

Demux8 uut (.s0(s0),
.s1(s1),
.s2(s2), .D(D),
.y0(y0), .y1(y1), .y2(y2), .y3(y3),
.y4(y4), .y5(y5),
.y6(y6), .y7(y7)
);

initial begin
// Initialize Inputs
s0 = 0;
s1 = 0;
s2 = 0;

63
 D = 1;
// Wait 100 ns for global reset to finish
#100;
s0 = 0;
s1 = 0;
s2 = 1;
D = 1;
// Wait 100 ns for global reset to finish
#100;
s0 = 0;
s1 = 1;
s2 = 0;
D = 1;
// Wait 100 ns for global reset to finish
#100;
s0 = 0;
s1 = 1;
s2 = 1;
D = 1;
// Wait 100 ns for global reset to finish
#100;
s0 = 1;
s1 = 0;
s2 = 0;
D = 1;
// Wait 100 ns for global reset to finish
#100;
s0 = 1;
s1 = 0;
s2 = 1;
D = 1;
// Wait 100 ns for global reset to finish
#100;
s0 = 1;
s1 = 1;
s2 = 0;
D = 1;
// Wait 100 ns for global reset to finish
#100;
s0 = 1;
s1 = 1;
s2 = 1;
D = 1;
// Wait 100 ns for global reset to finish
#100;
end

64
endmodule

RTL & Graph:

65
Simulation Output :

66
 Experiment 8:
*AIM:- Design Verilog program for implementing various types of Flip-Flops such as SR, JK
and D.
1) D_Flipflop :
*Verilog code:-
module D_ff(d,clk,reset,q,qb);
input d;
input clk;
input reset;
output q;
output qb;
reg q,qb;
always@(posedge clk)
begin
if(reset==1'b1)
begin
q<=1'b0;
qb<=1'b1;
end
else
begin
q<=d;
qb<=~d;
end
end
endmodule

*Test bench:-
module D_fft;
// Inputs
reg d;
reg clk;
reg reset;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
D_ff uut (
.d(d),
.clk(clk),

67
 .reset(reset),
.q(q),
.qb(qb)
);
initial begin
// Initialize Inputs
d = 0;
clk = 0;
reset = 1;

// Wait 100 ns for global reset to finish

#100;
d = 0;
clk = 1;
reset = 0;

// Wait 100 ns for global reset to finish

#100;
d = 0;
clk = 0;
reset = 0;

// Wait 100 ns for global reset to finish

#100;
d = 1;
clk = 1;
reset = 0;

// Wait 100 ns for global reset to finish

#100;
d = 0;
clk = 1;
reset = 0;

// Wait 100 ns for global reset to finish

#100;
end
endmodule

*RTL Diagram:-

68
69
*Simulation For D_flipflop:

2)JK filp-flop:-
*Verilog code:-
module JK_ff(JK,clk,reset,q,qb);
input [1:0] JK;
input clk;
input reset;
output q,qb;
regq,qb;
always@(posedgeclk)
begin
if (reset==1’b1)
q = 1'd0 ;
else
begin
case(JK)
2'b00 : q = q ;
2'b01 : q = 1'd0 ;
2'b10 : q = 1'd1 ;
2'b11 : q = ~ q ;
endcase
end
qb = ~q;
end
endmodule

70
*Test bench:-
Module JKtest();
JK = 00;
clk = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#100;
JK = 00;
clk = 1;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
JK = 01;
clk = 1;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
JK = 01;
clk = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#100;
JK = 10;
clk = 1;
reset = 1;

// Wait 100 ns for global reset to finish

#100;
JK = 10;
clk = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#100;
JK = 11;
clk = 1;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
JK = 11;
clk = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#100;
71
 JK = 00;
clk = 1;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
JK = 00;
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
JK = 01;
clk = 1;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
JK = 01;
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
JK = 10;
clk = 1;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
JK = 10;
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
JK = 11;
clk = 1;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
JK = 11;
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
*RTL diagrams:-

72
*Simulation Output :-

73
3. Verify the functionality of T Flip Flop using HDL.

VERILOG Code:
module T_ff(clk,reset,t,q,qb);
input clk;
input reset;
input t;
output q;
output qb;
reg q,qb;
always@(posedge clk)
begin
if (reset==1'b1)
begin
q=1'b0;
qb=1'b1;
end
else
begin
if(t==1'b1)
q = ~q;
else
q = q;

74
end
qb=~q;
end
endmodule

3.. Verify the functionality of SR-Flip flop using HDL

VERILOG Code:
module SR_f_f(SR,clk,reset,q,qb);
input [1:0] SR ;
input clk,reset;
output q,qb;
reg q,qb;
always@(posedge clk)
begin
if(reset==1'b1)
q = 1'b0;
else
begin
case (SR)
2'b00 : q = q ;
2'b01 : q = 1'd0 ;
2'b10 : q = 1'd1 ;
2'b11 : q = 1'dZ ;
endcase
end
qb = ~ q;
end
endmodule

75
76