Adders

Dr. Heranmoy Maity

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 Adders?
Binary Adders are arithmetic circuits in the form of
half-adders and full-adders used to add together
two binary digits.
Another –
Adder is a combinational logic circuit which can be
constructed using just a few basic logic gates
allowing it to add together two or more binary
numbers is the Binary Adder

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 Outline
• One-bit adder,
• basic ripple-carry adder
• Carry-Lookahead adders (CLA)
• Brent-Kung adder

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 Adding Two One-bit Operands
• One-bit Half Adder:
A B Sum Cout
A B 0 0 0 0
0 1 1 0
1 0 1 0
Cout HA
1 1 0 1

Sum

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 Adding Two One-bit Operands
• One-bit Half Adder:
A B Sum Cout
A B 0 0 0 0
0 1 1 0
1 0 1 0
Cout HA
1 1 0 1

Sum From the truth table …….

Sum = A’B + AB’ = A ⊕ B

Cout = A.B

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 Adding Two One-bit Operands
• One-bit Half Adder:
A B Sum Cout
A B 0 0 0 0
0 1 1 0
1 0 1 0
Cout HA
1 1 0 1

Sum

Sum = A’B + AB’ = A ⊕ B

Cout = A.B

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 Adding Two One-bit Operands
• One-bit Full Adder:
Cin A B Sum Cout
A B 0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
Cout FA Cin 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
Sum
1 1 0 0 1
1 1 1 1 1

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 Adding Two One-bit Operands
• One-bit Full Adder:
Cin A B Sum Cout
A B 0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
Cout FA Cin 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
Sum
1 1 0 0 1
1 1 1 1 1

Sum = A’BCin’ + AB’Cin’ + A’B’Cin + ABCin

=A ⊕ B ⊕ Cin

Cout = ABCin’ + A’BCin + AB’Cin + ABCin

= A.B + B.Cin + A.Cin
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 Adding Two One-bit Operands
• One-bit Full Adder:
Cin A B Sum Cout
A B 0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
Cout FA Cin 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
Sum
1 1 0 0 1
1 1 1 1 1
Sum = A’BCin’ + AB’Cin’ + A’B’Cin + ABCin
=A ⊕ B ⊕ Cin

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 Adding Two One-bit Operands
• One-bit Full Adder:
Cin A B Sum Cout
A B 0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
Cout FA Cin 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
Sum
1 1 0 0 1
1 1 1 1 1
Sum = A’BCin’ + AB’Cin’ + A’B’Cin + ABCin
=A ⊕ B ⊕ Cin

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 Adding Two One-bit Operands
• One-bit Full Adder:
Cin A B Sum Cout
A B 0 0 0 0 0
Sum = A’BCin’ + AB’Cin’ + A’B’Cin + ABCin
=A ⊕ B ⊕ Cin
0 0 1 1 0
0 1 0 1 0
Cout FA Cin Cout = ABCin’ + A’BCin + AB’Cin + ABCin
= A.B + B.Cin + A.Cin
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
Sum
1 1 0 0 1
1 1 1 1 1

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 Adding Two One-bit Operands
• One-bit Full Adder Circuit Using Half-Adder
Cin A B Sum Cout
A B 0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
Cout FA Cin 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
Sum
1 1 0 0 1
Cout = ABCin’ + A’BCin + AB’Cin + ABCin 1 1 1 1 1
= A.B + B.Cin + A.Cin

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 Adding Two One-bit Operands
• One-bit Full Adder Circuit Using Half-Adder
Cin A B Sum Cout
0 0 0 0 0
A B 0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
Cout FA Cin 1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
Sum
1 1 1 1 1

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 Adding Two One-bit Operands
• One-bit Full Adder Circuit Using Half-Adder
Cin A B Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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 Adding Two One-bit Operands
• One-bit Full Adder Circuit Using Half-Adder

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N-Bit Ripple-Carry Adder: Series of FA Cells
• To add two n-bit numbers
An-1 Bn-1 A2 B2 A1 B1 A0 B0

Cn FA ... FA FA FA C0

Sn-1 S2 S1 S0

• Note: adder delay = Tc * n

A B
• Tc = (Cin:Cout delay)
Cout FA Cin

Sum
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 4-bit Ripple Carry Addition: Example
A=0011 0 0 0 1 1 0 1 1
B=0101 A3 B3 A2 B2 A1 B1 A0 B0

C4 C C C
FA FA FA FA C 0
3 2 1
0

S3 S2 S1 S0

T=0 0 0 0 0 0 0 0 0 S=0000
T=1 0 0 0 1 0 1 1 0 S=0110
T=2 0 0 0 1 1 0 1 0 S=0100
T=3 0 0 1 0 1 0 1 0 S=0000
T=4 0 1 1 0 1 0 1 0 S=1000

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 One-bit Full Adder Implementation
• Direct gate implementation
Sum = A ⊕ B ⊕ Cin Cout = A.B + B.Cin + A.Cin
= A.B + Cin. (A+B)
A A
B Sum B
Cin Cout
Cin
A
B

32 Transistors Used

[WE92] p516

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 One-Bit Full Adder: Share Logic
• An observation
Cin A B Sum Cout
▪ Almost always,
0 0 0 0 0
sum = NOT carry
0 0 1 1 0
0 1 0 1 0
includes 111 0 1 1 0 1
1 0 0 1 0
Sum = A.B.Cin + 1 0 1 0 1
(A+B+Cin).Cout 1 1 0 0 1
1 1 1 1 1
excludes
000

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One-Bit Full Adder: Transistor Implementation
Cout = A.B + C.(A+B) Sum = A.B.C + (A+B+C).Cout

C B A
A B 28 Transistors
A
B C B
A Cou C Su
m
C At C
A B B B
A B C A
– Use inverters to get Cout and Sum [WE92] p517
[Rab96] p390
– C transistors close to output
– Cout delay: 2 inverting stages (1-stage possible?)
– Sum delay: 3 inverting stages (not an issue, though)
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 Outline
• One-bit adder, basic ripple-carry adder
• Carry-Lookahead adders (CLA)
• Brent-Kung adder

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 Carry-Lookahead Adder: Idea
• New look: carry propagation
• Idea:
▪ Try to “predict” Ck earlier than Tc*k
▪ Instead of passing through k stages, compute
Ck separately using 1-stage CMOS logic
• Carry propagation: an example
Bit position 7 6 5 4 3 2 1 0

Carry 1 0 0 1 1 1 1
A 0 1 0 0 1 1 0 1 +
B 0 1 0 0 0 1 1 1

Sum 1 0 0 1 0 1 0 0
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 Carry-Lookahead Adder (CLA): One Bit
• What happens to the
A B Cin Cout
propagating carry in
bit position k? 0 0 - 0 (kill)
0 1 C C
0-propag kill 1 0 C C(propagat
ate
A B A 1 1 - 1e)
B
C Cout
(propagat
B p = A+B e)
(or A ⊕
B)
A A
B (generate
g = A.B
1-propaga genera ) [Rab96] p391
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 CLA: Propagation Equations
• If C4=1, then either:
▪ g3 generated at bit pos 3
▪ g2.p3 generated at bit pos 2, propagated 3
▪ g1.p2.p3 generated at bit pos 1, propagated 2,3
▪ g0.p1.p2.p3 generated at bit pos 0, propagated 1,2,3
▪ Cin.p0.p1.p2.p3 input carry, propagated 0,1,2,3
• C4 = g3+ g2.p3 + g1.p2.p3 + g0.p1.p2.p3 +
Cin.p0.p1.p2.p3

Implement C4 as a one-stage CMOS logic

 large delay

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 CLA: 12-Bit Example
A= 110 100 101
B= 011
1 011
1 110
0
A1 A1 A
1 A A A 0A A A A 1 A A
B1 B1 B B B B B B B B B B
1 0 9 8 7 6 5 4 3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0
p, p, p, p, p, p, p, p, p, p, p, p,
g g g g g g g g g g g g 0
C
Carry Carry Carry 0

Generator Generator Generator

C1 C C
2 S1 S1 S S 8 S S S S 4 S S S S

T=0 1 0 0 0009 8 7
0 6
0005 4 3
0 2 0001 0

0 0 0
T=2 1 010 0 111 1 011
0 1 1
T=3 1 010 1 000 1 011
0 0 1
T=4 1 010 1 000 1 011
1 0 1
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 Summary: Carry Lookahead Adder
• CLA compared to ripple-carry adder:
▪ Faster (“4 times”?),
but delay still linear (w.r.t. # of bits)
▪ Larger area
o P, G signal generation
o Carry generation circuits
o Carry generation ckt for each bit position (no re-use)
• Limitation: cannot go beyond 4 bits of look-ahead
▪ Large p,g fan-out slows down carry generation

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 Outline
• One-bit adder, basic ripple-carry adder
• Carry-Lookahead adders (CLA)
• Brent-Kung adder

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Binary Carry-Lookahead or Brent-Kung Adder
• Idea: use binary tree for carry propagation
🡺 logarithmic delay

A0 F

A1 A2 A3 A4 A5 A6 A7
tp ~ N
A0
A1
A2
A3
F
A4
A5
A6 tp ~ log2 (N
A7 ) Hall]
[© Prentice
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 Brent-Kung Adder
• Basic component

MS LS
B B
(gleft, pleft) (gright
glef plef grig prig pright)

t t ht ht
(g,
p)
g p
g = gleft + pleft •
gright
Concatenati p = pleft • pright
on [©Hauck]
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 Brent-Kung Adder: Structure
• Define (Gi, Pi)
▪ generate and propagate for least significant i bits
(G0,P0) = (g0,p0) gi = Ai.Bi pi = Ai⊕Bi
for i>0: (Gi, Pi) = (gi, pi) • (Gi-1, Pi-1)
= (gi, pi) • (gi-1, pi-1) • . . . . • (g1, p1)
• Key to Brent-Kung adder – use tree structure to
perform concatenations
7 6 5 4 3 2 1 0

C5 7-6 5-4 3-2 1-0

?
No! Doesn’t know 7-4 3-0
about
7-0 [©Hauck]
C yet! 30
 Brent-Kung: the Complete Tree
( 0 ,p0 )
C0 C2
C1 C4
g( 1 ,p1 )
g

( 2 ,p2 ) C3 C5
g( ,p )
3 3
g

( 4 ,p4 ) C6
g( 5 ,p5 )
g

( 6 ,p6 ) C7
g( ,p )
7 7
g

t ad ~ 2 (N) [© Prentice Hall]

d log 31
 Brent-Kung: Timing
x15 x14x13 x12 x x x x8 x x x x x x x x
11 10 9 7 6 5 4 3 2 1 0
Leve
1l

6
s15 s14 s13 s12 s s s s s s s s s s s s [Par00] p.102
11 10 9 8 7 6 5 4 3 2 1 0
[©Oxford U Press]
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 Brent-Kung Adder: Summary
• Area
▪ On average, twice as large as ripple adder
▪ Layout of the cells is very compact
• Delay
▪ Logarithmic time
▪ Once carry signals are ready,
sum bits derived in const time
▪ Good for wide adders

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Thank You

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