CHAPTER 4

Central Processing Unit

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Chapter 4 content

8-1 Introduction
8-2 General Register Organization
▪ bus system
▪ Control Word
▪ ALU
▪ Examples
8-3 Stack Organization
▪ Register Stack Organization
▪ Memory stack organization
▪ Reverse Polish Notation
8-4 Instruction Formats
▪ Processor Organization
▪ Three, Two, One, Zero Address Instructions
▪ Three-Address Instructions
▪ Two-Address Instructions
▪ One-Address Instructions
▪ Zero-Address Instructions

8-5 Addressing Modes

▪ Implied Mode
▪ Immediate Mode
▪ Register Mode
▪ Register Indirect Mode
▪ Autoincrement or Autodecrement Mode
▪ Direct Address Mode
▪ Indirect Addressing Mode
▪ PC Relative Addressing Modes
▪ Index Relative Addressing Modes
▪ Base Relative Addressing Modes
8-6 Data Transfer and Manipulation
▪ Data Transfer Instructions
▪ Data Manipulation Instructions
1. Arithmetic instruction
2. Logical and bit manipulation instructions
3. Shift instructions
8-7 Program Control

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8-1 Introduction

Major Components of CPU

Storage Components Registers
Flags

Processing Components Arithmetic Logic Unit (ALU)

▪ Arithmetic calculations
▪ Logical computations
▪ Shifts/Rotates

Transfer Components Bus

Control Components Control Unit

Registers
Storage
Components
Flags

Arithmetic
CPU

Processing
ALU Logical
Components
Transfer
BUS Shift/Rotate
Components
Control
Control Unit
Components

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8-2 General Register Organization

In Basic Computer, there is only one general purpose register, the Accumulator (AC) but in modern CPUs, there are many general-purpose registers.
‫ يوجد عدد اكبر من سجالت األغراض‬، ‫ ولكن في المعالجات الحديثة‬Accumulator (AC) ‫ وهو‬، ‫ يوجد سجل واحد فقط لألغراض العامة‬، Basic Computer ‫في ال‬
.‫العامة‬

It is advantageous to have many registers because Transfer between registers within the processor are relatively fast and Going “off the processor” to access memory is much slower.

‫ًا بينما "إيقاف تشغيل المعالج" للوصول إلى الذاكرة يكون‬

‫من المفيد أن يكون لديك عدد اكبرالسجالت ألن النقل بين السجالت داخل مباشراداخل المعالج سريع نسبي‬
.‫أبطأ بكثير‬

General register organization

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Operation of Control Unit

The control unit is Directs the information flow through ALU by
▪ Selecting various Components in the system.
▪ Selecting the Function of AL
‫ بواسطة‬ALU ‫ في تدفق المعلومات عبر‬control unit ‫تتحكم‬
.‫▪ اختيار المكونات التي ستعمل اثناء حدوث عملية معينة‬
ALU ‫▪ تحديد وظيفة‬

𝐄𝐱𝐚𝐦𝐩𝐥𝐞: 𝐑𝟏  𝐑𝟐 + 𝐑𝟑

[1] MUX A selector (SELA): BUS A  R2

[2] MUX B selector (SELB): BUS B  R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1  Out Bus

Control Word
3 3 3 5
SELA SELB SELD OPR

Encoding of register selection fields

❖ Encoding of ALU operations

Examples of ALU Microoperations

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8-3 Stack Organization

Stack Applications:
▪ Very useful feature for nested subroutines and nested interrupt services
▪ Efficient for arithmetic expression evaluation
▪ Storage which can be accessed in LIFO

Push, Pop operations

FULL= 1 when the stack is full

EMTY = 1 when the stack is empty

Initially:

SP = 0,
EMPTY = 1,
FULL = 0

PUSH POP
𝐒𝐏 ← 𝐒𝐏 + 𝟏 𝐃𝐑 ← 𝐌[𝐒𝐏]
𝐌[𝐒𝐏] ← 𝐃𝐑 𝐒𝐏 ← 𝐒𝐏 − 𝟏
𝐈𝐟 (𝐒𝐏 = 𝟎) 𝐭𝐡𝐞𝐧 (𝐅𝐔𝐋𝐋 ← 𝟏) 𝐈𝐟 (𝐒𝐏 = 𝟎) 𝐭𝐡𝐞𝐧 (𝐄𝐌𝐏𝐓𝐘 ← 𝟏)
𝐄𝐌𝐏𝐓𝐘 ← 𝟎 𝐅𝐔𝐋𝐋 ← 𝟎

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Memory stack organization

❖ Memory with Program, Data, and Stack Segments

❖ A portion of memory is used as a stack with a processor register as a stack pointer.

PUSH POP
𝐒𝐏  𝐒𝐏 − 𝟏 𝐃𝐑  𝐌[𝐒𝐏]
𝐌[𝐒𝐏]  𝐃𝐑 𝐒𝐏  𝐒𝐏 + 𝟏

❖ Most computers do not provide hardware to check stack overflow (full stack) or underflow (empty stack) → must be done in software

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Reverse Polish Notation

Arithmetic Expressions: A + B
Infix notation 𝐀 + 𝐁
Prefix or Polish notation +𝐀𝐁
Postfix or reverse Polish notation 𝐀𝐁 +

❖ The reverse Polish notation is very suitable for stack manipulation.

❖ Evaluation of Arithmetic Expressions
❖ Any arithmetic expression can be expressed in parenthesis free Polish notation, including reverse Polish notation.

Example:
(𝟑 ∗ 𝟒) + (𝟓 ∗ 𝟔) → 𝟑 𝟒 ∗ 𝟓 𝟔 ∗ +

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8-4 Instruction Formats

Processor organization

General register organization Single register (Accumulator) Stack organization

organization
Used by most modern computer processors Basic Computer is a good example All operations are done using the hardware stack

Any of the registers can be used as the source or Accumulator is the only general-purpose register For example, an OR instruction will pop the two top
destination for computer operations elements from the stack, do a logical OR on them, and push
the result on the stack

▪ Three-Address Instructions ▪ One-Address Instructions ▪ Zero-Address Instructions

▪ Two-Address Instructions

Label field Instruction field Comment field

❖ Instruction Fields

▪ OP-code field: specifies the operation to be performed.

▪ Address field: designates memory address(es) or a processor register(s)
▪ Mode field: determines how the address field is to be interpreted (to get effective address or the operand)

Mode field OP-code field Address field

The number of address fields in the instruction format depends on the internal organization of CPU

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‫على التركيب الداخلي للمعالج‬ instruction ‫يعتمد عدد حقول العنوان في ال‬

Three and two- one – zero Address Instructions

Three-Address Instructions Two-Address Instructions One-Address Instructions Zero-Address Instructions

ADD R1, R2, R2 ADD R1, R2 ADD X ADD

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8-5 Addressing Modes

Addressing Modes: Specifies a rule for interpreting or modifying the address field of the instruction (before the operand is actually referenced)

Variety of addressing modes

❖ to give programming flexibility to the user
❖ to use the bits in the address field of the instruction efficiently

Types of Addressing Modes

Implied Mode Implied Mode: Address of the operands are specified implicitly in the
definition of the instruction No EA
AC=
• No need to specify address in the instruction

Immediate Mode No EA
Immediate Mode: Instead of specifying the address of the operand, operand
itself is specified AC=immediate filed in instruction

• No need to specify address in the instruction

• However, operand itself needs to be specified
• Sometimes, require more bits than the address
• Fast to acquire an operand

𝐄𝐀 = 𝐈𝐑(𝐑) 𝐈𝐑(𝐑): 𝐑𝐞𝐠𝐢𝐬𝐭𝐞𝐫 𝐟𝐢𝐞𝐥𝐝 𝐨𝐟 𝐈𝐑

Register Mode No EA
Register Mode: Address specified in the instruction is the register address AC = R

• Designated operand need to be in a register

• Shorter address than the memory address
• Saving address field in the instruction
• Faster to acquire an operand than the memory addressing

Register Indirect EA=R

Register Indirect Mode: Instruction specifies a register which contains the
Mode memory address of the operand
AC = [R]

• Saving instruction bits since register address is shorter than the memory address
• Slower to acquire an operand than both the register addressing or memory
addressing

Autoincrement EA=R
Autoincrement or Autodecrement Mode: When the address in the register is
Mode used to access memory, the value in the register is incremented or
AC = [R]
R=R+1
decremented by 1 automatically

The auto-increment mode R1 is incremented after the execution of the instruction.

The auto-decrement mode R1 is decremented before the execution of the instruction. R=R-1
Autodecrement EA=R
Mode AC = [R]

Direct Address Mode : Instruction specifies the memory address which can
Direct Address be used directly to access the memory EA= Address filed in instruction
Mode AC = [EA]
• Faster than the other memory addressing modes
• Too many bits are needed to specify the address for a large physical memory space

EA= [Address filed in instruction]

Indirect Addressing Mode e: The address field of an instruction specifies the
Indirect address of a memory location that contains the address of the operand
AC = [EA]

Addressing Mode
• When the abbreviated address is used large physical memory can be addressed with a
relatively small number of bits
• Slow to acquire an operand because of an additional memory access

Relative
Relative Addressing Mode e: The Address fields of an instruction specifies the
Addressing Modes part of the address (abbreviated address) which can be used along with a
3 different Relative Addressing Modes depending on R;
designated register to calculate the address of the operand PC Relative R = PC EA = PC + IR(address)
Addressing Mode
• Address field of the instruction is short Indexed Addressing R = IX, EA = IX + IR(address)
• Large physical memory can be accessed with a small number of address bits Mode 𝑤ℎ𝑒𝑟𝑒 𝐼𝑋: 𝐼𝑛𝑑𝑒𝑥 𝑅𝑒𝑔𝑖𝑠𝑡𝑒𝑟
Base Register R = BAR, EA = BAR + IR(address)
Addressing Mode 𝑤ℎ𝑒𝑟𝑒 𝐵𝐴𝑅: 𝐵𝑎𝑠𝑒 𝐴𝑑𝑑𝑟𝑒𝑠𝑠 𝑅𝑒𝑔𝑖𝑠𝑡𝑒𝑟

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Addressing Mode EA (Effective Address) AC

1. Implied Mode

2. Immediate Mode AC= 𝐀𝐝𝐝𝐫𝐞𝐬𝐬

3. Register Mode AC = Register

4. Register Indirect Mode EA=R AC = [EA]

5. Autoincrement Mode EA=R AC = [EA]

R=R+1

Opcode Mode Address

6. Autodecrement Mode R=R-1 AC = [EA]

EA= R

7. Direct Address Mode AC = [EA]

EA= 𝐀𝐝𝐝𝐫𝐞𝐬𝐬

8. Indirect Addressing Mode AC = [EA]

EA= [ 𝐀𝐝𝐝𝐫𝐞𝐬𝐬 ]

9. PC Relative Addressing Mode 𝐑 = 𝐏𝐂 AC = [EA]

𝐄𝐀 = 𝐑 + 𝐀𝐝𝐝𝐫𝐞𝐬𝐬

10. Indexed Relative Addressing Mode 𝐑 = 𝐈𝐗 AC = [EA]

𝐄𝐀 = 𝐑 + 𝐀𝐝𝐝𝐫𝐞𝐬𝐬

11. Base Relative Addressing Mode 𝐑 = 𝐁𝐀𝐑 AC = [EA]

𝐄𝐀 = 𝐑 + 𝐀𝐝𝐝𝐫𝐞𝐬𝐬

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Addressing Mode EA (Effective Address) AC

1. Implied Mode 𝐂𝐋𝐀

𝐂𝐌𝐀

all register reference instructions

Zero-address instructions in a stack-organized computer

2. Immediate Mode AC= 𝐢𝐦𝐦𝐞𝐝𝐢𝐚𝐭𝐞

3. Register Mode AC = Register LDA A

all Memory reference instructions

4. Register Indirect Mode AC = [EA]

EA=R

Opcode Mode Address / immediate

5. Autoincrement Mode EA=R AC = [EA]

R=R+1

6. Autodecrement Mode R=R-1 AC = [EA]

EA= R

7. Direct Address Mode AC = [EA] ADD X

EA= 𝐀𝐝𝐝𝐫𝐞𝐬𝐬

ADD X I
8. Indirect Addressing Mode AC = [EA]
EA= [ 𝐀𝐝𝐝𝐫𝐞𝐬𝐬 ]

9. PC Relative Addressing Mode 𝐑 = 𝐏𝐂 AC = [EA]

𝐄𝐀 = 𝐑 + 𝐀𝐝𝐝𝐫𝐞𝐬𝐬

10. Indexed Relative Addressing Mode 𝐑 = 𝐈𝐗 AC = [EA]

𝐄𝐀 = 𝐑 + 𝐀𝐝𝐝𝐫𝐞𝐬𝐬

11. Base Relative Addressing Mode 𝐑 = 𝐁𝐀𝐑 AC = [EA]

𝐄𝐀 = 𝐑 + 𝐀𝐝𝐝𝐫𝐞𝐬𝐬

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8-6 Data Transfer and Manipulation

Instructions

Data Transfer Instructions Data Manipulation Instructions Control Instructions

Logical and bit

Arithmetic Shift
manipulation
instruction instructions
instructions

Data Transfer Instructions

Data Transfer Instructions with Different Addressing Mode

Data Transfer Data Manipulation Instructions

Instructions

Arithmetic instruction Logical and bit manipulation Shift instructions

instructions

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