Pictorial Introduction To Using Cadence & Subversion - Circuit Design
Pictorial Introduction To Using Cadence & Subversion - Circuit Design
Just hit OK
Do a status on the command-line
1 [wagh@porthos CDSVN]$ svn st
2 ? libManager.log.1
3 ? libManager.log.1.cdslck
4 A shared_design/top_level
5 A shared_design/top_level/schematic
6 A shared_design/top_level/schematic/sch.cdb
7 A shared_design/top_level/schematic/master.tag
8 A shared_design/top_level/schematic/pc.db
9 A shared_design/top_level/schematic/prop.xx
Check in
1 [wagh@porthos CDSVN]$ svn ci -m "Adding shared_design"
2 Adding shared_design/top_level
3 Adding shared_design/top_level/schematic
4 Adding shared_design/top_level/schematic/master.tag
5 Adding shared_design/top_level/schematic/pc.db
6 Adding (bin) shared_design/top_level/schematic/prop.xx
7 Adding (bin) shared_design/top_level/schematic/sch.cdb
8 Transmitting file data ....
9 Committed revision 3.
Check in again
1 [wagh@porthos CDSVN]$ svn ci -m "Added another resistor"
2 Sending shared_design/top_level/schematic/pc.db
3 Sending shared_design/top_level/schematic/prop.xx
4 Sending shared_design/top_level/schematic/sch.cdb
5 Transmitting file data ...
6 Committed revision 4.