Introduction to VLSI Design

P Narashimaraja
Aug 2019

1 Introduction
This chapter discusses 4 major sub topics, namely, 1. VLSI Design flow, 2. MOSFET Operation, 3. Non-
ideal effects in MOSFET, and 4. DC characteristics. We begin this chapter with the discussion VLSI
design flow, where we first discuss some common terminologies that are used in the development of VLSI
design flow. Later we discuss about about different types of MOSFET structures and it’s operation. This
is followed by the non-ideal characteristics of MOSFET, where we emphasis the deviation of an ideal
behavior due to shortening of channel length, despite it’s advantage towards miniaturization and speed.
And the last subtopic gives some insight into the operation of a CMOS Inverter and pass-transistor under
static input condition.

2 History & VLSI Design flow

We begin with the brief history about VLSI Design and we discuss about some of the common termi-
nologies that are used in the development of VLSI design flow. This is followed by VLSI Design flow,
where we try to understand how a user specification gets converted into an Integrated Circuit (IC) chip.
So with no further due, we start with the History.

2.1 History
It was till 1950’s the electronic active device technology was dominated by Vacuum tubes.

2.2 VLSI Design flow

This subsection gives us a overall view of about ASIC design flow, where we try to answer the following
basic questions:
1. How a code that is written using some HDL gets converted into a hardware?

2. What is meant by Standard cell library?

3. What is meant by Functional & Timing Simulation?
4. How to get an IC chip using this flow?

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Introduction to VLSI Design Unit 1

Design Specification

NO (1st iteration)
NO (1st iteration)
Design Entry: Planning Placement Timing simulation
HDL / Schematic Entry and Routing PPR and Timing Analysis

Functional Simulation Timing

/Logical verification spec met?
Design Routed?

yes
yes
Functionally
Fusing / Fabrication into chip
Correct? yes
NO (if 1st iteration fails)

Figure 1: VLSI Design flow

2.2.1 Specification
In general, to design a chip, the following specifications are important under different circumstances.
• Algorithm in detail with mathematical representation

– Gives the complexity of the design

– Gives an idea of the number of gates required
• Number of I/Ps & O/Ps in the design and number of bits in each of them
– Gives the type of interface used. Eg., data lines, control lines.
– Number of pins used in the chip
• Number of bits used in the internal arithematic operation
– In general, this is kept higher than the number of I/P bus size
- to avoid chances of overflow and underflow
- to reduce the round-off errors to the required accuracy.

• Number of clock signal used in the design

– Since clock routing requires dedicated channels to avoid second-order effects like cross-talk ⇒
considered during the fabrication of the chip.
• Maximum clock frequency to be used
– Defines the speed of operation of the chip
– Important: If the chip - interfaces with very high speed (or) - needs to perform real time
complex computation
• Area of the chip
– For a portable system

• Power dissipation of the chip

– Portable system - requires power efficient devices

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2.2.2 Design entry

In design entry, Architectural decisions are taken first.
-Like

• # of sub-blocks [adders, multipliers, dividers] and

• their interconnects [serial, parallel],
• whether requires pipelining,

– # of pipeline stages and

– operation in each stages.
There are two types of design entry:
• Schematic entry

• HDL entry
Design Entry - Schematic entry:
Schematic entry uses hierarchical design approach and needs cell library
• Larger designs are sub-divided into sub-designs, further into sub-blocks

• Higher sub-blocks are built using primitive cells & Macros -from cell library

Schematic Library

♣
Macro

Figure 2: Schematic Library

Design Entry - HDL entry:

The dominant HDLs: VHDL & Verilog
A digital system can be expressed in one of the 3 forms, namely:
• Structural - involves component instantiation & their interconnections
• Dataflow - involves concurrent statements

• Behavioral - - involves sequential statements

2.2.3 Functional simulation

• Done before design implementation
• Verifies that the logic created using either of the Design entry method provides the desired func-
tionality.

• Gate delays and net delays are not considered

In short, only logical functionality is verified.

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2.2.4 Planning Placement and Routing

This part refers to Physical design (or) Layout phase.
Involves 2 steps:
• Determining the physical location of devices/block
• Interconnecting them
Basically driven by a set of constraints:
• Minimize chip area
– Reduces the cost
– Fewer defects
– Increases the yield
• Minimize wire length
• Other constraints: Minimize delay, power, via
Layout Methodologies
• Partitioning
– Dividing a circuit into smaller parts
• Floorplanning
– Determination of the approximate location of each module in a rectangular chip area
– Shape of each module and pin locations may also be determined

a f
b a
cut c
c f
d
e
g
e
b d

(a) Example: Circuit partitioning (b) Example: Floorplanning

Figure 3: Planning and Floorplan

All of these can be achieved by using CAD tools.

Next, we discuss about Placement and Routing
• Placement
– Determination of the best position for each module
• Routing
– Interconnects different components
– Constraints: minimize - Chip area & total wire length
– Global routing
∗ Partitioning routing region into a collection of disjoint rectilinear subregions
∗ Assignment of subregions to net, finding out rough path
– Detailed routing

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∗ Realization of interconnections in subregions

b a b a

c c

d f d f

e g e g

(a) Placement (b) Routing

Figure 4: Illustration of Placement and Routing process

2.2.5 Timing simulation

Timing simulation:

• Done after successful PPR

• Functional Vs Timing simulation

– Function sim.: verifies only logical
functionality Figure 5: Timing simulation
– Timing sim.: includes gate delays &
net delays along with functional verifi-
cation
• Constraints: Timing/Speed specification
• Gives an idea of Max. clk. freq. for a
given routed design

2.2.6 Fusing/Fabrication into chip

Chip fabrication: 2 design styles

• Full Custom

– ASICs - designed specifically for a cer-

tain application
– Hand-crafted at transistor levels -
Yields optimal area & performance

• Semi custom
Figure 6: Standard cells layout
– Cell based design - uses library of
pre-designed cells
– Array based design - uses pre-
fabricated matrix of non-connected
components
-Eg. FPGA

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3 MOSFET
We know from basic electronics, that the MOSFETs are majority carrier device and are called uni-polar
device.
Based on the construction one can categories the MOSFET as
• Enhancement mode - No channel by default.

• Depletion mode - Channel exist under zero bias.

Among these 2 types, the Enhancement mode MOSFETs are the most widely used transistor in digital
IC designs.

Also, based on Majority carriers one can classify the MOSFET as

• n-type MOS [NMOS]
• p-type MOS [PMOS]

Note
We will use nmos as the default transistor throughout this chapter - until otherwise it is stated.
So an nmos transistor has a p-type semiconductor and doped with acceptor concentration, NA .

3.1 MOS structure

The behavior of Metal-Oxide-Semiconductor (M-O-S) structure under different biasing condition is re-
flected in the Fig.7.

When the Vg < 0, the majority charge carriers in-

side the p-type material, accumulates more at the
Oxide-Semiconductor (O-S) interface. The same
is reflected in Fig.7.(a).
When the gate terminal is biased within the
range, 0 < Vg < VT , the positive charge carriers
at the Metal-Oxide (M-O) interface fires the holes
away from O-S interface - leaving behind negative
ions. Since ions are immobile, they create deple-
tion at this interface as shown in Fig.7.(b).
Finally when the gate terminal is biased above
Vg > VT , the positive carrier concentration at the
M-O interface becomes so high, such that they
start attracting the minority carriers, electrons
from the p-type bulk towards the interface. These
negative charges inverts the material from p-type
to n-type at the O-S interface, as shown in
Fig.7.(c). Figure 7: Channel condition under different bias

3.2 MOSFET region of operation

First, we begin with the discussion of nmos transistor region of operation. We know that there are 3
regions in which the MOS device can be operated.
. VGS VDS

• Cutoff ≤ VT NA
• Linear > VT < VGS − VT
• Saturation > VT ≥ VDSat

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(a) Cutoff (b) Linear (c) Saturation

Figure 8: Illustration - nMOS Regions of operation

Also, the characteristic graphs of nmos transistor is shown in Fig.

IDS (mA) IDS (mA)

Vds
1

0.8

0.6

0.4
0.2
0
VGS (V ) VDS (V )

(a) Transfer characteristics (b) Output characteristics

Figure 9: Characteristic plots of nMOS

In the similar way, one could study the behavior of pmos transistor. It’s region of operation is
. VGS VDS
• Cutoff ≥ VT NA
• Linear < VT > VGS − VT
• Saturation < VT ≤ VDSat

Example 3.1:

Consider an nMOS transistor in a 65 nm process with a minimum drawn channel length of 50

nm (λ = 25nm). Let W/L = (4/2)λ. In this process, the gate oxide thickness is 10.5Å and the
estimated high-field mobility of electrons to be 80 cm2 /V · s at 70◦ C. The threshold voltage is
0.3V .
Calculate the value of βn .

F
 
W

cm 2
 3.9 × 8.85 × 10−14
β = µCox = 80
 cm 
 (2 × 25nm) =
L V ·s 10.5 × 10−8 cm


A
1.31485 × 10−11 .
V2

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4 CV characteristics
Before we discuss about the MOS capacitance, we begin with the understanding of Flat band voltage.
It is not necessary, but advised to look at some potential and field profile of M-O-S structure. A brief
explanation is attempted in Appendix.??.

4.1 Flat band voltage

This is a special potential, like threshold voltage, that exist when the fermi-levels between Metal and
Semiconductor are different under equilibrium in M-O-S structure. To understand the physical meaning
of this voltage, we have to look at the energy band diagram of the structure. Also, one can use the Fig.7
as a reference for the complete discussion under this topic.
We know from basic science that the energy gap of a dielectric medium is high compared to an
undoped semiconductor material. One can make a semiconductor material to act as a conductor by
doping appropriate impurities, which then shifts their fermi energy level closer to conduction/valence
band. In the case of a metal, there is no band gap and both the conduction and valence band are merged
together. The same is reflected in Fig.10.
Note that the fermi-levels of p-type and Metal layers are not aligned, due to which, when they are
brought in contact with each other, the fermi - level of semiconductor tries to align with the fermi - level
of the metal. During the alignment process, the energy bands of p-type material tries to retain it’s initial
relation at the interface(due to continuity requirement). Because of which, the holes are repelled away
from the O-S interface.
Oxide
Metal

p-Type

Eo : Vaccum energy
EC : Conduction band energy
EV : Valence band energy
E0 EF : Fermi energy
Ei : Intrinsic energy
χ ϕ: Work function
EC
ϕM χ: Electron affinity
ϕS
EC

EF m Ei
EF s
EV

EV

Figure 10: Energy band diagrams for MOS structure

Note
The above concept is shown as an animation in the following Fig. Use Acrobat reader to run
the animation.

Figure 11: Animation that reflect the Band bending

Now let’s look at the definition of Flat-band voltage.

Definition of Flat-band voltage

It is the voltage required across this M-O-S structure to flatten the bands.

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Now the question is, ”Whether this potential is a +ve or -ve value?”
To answer this, let’s look at the charge distribution across the M-O and O-S interfaces. As you could
absorb that the removal of holes at O-S interface has left behind immobile -ve ions at the interface. Due
to charge neutrality condition, one has to have equivalent and opposite charges on the other side of the
oxide (on the metal). Since because the fields inside metal is zero, all these extra charges has to be only
on the surface of the metal. The same is depicted in the Fig.
Oxide
Metal

p-type ρ(x)

+ = represents immobile ions

+
= mobile charge carriers
QG
+

+ 0 0
−tox - - - x x
−tox

(a) Charge distribution (b) Charge density representation

Figure 12: Charge distribution and density across MOS interface

As it is evident from the above Fig. that in order to make the bands flat, one has to remove the
positive charges at the M-O interface. We know that opposite charges attract each other, due to the
same reason one has to apply a negative potential w.r.t body terminal. This eats up all the holes at the
M-O interface.
Potential Vs Energy

A negative potential lowers the fermi energy level of metal, whereas a positive potential increases
the fermi energy level.

So based on the above concept, the fermi-level of metal, EF,m , gets lowered when a negative gate
voltage is applied. Due to the same reason said above, the Fermi-level of semiconductor will then try to
align with the Fermi-level of metal. Thus achieving a Flat band structure. This phenomena is illustrated
in the following animated Fig.

Figure 13: Animation explaining flat band voltage

and the corresponding charge distribution is shown in Fig.

Oxide
Metal

p-type ρ(x)

0 0
−tox x x
−tox

(a) Charge distribution (b) Charge density representation

Figure 14: Charge distribution and density across MOS interface at VF B

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Definition of Flat band voltage

It is the voltage when applied across M-O-S structure, makes the energy band of semiconductor
straight.

4.2 Intrinsic capacitance

Now it’s time to study the behavior of M-O-S structure’s capacitance. As stated earlier in Eq.??, the
capacitance in MOS theory is always measured as small-signal quantities. So let’s add a small-signal
across the M-O-S structure under different biasing conditions as shown in Fig.

vgs

p-Type
VGB

Figure 15: MOS structure basied with VGB and excited with small-signal vgb

Thus the capacitance is calculated based on the following relation

dQg qg
C(VGB ) = = (1)
dVgb VGB vgb

where Qg = QG + qg and Vgb = VGB + vgb .

The expression suggest us that, one can bias this M-O-S structure by applying suitable DC value
to VGB - such that the structure is biased in one of the region, namely 1. Accumulation, 2. Depletion,
and 3. Inversion . Once the bias voltage is fixed though VGB , it set the appropriate charge condition
across Metal and Semiconductor. Now it’s time to compute the value of capacitance, by applying a
small incremental change over the biased voltage, through vgb . This small wiggle results in change in the
value of gate charge qg , thus the value of capacitance is measured. We call this capacitance as Intrinsic
capacitance, and the reason for using such a naming convention will becomes evident at the end of this
section.

4.2.1 Accumulation
In order to create accumulation of holes at the O-S interface, one has to deposit electrons on the surface
of M-O interface - to satisfy charge neutrality. So to achieve this, the value of VGB should be more
negative than the Flat band voltage (VF B ). This condition is reflected in the Fig.(a). Now when a
positive small-signal is applied over the biased M-O-S structure, it reduces the negative charges at the
M-O interface and the same is reflected in Fig.(b).

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ρ(x) VGB < VF B < 0

0
QG ρ (x) Vgb = VGB + vgb

tox Qg

x tox
x

−QG −Qg = QG + qg

(a) Charge density due to VGB = −V < −VF B (b) Charge density due to Vgb = VGB + vgb

Figure 16: Charge density of MOS biased under Accumulation

As given in Eq.1, in order to extract the capacitance of M-O-S structure biased under Accumulation
region, one has to extract the difference in charge densities - when biased at VGB and Vgb . The difference
in charges gives us, dQg = Qg − QG - a negative value but since the charges at the gate terminal are
negative, it creates an effective positive charge representation. This is reflected in Fig.

0
ρ(x) ρ (x) ∆ρ(x) qg = Qg − QG

QG

Qg
qg
Cacc = Cox
tox tox +qg

x x x
tox −qg

−Qg = QG + qg −qg

−QG

Figure 17: Capacitance computation in Accumulation

The charge increment on the gate is mirrored in the accumulated holes under the oxide/substrate
interface. Thus the capacitance in accumulation is expressed as
qg ox
Cacc = = = Cox [F/m2 ] (2)
vg tox

4.2.2 Depletion
Now let’s switch the VGB value between the range 0 < VGB < VT . The charge distribution is reflected
in Fig.

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0 ∆ρ(x) qg = qG − QG
ρ(x) 0 < VGB < VT ρ (x) vGB = VGB + vgb

qG = QG + qg +qg
QG

Cox
0
0 qg XdXd
X
Xd d
Cb
Xd x
x x tox −qNA
tox −qNA tox −qNA
0 0
−qg
−QG = −qNA Xd −QG = −qNA Xd −qNA (Xd − Xd )

Figure 18: Capacitance computation in Depletion

The gate charge increment is mirrored at the bottom of the depletion region. The incremental
charges +qg and –qg are separated by an oxide layer of thickness tox with capacitance Cox = ox /tox and
a depletion region of thickness Xd (VGB ) with capacitance s /Xd (VGB ).
The capacitance in depletion region is expressed as
1
Cdep = = Cox k Cb [F/m2 ] (3)
1 1
+
Cox Cb

4.2.3 Inversion
Under inversion, the p-type material get’s inverted into n-type material at the O-S interface. Also
under inversion, the depletion region attains a maximum width under O-S interface. So any incremental
changes applied to the bias voltage, VGB , will not alter it’s width further, but only alters the inverted
layers width.
Since the inverted region is composed of mobile negatively charged carriers, they are represented as
arrow lines rather than rectangular boxes in the Fig.

0
ρ (x) vGB = VGB + vgb

ρ(x) VGB > VT qG = QG + qg

∆ρ(x) qg = qG − QG

QG

Xd,max

Xd,max
x Cinv = Cox
−tox −qNA +qg +qg
x
−tox −qNA QB,max = −qNA Xd,max x
QB,max = −qNA Xd,max
−tox −qg −qg
QN qN = QN − qg

Figure 19: Capacitance computation in Inversion

The capacitance in inversion can be expressed as

qg ox
Cinv = = = Cox [F/m2 ] (4)
vg tox

Now when we combines the CV characteristics of all 3 regions, one would end up with a characteristics
shown in Fig.(a). Also one could note from Fig.(b), that the value of gate charge, qg is constant w.r.t
Vgb in both Inversion and Accumulation region of operation - which gives a constant gate capacitance
in these regions. Whereas in the Depletion region, one could note that qg varies non-linearly w.r.t to Vgb
- due to increase in dielectric medium2 .
2 considering depletion region as non-conducting medium, it is referred as dielectric in this context.

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Cg
C0 qG

n
io
rs
ve
in
n
l e tio
dep

vGB (V )

n
io
0

at
ul
m
0

cu
Vgs

ac
-1 VF S 0 Vt 1
(a) MOS capacitance w.r.t Vgb (b) Charge variation w.r.t Vgb

Figure 20: CV characteristics of MOS structure

Use of C-V characteristics

MOS C-V Characteristic measurements are a commonly used method of determining gate oxide
thickness, substrate doping concentration, flat-band voltage and threshold voltage

4.3 Detailed MOSFET capacitance model

In the previous subsection, we considered only M-O-S capacitance. Here we will look at MOSFET, which
includes the M-O-S structure along with the Source and Drain diffusion - which are made of n-type
material. The inclusion of these structures in parallel with M-O-S gives rise to 2 types of capacitances:
1. Gate capacitance.
2. Diffusion/Parasitic capacitance.
Let’s look at them in detail in the following subsections.

4.3.1 Gate capacitance

In the simplified MOS capacitance model, the Gate capacitor can be viewed as a Parallel plate ca-
pacitor
- Necessary to attract charges to invert the channel

Cg = Cox W L (5)
Cg is a good capacitance, since high Cg is required - to obtain High IDS .
Note
The Bottom plate is a channel & Not connected to the terminal.

In reality, the Gate capacitance, Cg , has 2 components:

• Intrinsic capacitance Cgc (Over the channel)

• Overlap capacitance Cgol (to the Source and Drain)
Intrinsic capacitance:

The previous definition of gate capacitance Cg is used for the definition of intrinsic capacitance Cgc .
Since the bottom plate depends on the mode of operation of the transistor, we will define a capacitive
term, C0 and is defined as
C0 = Cox W L [F ] (6)

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As stated, since the bottom plate depends on the mode of operation of the transistor, Cgc has 3 compo-
nents:
• Cgb (gate-to-channel)

• Cgs (gate-to-source)
• Cgd (gate-to-drain)
The Cgc can be expressed as
Cgc = Cgs + Cgd + Cgb (7)
These capacitances are defined in terms of C0 , depending on the mode of operation of the MOSFET.
The Table.1 could be understood with the help of Fig.7.

Table 1: Approximation for intrinsic MOS gate capacitance

Parameter Cutoff Linear Saturation

Cgb ≤ C0 0 0
2
Cgs 0 C0 /2 C0
3
Cgd 0 C0 /2 0
2
Cg = Cgs + Cgd + Cgb C0 C0 C0
3

Note that in saturation region, near the drain terminal the channel gets pinched-off and due to which
2
Cgd = 0 and the channel contains only 2/3 of the charge carriers in it. This gives rises to Cgs = Cox .
3
The same is plotted in Fig., one w.r.t Vgs and the other w.r.t Vds .

(a) Cg Vs Vgs (b) Cg Vs Vds

Figure 21: CV characteristics of MOSFET

Overlap capacitance:

This capacitance exist due to overlap of source/drain and gate terminals - caused during fabrication
process. The same is displayed in Fig.

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Figure 22: Overlap capacitance

This overlap capacitance is expressed as

Cgs(overlap) = Cgsol · W
(8)
Cgdol(overlap) = Cgdol · W

Typical values are Cgsol = Cgdol = 0.2–0.4f F/µm.

Note
The overlap capacitance is bias independent - means that they stay constant irrespective of
Source/Drain potentials.

4.3.2 Diffusion capacitance

In addition to the Gate capacitance, the Source & Drain diffusion layers have capacitance, Csb & Cdb ,
around them - due to reverse biased pn junction between S/D and body. Hence called Diffusion
capacitance.

Electron Donor ion Acceptor ion Holes

n p
Majority
+ + + + + - - - - -

+ + + + + - - - - -
carriers nn pp
+ + + + + - - - - -

+ + + + + - - - - -
Minority pn np
+ + + + + - - - - -
carriers
n-Type p-Type
xn xp
(a) Depletion region at the interface (b) Charge distribution

Figure 23: PN junction and it’s charge density profile

Where,
n2i
nn : Concentration of electrons on n-side ≈ ND pn : Concentration of holes on n-side ≈
ND
n2i
np : Concentration of electrons on p-side ≈ pp : Concentration of holes on p-side ≈ NA .
NA
Note that the Csb , Cdb are Bad Capacitances, since they are Not fundamental to the operation of
the device. So it is also called Parasitic capacitances.
Now let’s try to understand it’s behavior w.r.t variation in S/D potential. Based on the above Fig.,
it’s pretty clear that the diffusion width varies as a function of the potentials at S/D terminal. This
leads to voltage dependent capacitance.
One can express the parasitic capacitance
based on Fig.24. As you could observe that the
Source/Drain diffusion are sounded by both at

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bottom and sides, one can express this capaci-

tance in terms of 1. Bottom plate capacitance, and
2. Side wall capacitance .
The capacitance depends on both the area AS and
sidewall perimeter PS of the source diffusion re-
gion. Based on the geometry illustrated in Fig.24,
one can express the area as AS = W D and the
perimeter as 2W +2D. Of this perimeter, W abuts
the channel and the remaining W + 2D does not.
So it is redefined as P S = W + 2D.
Thus the total diffusion capacitance is

Csb = AS × Cjbs + P S × Cjbssw

Where the bottom plate capacitance is expressed as

 −MJ
Vsb
Cjbs = CJ 1+
φ0

and the side-wall capacitance as

 −MJSW
Vsb
Cjbssw = CJSW 1+
φ0

MJ is the junction grading coefficient, typically in the range of 0.5 to 0.33 depending on the abruptness
of the diffusion junction.

Here, the φ0 denotes the built-in potential across the PN junction that depends on doping level and
it can be expressed as
NA ND
φ0 = ϑT ln
n2i

5 Non-Ideal IV Effects
For channel lengths (L) > 1µm: Long- channel IV model that is discussed before is valid. But, for
L < 1µm: Long- channel IV model is NOT valid. So these devices are called short channel devices
and they experience the following effects:

1. Velocity saturation effect 6. DIBL

2. Mobility degradation 7. Sub-threshold conduction
3. Channel length modulation 8. Gate leakage
4. Body effect 9. Junction leakage

5. Short channel effect 10. Mobility & VT H variation w.r.t Temp.

Note that throughout the entire discussion we consider nMOS structure by default, until otherwise it is
stated explicitly. Now let’s study these effects in detail.

5.1 Velocity saturation effect

It’s an effect that happens due to high lateral electric field across Source and Drain terminals. Consider
that the terminals are aligned along the x-axis as shown in Fig.25. One can express this field quantity
based on the gradient of a scalar potential as
→
−
E =∇·φ (9)

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and for the configuration shown in Fig.25, the above equation can be rewritten as

ZL ZL
dφ(x) VDS
EL = ⇒ EL · dx = dφ(x) ⇒ EL (L − 0) = φ(L) − φ(0) = VDS ⇒ EL = (10)
dx L
0 0

n+ n+
x
0 p-type L

Figure 25: nMOS 2D structure

One can express the drift velocity of the charge carriers across the channel as

vD = µn EL (11)

Where µn represents the mobility of free electron.

The expression for vD represents a linear relation between field and velocity and it can be graphed
with a straight line with a slope µn .
First we will derive the long channel current expression:
Vds
w.k.t drift velocity, vD = µE and E = , so the current in deep triode region is given by
L
Qch Qch Cox W L(Vgc − Vt )
Ids = = =
t L/vD L2 /µVds

where, t - represents the time required for carriers to cross the channel and Vgc - represents the average
gate to channel potential.
   
Vs + Vd Vs + Vd Vs Vs Vds
Vgc = Vg − Vc = Vg − = Vg − + − = Vgs −
2 2 2 2 2

on substituting the above expressions

 
Cox W L(Vgc − Vt ) W Vds
Ids = = µCox Vgs − Vt − Vds (12)
L2 /µVds L 2

The above expression is valid only for channel lengths L > 1µm. But for channel lengths that are
small, it creates a large value of EL across the channel, even for a moderate value of VDS . In the
velocity saturation, there exist a critical electric field, EC , above which it ceases the carrier velocity from
increasing linearly with EL . This can be graphed as shown in Fig.26.

Figure 26: Velocity saturation effect

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Velocity saturation effect

This phenomena happens due to the following

• Collusion and

• Increase in effective mass of the charge.

Due to this phenomena, one has to modify the drift velocity expression as
µn E


 for E ≤ Ec
 E
vD = 1 + (13)

 Ec
vsat for E > Ec


The continuity requirement between 2 regions - dictates:

2vsat
Ec = (14)
µn
Now let’s reevaluate the linear region drain current, which experiences
 velocitysaturation effect. This
Vds
can be done by replacing just the µn of long channel MOS with µn / 1 + .
EC L
 
µn W Vds
ID =   Cox Vgs − Vt − Vds
Vds L 2
1+
EC L (15)
 
W Vds
= κ(Vds )µCox Vgs − Vt − Vds
L 2
1
where κ(V ) = - measures Degree of velocity saturation, since Vds can be interpreted
1 + (V /Ec L)
as the avg. field in the channel.
• For long channel (OR) small values of Vds
κ → ”1”
• For short channel and high values of Vds
κ < ”1”
- means the delivered Ids is smaller than expected.
Now let’s reevaluate the saturation region drain current. We will adopt 2 methods to derive the current
in saturation region
1. By substituting Vds = Vdsat
It’s quite similar to long channel saturation current derivation, but instead of Vds = Vgs − Vt we
have Vds = Vdsat , assuming Vdsat 6= Vgs − Vt .
The proof of this assumption will be done at the end.
Qch L
2. Using Ids = , where t = and vsat is assumed to be constant in saturation and doesn’t
t vsat
depend on E ≥ Ec
The above discussion results in 2 expressions for ID in saturation region:
 
W Vdsat
ID = κ(Vdsat )µCox Vgs − Vt − Vdsat (16a)
L 2
= vsat Cox W (Vgs − Vt − Vdsat ) (16b)

Now let’s solve for Vdsat in terms of Vgs − Vt and prove that Vdsat 6= Vgs − Vt . This can be done by
1 2vsat VC
equating both the expressions and by substituting κ(Vdsat ) =   & EC = ⇒ =
Vdsat µn L
1+
VC

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2vsat µn VC
⇒ vsat = .
µn 2L
 
W
 Vdsat
W (Vgs − Vt − Vdsat ) = κ(Vdsat )µ Vgs − Vt −

vsat 
Cox 
  Cox
 Vdsat
L 2
 
µVC 1 1 Vdsat
 (Vgs − Vt − Vdsat ) =  µ Vgs − Vt − Vdsat
2
L Vdsat   L 2
1+
VC
 
V
C (V − V − V
 VC
 Vdsat
gs t dsat ) =
 Vgs − Vt − Vdsat
2 (VC + Vdsat ) 2
2 2
(17)
(Vgs − Vt )VC + (Vgs − Vt )Vdsat − Vdsat VC −   = 2(V − V )V
Vdsat gs t dsat − Vdsat

(Vgs − Vt )VC = (Vgs − Vt + VC )Vdsat
VC
vdsat = (Vgs − Vt )
VC + (Vgs − Vt )
1
= (V − Vt )
(Vgs − Vt ) gs
1+
VC
Thus writing in a compact form, where VGT = Vgs − Vt

Vdsat = κ(VGT )VGT

The above expression clearly indicates that the device enters to saturation before Vds reaches VGT , as
the value of κ(Vds ) < 1 for short channel.
Thus one can make 3 important observations
1. For short channel device - Larger VGT forces κ (VGT ) to be < 1. Hence Vdsat < VGT . The
consequence of this is that the device enters saturation region for the value of Vds < VGT and thus
the device experiences an ”Extended saturation”. This is reflected in Fig.

2. Based on Eq.16b, Idsat displays ”Linear dependency w.r.t Vgs ”. This results in

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3. ID is proportional to κ(V ) and due to which, whenever V is high, the value reduces < 1.
- Reduces the amount of current a transistor can deliver for a given control Vgs .

Velocity saturation effect Approximation

Unfortunately, ID expression are complex expression of Vgs and Vds - making hard for manual
analysis.
A substantially simple model can be obtained by making 2 assumptions, which makes the com-
putation ease.
1. The velocity saturates abruptly at Ec , and is approximated by the following expression:
(
µn E for E ≤ Ec
vD =
vsat = µn Ec for E > Ec

2. The drain-source voltage Vdsat at which the critical electrical field is reached and velocity
saturation comes into play is constant and is approximated by
Lvsat
Vdsat = LEc =
µn
This assumption is reasonable for larger values of VGT (>> Ec L).
3. Once Vdsat is reached, the current abruptly saturates.
V2
 
W
Idsat = Id (Vds = Vdsat ) = µn Cox (Vgs − VT )Vdsat − dsat
L 2
 
Vdsat
= vsat Cox W Vgs − VT −
2

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Assignment 5.1:

cm2
The critical voltage for fully ON pmos transistor, having effective mobility of µef f −p = 38 ;
V ·s
cm
and velocity saturation of vsat = 7 × 107 is . Assume velocity saturates
s
abruptly at Ec .

5.2 Mobility degradation

Vgs
This effect is due to vertical electric field, Ev = . For lower technologies, tox is generally in the order
tox
of few atomic scale - leading to high vertical Ev . This high Ev leads to
• Carriers scatter-off the oxide interface
• Slows the carrier progress - leading to less current than expected at high Vgs

5.3 Channel length modulation

The impact is observed in the saturation region, where Ids displays dependence on Vds .
As Vds increases beyond Vov , the voltage drop across the depletion region has this following relation:
0
∆L ∝ Vds − Vov ⇒ ∆L = λ (Vds − Vov )
and effectively channel length becomes
Lef f = L − ∆L
The same is reflected in Fig.27.

Source Channel Drain

- +
Vds − Vov
- vov +
L − ∆L ∆L

Figure 27: Impact of Channel length modulation onto the channel charge

Just because the effective channel length has reduced in the saturation region, the drain current can
be reformulated to account this reduced channel length.

1 W 2
Ids =µn Cox (Vgs − VT )
2 Lef f
1 W 1
= µn Cox   (Vgs − VT )2
2 L ∆L
1−
L
 −1
∆L ∆L
Considering ∆L/L << 1, the binomial expansion of 1 − ≈1+
L L
0 0
W.k.t ∆L = λ (Vds − Vov ) and for simplicity, ∆L ≈ λ Vds .
0
!
1 W 2 λ Vds
Ids = µn Cox (Vgs − VT ) 1 +
2 L L
(18)
1 W 2
= µn Cox (Vgs − VT ) (1 + λVds )
2 L

5.4 Body effect

Before we get into the topic, let’s review the definition of threshold voltage of MOS.

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Threshold voltage definition

Threshold voltage is the minimum voltage that is required to create the channel.
One can decompose VT into 2 components
1. First, it needs to deplete the majority carriers away from the O-S interface.

2. Second, it needs to pull the minimum minority carriers towards O-S interface to create the
channel.

We know MOSFET is a 4 terminal device. When Vsb is applied b/w Source & Body - it increases the
amount of charge required to invert the channel - hence it increases the value of VT , which is given by,
p p 
VT = VT 0 + γ φs + Vsb − φs (19)

√ 1
2qsi NA
where body-effect co-efficient, γ = , typically ranges from 0.4 to 1 V 2
Cox
NA
and surface potential at threshold, φs = 2ϑT ln .
ni
κT
where NA : Acceptor conc.; ni : Intrinsic conc.; ϑT = : Thermal voltage; κ: Boltzmann constant.
q
Qualitatively one could think of the above phenomena with the following example. As the channel
length is quite small, let’s assume that we need only 10 electrons to create the channel between S & D,
as shown in Fig.28(a).

- - - - - - - - - -

n+ n+ - - - - - - - - -

n+ n+
p-type
Vsb + p-type
−

(a) When Vbs = 0 (b) When Vbs 6= 0

Figure 28: Body effect

Now let’s apply a potential difference between S & B (- without changing the other bias condition),
such that it can pull one of the electron from channel through S terminal. This reflected in Fig.28(b).
This phenomena happens due to the source node that is slightly at a higher potential than the ground.
But to create a channel we need 10 electrons, but we right now have only 9 out of 10. So one has to
apply a bit high Vgs to pull an extra minority carrier from the bulk.

5.5 Short channel Effect

Traditionally, VT was assumed to do the following
• Channel depletion region is only due to Gate voltage.
• All channel charges originates from MOS field effect(Vertical EV ).

Short channel effect

But this wasn’t the case in short-channel devices, where,
- Part of the channel charges below Gate is already depleted by S/D reverse-biased pn depletion
region.
- Requiring only lesser VT to causes a strong inversion.

The above phenomena is reflected in Fig.29.

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Figure 29: Short channel effect

You might think that we had the same pn junction between S/D and body - which means part of the
depleting work is done even in the case of a long channel device. But still we never consider their work
and assumed that only VG depleted the carriers under O-S interface. Why is this?
The answer can be drawn from the previous discussion of Body-effect. When one deal with short-
channel devices, the length of the channel is very small and it becomes comparable to the depletion
region width created by these pn junctions. Thus one has to encounter their contribution for the channel
creation through lowering the value of VT .

Note
Fig.29 shows a classical short-channel effect - decrease of VT with decrease of L.

In newer processes (like 180 nm technology), there is so-called halo or pocket implant , where
substrate/body/channel is more heavily doped near source/drain junctions - this is done in order
to suppress DIBL (decrease of Vt with increase of Vds voltage).

When L gets shorter, halo regions overlap, leading to effectively higher substrate doping, and
thus higher Vt. This is called a reverse short-channel effect - Vt increase with decrease of L.
This effect is shown in Fig.30

Figure 30: Reverse short channel effect

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5.6 Drain Induced Barrier Lowering (DIBL) effect

Figure 31: DIBL

As the name suggest, it’s an effect that is related to the drain terminal. This effect is almost similar
to short channel effect. Here when the Drain potential is raised, the depletion region around the drain
enlarges, encroaching more under the gate. So due to which, the value of VT that is required to invert
the channel is reduced further. The same is reflected in the Fig.31.

5.7 Leakage effects

There are 3 types of leakages in short channel MOS device

1. Subthreshold conduction b/w Source & Drain

- due to Thermal emission of carriers over the potential barrier set by VT
2. Gate leakage from Gate to Body
- due to Quantum mechanical effect called Tunneling

3. Junction leakage from Source/Drain to Body

- due to reverse biased pn junction
Let’s discuss each of them in a bit detail.

5.7.1 Subthreshold conduction

By theory, Ids should abruptly become 0 when Vgs < VT . But in reality, it decays exponentially -
whose characteristics reminds us the similar behavior of a bipolar transistor. This effect is called as
Sub-threshold (or) weak-inversion conduction.
In the absence of a conducting channel, the n+ (source) - p (bulk) - n+ (drain) terminals actually
form a parasitic bipolar transistor.

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Figure 32: Subthreshold conduction

Note: The graph shown in Fig.32 is logarithmic scaled in y-axis. We know that a straight line in log
scale, implies exponential dependence on x-value(Vgs ).
The current in channel region -due to parasitic bipolar transistor - can be approximated by
Vgs − VT Vds
 
−
Ids = Is e nκT /q 1 − e nκT /q  (20)
 

Slope factor, S

Measures the (inverse) rate of decline of Ids w.r.t Vgs below VT

- hence the quality of the device.
Measures by how much Vgs has to be reduced for the Ids to drop by a factor of 10.
 
κT
S=n ln(10) (mV /decade)
q

For an ideal transistor with the sharpest possible rolloff, n = 1, at room temperature, would have a
slope factor, S
S = 60mV /decade
- means the subthreshold current drops by a factor of 10 for a reduction in Vgs of 60 mV below VT .
Unfortunately, in actual devices, n > 1 and the current falls at a reduced rate (90 mV/decade for n
= 1.5).
Assignment 5.2:

What is the minimum threshold voltage for which the leakage current through an OFF transistor
(Vgs = 0) is 103 times less than that of a transistor that is barely ON (Vgs = VT ) at room
temperature if n = 1.5? One of the advantages of silicon-on-insulator (SOI) processes is that they
have smaller n. What threshold is required for SOI if n = 1.3?

5.7.2 Gate Leakage

For Oxide Thickness < 15 − 20Å:
- Carrier crosses the thin barrier - this effect is called Tunneling

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- Results in gate leakage current

There are 2 physical mechanisms for gate tunneling:

• Fowler Nordheim (FN)tunneling
- Important at High voltage and moderate oxide thickness
- Used to program EEPROM
• Direct tunneling
- Important at Low voltage with thin oxide
- Dominant leakage component

5.7.3 Junction Leakage

From the basic electronic course, we know that a reverse biased diode conducts a small amount of current,
known as junction leakage current and it can be expressed as
 
VD
ID = IS e ϑT − 1 (21)
 

where IS : Saturation current - related to doping

. VD : Diode voltage(like, −Vsb or −Vdb ) as shown in Fig.??.

p+ n+ n+ p+ p+ n+

n − well
p − sub

Figure 33: nMOS & pMOS in nwell CMOS process exposing all the parasitic diodes

The Fig.?? shows an n-well fabrication process for CMOS circuit realization. Here, a separate
n-well is embedded into p-sub to realize pMOS transistor. This one of the other processes, like, p-well,
twin-tub fabrication techniques for CMOS realization. We will study about these processes later in
unit.5.
Note that the mechanism of junction leakage is almost identical to Sub-Threshold conduction. The
only difference is that, it has additionally parasitic diodes at the interface between p-suband n-well -
which contributes to leakage independent of VG .

5.8 Mobility and threshold voltage variation with respect to temperature

Transistor characteristics are influenced by temperature.
• µ reduces with temp

• vsat reduces with temp

• VT reduces linearly with temp
• Ion at high VDD reduces with temp

• Sub-threshold conduction increases exponentially with temp

• Gate leakage is almost independent of temp
The combined effect is shown in Fig.

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Figure 34: Parameter variation with temp

Observation
• At high Vgs the current has negative temperature co-efficient
• At low Vgs the current has positive temperature co-efficient

Conclusion
• OFF current increases with temperature.
• ON current Idsat normally decreases with temperature.

- So circuit performance is worst at high temperature.

- For systems operating at low VDD (typically < 0.7–1.1V), Idsat increases with temperature.

6 DC characteristics
In most cases, DC characteristic of the circuit is the study of DC input Vs DC output. For instance, Vin
Vs Vout or Vgs Vs Ids . But in certain cases, the study of Vds Vs Ids for different Vgs is known as output
characteristics is also considered as DC characteristics. So in general, it is the study of change in one
node, measured either as I or V, to the change in another node.
In this section, we will be studying the static characteristics of CMOS Inverter. But in order to
appreciate the mechanism, we first look at the characteristics of an inverter built using an nMOS and
a resistive load. With this as the base, we will continue to study the behavior of CMOS inverter under
different DC conditions, which then be utilized to extract the Noise margin parameter of the CMOS
inverter. Finally, we end the section with the study of static behavior of pass-transistor logic.

6.1 nMOS DC characteristics

Consider the inverter shown in Fig.??, known as nMOS inverter with resistive load, whose output voltage
is defined as
Vds = Vout = VDD − Id RD (22)

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VDD

RD

Vout

Vin

Figure 35: nMOS inverter

We know that Ids is function of Vin = Vgs . So when the value of Vin < VT , the nMOS is in cut-off
and Ids = 0. Due this condition, the output voltage is defined as

Vout = VDD

This situation is reflected in Fig., where the black dot denotes the current value of Vds w.r.t x-axis and
Ids w.r.t y-axis.

Ids (mA)

VDD
0 Vds (V )

Figure 36: Output characteristics of nMOS with load line

Now when VDD /2 > Vin > VT , the ID 6= 0 and it is small. This small value of Ids makes Vout to
slightly reduce from VDD value. Now we have a situation, where Vout > Vin − VT , which dictate nMOS
to be in saturation region. The same is reflected as a black dot in Fig.

Ids (mA)

0.2
Vds (V )

Figure 37: Output characteristics of nMOS with load line

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As one increase the value of Vin further, the Vout starts to go towards low value. Ultimately Vout <
Vin − VT , the nMOS enters the linear region. The same is reflected in the plot shown in Fig.

Ids (mA)

0.8

0.6

0.4
0.2
0 Vds (V )

Figure 38: Output characteristics of nMOS with load line

Note
The nMOS started in cut-off region, then it traveled into saturation region and finally it enters
into linear region.
Normally, we have the notion in mind that the transistor travel from cut-off to linear and then
to saturation, due to visual representation of Vds Vs. Ids graph. But this is always a falls
misconception, as we tend to think that the cut-off region in near Vds = 0. This is not the case,
it doesn’t belong to a single value of Vds , but rather it traces out entire Vds spectrum, where
Ids = 0. It’s only when a load is added to the circuit, the cut-off sticks to a single value of Vds .
In the above case, it sticks to Vds = VDD .
Also, it is evident that the travel along the load line defines the path cut-off →saturation→linear
for nMOS.

6.2 CMOS DC characteristics

A CMOS inverter replaces the resistive load, that was in nMOS inverter, with a pMOS device. The
circuit shown in Fig.?? reflects the CMOS inverter and the corresponding output characteristics plot of
nMOS & pMOS.

Ids (mA)
1

0.8 NMOS Characteristics

- As individual transistor
0.6
M2 0.4
−0.20 0.2
0
Vin Vout −0.4 Vds (V )
−0.6
PMOS Characteristics
M1
- As individual transistor −0.8

−1

(a) Realization of CMOS Inverter (b) Output characteristic plots

Figure 39: CMOS inverter

Based on the study conducted in the previous subsection, one can analyze DC characteristics of the
CMOS inverter for different values of input. Before we begin to do so, let’s define some variables related
to both the MOSFETs.

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Variable definitions
nMOS: VGS,n = Vin , VDS,n = Vout
pMOS: VSG,p = VDD − Vin , VSD,p = VDD − Vout

Now let’s use the above variable definitions to re-plot the Output characteristics of the above plots,
such that our x-axis is defined in terms of Vout , rather than Vsd,p and Vds,n .
For instance, assume that we have Vin = 0 and the corresponding value of Vgs,n = 0 dictates nMOS
to be in cut-off and the value of Vsg,p = VDD , which is > |VT p |, dictating pMOS to be in ON, but one
cannot defines it’s region of operation until the value of Vsd,p is known. So how on earth one can solve
this puzzle?
The puzzle could be solved by plotting the output characteristics of both nMOS and pMOS.

Ids (mA)

Vin = 0

VDD Vout

Figure 40: For Vin = 0

As you could see, both the graphs intersects at the black dot and dictates pMOS to be in deep linear
region and defines it’s Vsd,p = 0 and Vout = VDD .
Now let’s increase the value of Vin further, say 0.2% of VDD and 0.4% of VDD . In this case, both the
transistors are ON and they start conducting a current such that they agree each other. The situation
is reflected in Fig.

Ids (mA) Ids (mA)

Vin = 0.4
Vin = 0.2

Vout Vout
(a) For Vin = 0.2 × VDD (b) For Vin = 0.4 × VDD

Figure 41: For VT n < Vin < VDD /2

Clearly, the above graph dictates pMOS to be in linear region and nMOS to be in saturation region.
Now let’s see for Vin = VDD /2.

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Ids (mA)

Vin = 0.5

Vout

Figure 42: For Vin = VDD /2

As you might have expected, both pMOS and nMOS has entered into saturation. Now if the value
of Vin increases further, say Vin = 0.6% and Vin = 0.8% of VDD , the nMOS moves to linear and pMOS
stays in saturation and the same is reflected in Fig.

Ids (mA) Ids (mA)

Vin = 0.6
Vin = 0.8

Vout Vout
(a) For Vin = 0.6 × VDD (b) For Vin = 0.8 × VDD

Figure 43: For < VDD /2 < Vin < VDD − |VT p |

But the moment Vin is increased to VDD − |VT p |, the pMOS enters cut-off and conducts no current,
whereas the nMOS stays in linear with Vds,n = 0 bringing Vout = 0.

Ids (mA)

Vin = 1

Vout

Figure 44: For Vin = VDD

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Ids (mA)

Vout
(a) Output characteristics (b) Voltage Transfer Characteristic graph

Figure 45: CMOS Inverter region of operation

Observe that the nMOS follows the trend of being from cut-off to saturation and finally to linear,
where as pMOS being from linear to saturation and to cut-off. This is the similar cycle that we had
observed earlier w.r.t nMOS inverter.
A summary of CMOS inverter region of operation is shown in Table

Table 2: Summary of CMOS region of operation

Region Condition pMOS nMOS Output

A 0 ≤ Vin < VT n linear cut-off Vout = VDD
B VT n ≤ Vin < VDD /2 linear saturation Vout > VDD /2
C Vin = VDD /2 saturation saturation Vout drops sharply
D VDD /2 < Vin ≤ VDD saturation linear Vout < VDD /2
E Vin > VDD − |VT p | cut-off linear Vout = 0

6.3 Inverter switching voltage

Let’s define a parameter named as beta ratio, r
βp
r= (23)
βn
Now let’s look into the definition of ”Inverter Switching voltage”, also known as ”Inverter threshold
voltage” VM (or) Vinv :
Inverter switching voltage

VDD
It is defined as the input voltage at which the output of the inverter is equal to .
2
VDD
Vinv = (24)
2

You might have a question in our mind: ”What is this VM ? What to do with it? (or) How does it
helps us?”
- It is used to define the Noise margin of the inverter.
βp
Note: When βp = βn (or) Beta ratio,r = = 1, then
βn
VDD
VM =
2
-which is desirable value in-order to have

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1
• High Noise Margin
• Charge & discharge the output capacitor with equal time
Inverters with r = 1 - said to be Unskewed
6 1 - said to be Skewed
Inverters with r =
There are two cases of Skewed Inverters:
• If r > 1, then the inverter is Hiskewed
-means PMOS is more stronger than NMOS
VDD VDD VDD
-so at Vin = , Vout > ⇒ Vinv >
2 2 2
• If r > 1, then the inverter is Lowskewed
-means NMOS is more stronger than PMOS
VDD VDD VDD
-so at Vin = , Vout < ⇒ Vinv <
2 2 2
Note: Gates are usually skewed by adjusting W - while maintaining min. L for speed.
The effect of Voltage Transfer characteristics for the range of r is shown in Fig.

Figure 46: Beta ratio effect

Now let’s look at the quantitative view of VM , through the following derivations:

6.3.1 Derivation of Vinv for long channel MOSFET

Equating the currents of the MOSFETs for the Long channel transistor in saturation:
βn βp
Idn = Idp ⇒ (Vgsn − VT n )2 = (Vsgp + VT p )2
2 2
1
(Vinv − VT n )2 = (VDD − Vinv + VT p )2
r
Taking square-root on both sides:
 
1 1 V
√ (Vinv − VT n ) = (VDD − Vinv + VT p ) ⇒ √ + 1 Vinv = √T n + VDD + VT p
r r r

VT n
VDD + VT p + √
r
Vinv = (25)
1
1+ √
r
1 will be discussed later

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6.3.2 Derivation of Vinv for short channel MOSFET

For Short channel transistor in saturation:

Idn = Wn Cox ϑsat−n (Vinv − VT n )

Idp = Wp Cox ϑsat−p (VDD − Vinv + VT n )

Redefining the beta ratio as, r = Wp ϑsat−p /Wn ϑsat−n

Idn = Idp ⇒ Wn Cox ϑsat−n (Vinv − VT n ) = Wp Cox ϑsat−p (VDD − Vinv + VT p )

1
(Vinv − VT n ) = (VDD − Vinv + VT p )
r
VT n
VDD + VT p +
Vinv = r (26)
1
1+
r
Special case of r

VDD
In both the case, when VT n = −VT p and r = 1, the Vinv = .
2

6.3.3 Noise Margin

Now with the definition of Vinv , let’s define 4 more parameters to define the Noise margin.
VIH and VIL are the input acceptance value for logic values 1 and 0, respectively.
VOH and VOL are the output acceptance value for logic values 1 and 0, respectively.
These above parameters are visually represented in the following Fig.

VDD
Logic High
Output range Logic High
VIH
Input range
N MH
VOH Indeterminate
VOL Region
N ML
Logic Low
Logic Low VIL
Input range
Output range
GN D

Figure 47: Noise Margin definition

and by expression as

• Low Noise Margin, N ML = VIL − VOL

• High Noise Margin, N MH = VOH − VIH
Note:
Now theboth must is ”How to measure V
question OH , VOL , VIH and VIL ??”
be +ve
The way to measure these values are by looking at the slope of the voltage characteristics graph, where
the slope value is -1, as shown in Fig.

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Figure 48: VIL , VIH , VOL and VOH definition

Noise margin extraction through simulation

The way one could extract the slope parameter in simulation, is by taking the derivative of Vout
of the inverter. The same is plotted in Fig.

6.4 Pass-transistor DC characteristics

A pass-transistor is logic family, like CMOS logic family, where the Gate terminal is used as control
input and either Source/Drain being used as input, while the other terminal as output. The control input
serves to turn-on the device under consideration.
Let’s understand the DC conditions for the following circuit conditions shown below. The values for
Vout for each of the case is listed with the assumption that the Vout node is connected to an output
capacitor load, CL with an initial value of VDD /2 across it.

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Introduction to VLSI Design Unit 1

Vout Vout

VDD VDD
(a) nMOS: When Vin = 0 (b) nMOS: When Vin = 1
Vout Vout
VDD

(c) pMOS: When Vin = 0 (d) pMOS: When Vin = 1

Figure 49: DC conditions for the pass transistor

(a) Since VG = VDD and VS = 0, effectively the VGS = VDD > VT n and due to which the nMOS
transistor is ON. This condition ensures the existence of channel throughout the discharging period
of Vout - from the initial value of VDD /2 to the final value of 0.
So one can conclude that nMOS is a good conductor of 0.
(b) In this case, the Source and Gate terminals are connected to VDD - due to which the question of
whether the nMOS is ON or not might arise in your mind.
The answer to your doubt is that - In a MOSFET, there is no difference between Source and Drain
terminal. Due to which, one can treat the Drain terminal as the Source terminal to analyze the
circuit conditions further.
In that case, the VGD ≡ VGS = VDD /2 > VT n is met and the transistor is tuned ON and the channel
is created under the Gate. Due to potential difference VDS = VDD /2 6= 0, there will be a current
flow between Source and Drain terminals and the output node charges towards VDD .
But the charging trend stops when VGD = VT n - because there exist no channel. So the output node
can only charge upto VDD − VT n , resulting in poor conduction of VDD .
So one can conclude that nMOS is a poor conductor of 1.
(c) This case is identical to the case of (b). So we will assume that the Drain terminal as the Source
terminal and analyze the circuit conditions.
In that case, the VDG ≡ VSD = VDD /2 > |VT p | is met and the transistor is tuned ON and the
channel is created under the Gate. Due to potential difference VDS = VDD /2 6= 0, there will be a
current flow between Source and Drain terminals and the output node discharges towards 0.
As usual, the moment when VSG = |VT p | is reached, the channel disappears and the output node
stays at |VT p |.
So one can conclude that pMOS is a poor conductor of 0.

(d) The last case is pretty straight forward as (a). Since the channel is ON through out entire charging
period of the output capacitor - one can conclude that pMOS is a good conductor of 1.

Note
In the Pass-transistor logic, the input and output are connected through low-impedance path,
while in CMOS logic, the input and output are connected through High-impedance path.

Assignment 6.1:

Compute the values of Vout for the following circuits:

Vout =

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Introduction to VLSI Design Unit 1

Vout =

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Introduction to VLSI Design Unit 1

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