ISSN: 2582-1458

https://doi.org/10.31838/jvcs/01.01.02
Research Article

HIGH SPEED AND LOWPOWER GDI BASED FULL

ADDER
Z.ZAIN
Information Systems Department, College of Computer & Information Sciences, Princess Nourah Bint
Abdulrahman University, Riyadh, Saudi Arabia,
Email id : [email protected]
Received: 25.01.19, Revised: 27.02.19, Accepted: 28.04.19

ABSTRACT
Full adder is one of the fundamental digital block in the many electronic circuits. As the day by day scaling down the
technology(Deep-sub micron level) power consumption becomes one of the primary concern for any portable
electronic devices. In this paper our main motto is to design and implement the low power full swing full adder, using
GDI (Gate Diffusion input )technique. Simulated full swing GDI based adder using the cadence virtuoso in 180nm
technology. and also we conducted the a comprehensive study on different types of full adders and their
performances with respect to SERF and 28 T circuits respectively.
Keywords: Full Adder,GDI

INTRODUCTION verity of full adders have been implemented and

With the enormous development of versatile simulated using different circuit topologies to
electronic items, the creators are headed to perform the single bit addition[1-3].although many
endeavour for longer battery life, higher speed, and of papers has been published on full adders and
improved quality with innovation scaling. which push mentioned in literature survey [4-6] but which
the market interest for additional what's more and produces the different yields in terms of propagation
more capacity in Integrated circuit(IC).In many delay, power consumption, size and wiring
electronic devices addition is one the fundamental complexity of the circuit. the basic block diagram of
operation, these operation can be widely used in full adder as shown in fig1 and its truth table 1
many application areas. full adder is one of the basic represents the operation of full adder.
fundamental electronic circuit which can extensively
used to perform the addition operation. A wide
Table 1: truth table of 1bit-full adder.

Fig 1:Block diagram of Full Adder.

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The rest of the paper is organised as follows section be designed using the more than one logic style[]. in
2 describes the various types of the CMOS type full below section we are explaining the different types of
adders and their comparison 3 explains the GDI full adders using the CMOS architectures
based CMOS full adder and simulation results. respectively.
CMOS full adder using 28 transistors
Previous work As shown in Fig:2 the full adder is designed using 28
A wide verity of CMOS full adders cells are proposed transistors using convention CMOS topology. Due to
to achieve the high speed and low power. Generally more number of transistors which may leads to more
full adders have been classified majorly in two types power consumption and occupies the huge area.
such as classical design, which means the whole One of the most desired feature and significant
circuit can be implemented using only PMOS and advantage is it offers the full voltage swing, better
NMOS by means of pull up and pull down noise immunity and operated at wide range of
configuration modelling[7]. On the other hand temperature.
design of full adder using hybrid style, the circuit can

Fig 2: CMOS full adder using 28 transistors.

CMOS full adder using 16 transistors transmission gate respectively. This 16 transistor
in order to reduce the number of transistors and adder reduces the power as compared to
decrease the power consumption proposed a full conventional full adder circuit. the architecture of the
adder by compositing of 16 transistors. The design is CMOS full adder as shown in figure3. respectively[8-
combination of XOR and XNOR circuits as well as 10].

Fig 3: CMOS full adder using 16 transistors.

Static Energy Recovery Full Adder (SERF) reducing the full swing voltage. During the design of
Further to improve the performance of the proposed the SERF there is no direct connection is between
a full adder using only 10 transistors. this full adder VDD to ground. The capacitor stores the capacitor
reduces the power and enhances the speed of the stores the charge with respect to the supply grounds.
circuit to achieve the sum and carry output without figure4. depicts the CMOS SERF full adder.

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 Zain et al / High Speed And Lowpower Gdi Based Full Adder

Fig 4: SERF Full Adder

GDI based full adder here the diffusion terminals are taken to be input
The basic GDI cell is designed with the help of terminals. The basic GDI based cell shown by figure
CMOS inverters, the architecture consists of PMOS 5 respectively. As the GDI cell is going to perform the
and NMOS transistors. In conventional CMOS different types of the Boolean operations, (inverter,
inverter PMOS and NMOS substrates are connected buffer, or, xor, nor, mux)as shown in the table-2.
to VDD and ground respectively. On the other hand

Table 2. Truth table of CMOS GDI cell

Fig 5: Basic GDI cell.

Proposed GDI full adder

The proposed GDI based full adder is generates the full adder expression in to the equation(1)& (2)
full swing output without need of the any swing respectively. the designed structure as shown in
restoring circuits. which completely avoids the buffers figure 6 and whose layout also drawn using the
there the performance can be improved. The cadence virtuoso 180 nm technology.verifed the
possible full swing can be achieved by rewriting the DRC,LVS and RC extraction for the proposed circuit .

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 Zain et al / High Speed And Lowpower Gdi Based Full Adder

Fig 6: proposed full swing GDI full adder.

simulation setup
In order to measure the metrics of the proposed full and verified the output voltage at all nodes. From the
adder we have been simulated using the cadence obtained results it consumes the minimum power
virtuoso 180nm technology, with the supply voltage consumption of 1084nanowatts and maximum
of 1.8v and ambient temperature of 270C power consumption of 1217 and 1084nanowatts.In
respectively. All PMOS and NMOS transistors has similar passion the delay was obtained as 22.6 and
Lmin=180nm.we applied the 50ms at transient time 31.8ps respectively.

Fig 7: Layout for Proposed full swing GDI full adder.

Conclusion References
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