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21 views3 pages

Without Assign

Bsnsjsjsjsjs jsjsjsk jsjsjss kJajsks snsk

Uploaded by

YOGESH GOWDA V
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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module fir_filter (

input wire clk,


input wire reset,
input wire [7:0] x, // Input data from LFSR
output reg [15:0] y // Filter output
);
reg [7:0] h0, h1, h2, h3;
reg [7:0] x_reg0, x_reg1, x_reg2, x_reg3;
wire [15:0] mul0, mul1, mul2, mul3;
wire [15:0] sum1, sum2;
karatsuba_multiplier mult0 (.a(x_reg0), .b(h0), .product(mul0));
karatsuba_multiplier mult1 (.a(x_reg1), .b(h1), .product(mul1));
karatsuba_multiplier mult2 (.a(x_reg2), .b(h2), .product(mul2));
karatsuba_multiplier mult3 (.a(x_reg3), .b(h3), .product(mul3));
brent_kung_csa_16bit adder1 (.a(mul0), .b(mul1), .sum(sum1), .carry_out());
brent_kung_csa_16bit adder2 (.a(mul2), .b(mul3), .sum(sum2), .carry_out());
always @(posedge clk or posedge reset) begin
if (reset) begin
h0 <= 8'd1;
h1 <= 8'd2;
h2 <= 8'd3;
h3 <= 8'd4;
x_reg0 <= 8'd0;
x_reg1 <= 8'd0;
x_reg2 <= 8'd0;
x_reg3 <= 8'd0;
y <= 16'd0;
end else begin
x_reg0 <= x;
x_reg1 <= x_reg0;
x_reg2 <= x_reg1;
x_reg3 <= x_reg2;
y <= sum1 + sum2;
end
end
endmodule
module brent_kung_csa_16bit (
input wire [15:0] a,
input wire [15:0] b,
output reg [15:0] sum,
output reg carry_out
);
reg [7:0] sum_low, sum_high, sum_high_with_carry1;
reg carry_out_low, carry_out_high, carry_out_high_with_carry1;
wire [7:0] a_low = a[7:0];
wire [7:0] b_low = b[7:0];
wire [7:0] a_high = a[15:8];
wire [7:0] b_high = b[15:8];
always @* begin
{carry_out_low, sum_low} = a_low + b_low;
{carry_out_high, sum_high} = a_high + b_high + 1'b0;
{carry_out_high_with_carry1, sum_high_with_carry1} = a_high + b_high + 1'b1;
sum = {carry_out_low ? sum_high_with_carry1 : sum_high, sum_low};
carry_out = carry_out_low ? carry_out_high_with_carry1 : carry_out_high;
end
endmodule
module brent_kung_adder_8bit (
input wire [7:0] a,
input wire [7:0] b,
input wire carry_in,
output reg [7:0] sum,
output reg carry_out
);

reg [7:0] g, p;
reg [7:0] c;
always @* begin
g = a & b;
p = a ^ b;
c[0] = carry_in; // Use carry_in for the first carry
c[1] = g[0] | (p[0] & c[0]);
c[2] = g[1] | (p[1] & c[1]);
c[3] = g[2] | (p[2] & c[2]);
c[4] = g[3] | (p[3] & c[3]);
c[5] = g[4] | (p[4] & c[4]);
c[6] = g[5] | (p[5] & c[5]);
c[7] = g[6] | (p[6] & c[6]);
carry_out = g[7] | (p[7] & c[7]);
sum = p ^ c;
end
endmodule
module karatsuba_multiplier (
input wire [7:0] a,
input wire [7:0] b,
output reg [15:0] product
);

reg [3:0] a_low, a_high, b_low, b_high;


reg [7:0] P1, P2, P3;
reg [15:0] part1, part2, part3;
always @(*) begin
a_low = a[3:0];
a_high = a[7:4];
b_low = b[3:0];
b_high = b[7:4];
P1 = a_low * b_low;
P2 = a_high * b_high;
P3 = (a_low + a_high) * (b_low + b_high) - P1 - P2;
part1 = {P2, 8'b0};
part2 = {P3, 4'b0};
part3 = P1;
product = part1 + part2 + part3;
end
endmodule

module tb_fir_lfsr;

// Testbench signals
reg clk;
reg reset;
wire [7:0] lfsr_out;
wire [15:0] fir_out;

// Instantiate the LFSR


fibonacci_lfsr lfsr_inst (
.clk(clk),
.reset(reset),
.lfsr_out(lfsr_out)
);

// Instantiate the FIR filter


fir_filter fir_inst (
.clk(clk),
.reset(reset),
.x(lfsr_out),
.y(fir_out)
);

// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // 10ns clock period
end

// Stimulus generation
initial begin
// Initialize signals
reset = 1;
#10;
reset = 0;

// Simulate for a while


#200;

// End simulation
$finish;
end

// Monitor signals
initial begin
$monitor("Time: %0t | LFSR Out: %h | FIR Out: %h", $time, lfsr_out,
fir_out);
end

endmodule

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