Design for testability (DFT)

Introduction
• Sequential circuit testing requires (dseq+1) number of
test patterns
• Inconsistency may occur in any time frame
• Difficulty in controlling secondary inputs and difficulty in
observing secondary outputs --- sequence of patterns for
ATPG
• Various techniques to make the flip-flops controllable
and observable which convert a sequential circuit into
virtual combinational one such that ATPG for
combinational circuit can be used for seq. circuits
• Results in additional circuitry, called design for test
(DFT), will be put on-chip, adding to extra area overhead
2
 Design for testability (DFT)
• Refers to those design techniques that make test
generation and test application cost-effective
• Improve
• Controllability: a measure of the difficulty of
setting internal circuit nodes to 0 or 1 by assigning
values to primary inputs (PIs)
• Observability: a measure of the difficulty of
propagating a node’s value to a primary output
(PO)
 Design for testability (DFT)
• DFT methods for digital circuits:
• Ad-hoc methods
• Structured methods:
• Scan
• Partial Scan
• Built-in self-test (BIST)
• Boundary scan
 Ad-Hoc DFT Methods
Good design practices learnt through experience are
used as guidelines

• Insert test points

• Avoid asynchronous set/reset for storage
elements
• Avoid combinational feedback loops
• Avoid redundant logic
• Avoid asynchronous logic
• Partition a large circuit into small blocks
 Ad-Hoc DFT Methods

• Disadvantages of ad-hoc DFT methods

• Experts and tools not always available
• Test generation is often manual with no guarantee
of high fault coverage
• Design iterations may be necessary
Controllability and observability
of Flip-flops
set
• Asynchronous set and reset inputs Input Output
D Q

clk FF

reset
Input(D) Output(Q) Set Reset clk

Don’t care 1 1 0 Don’t care

Don’t care 0 0 1 Don’t care

Don’t care illegal 1 1 Don’t care

1 1 0 0 Clk edge

0 0 0 0 Clk edge
7
 Test generation using set/reset pins

• Fault can not be tested as b=X, c = X/X

• Step 1: set = 1 and reset = 0 (primary input = X), Primary
output = 1
b
c
D Q
Primary input sa1 FF Primary output
clk

b set=1
1
c
D Q
Primary input sa1 FF Primary output
clk 8
Reset = 0
 Test generation using set/reset pins

• Step 2: set = 0, reset = 0, and primary input = 0 - a +ve

clk pulse transfers D to output of FF (primary output)

b=1 set=0
D
c
D D Q
Primary input=0 sa1 FF Primary output
clk
Reset = 0

b set=0
D
c
D Q
Primary input sa1 FF Primary output
clk 9
Reset = 0
 Test generation using set/reset pins

• Using set/reset pins in FF, the faults in cyclic circuit can

be detected, which were not testable by time frame
expansion method
• Only two patterns are required (one for set/reset the FFs
and other for sensitize/propagate the fault effects) as
against time frame expansion method, which require
Dseq+1 test patterns to test a fault
• Saves the number of test patterns and hence the test
time
• Convert sequential circuit into virtual combinational
circuit and hence combinational ATPG algorithm (D-alg)
used for TG

10
 Test generation using set/reset pins -
Drawback
• Irrespective of the value of dseq, only 2 patterns are
required to test a sequential circuit with set/reset FFs –
Solves the problem of too many test patterns
• Increase pin-out – increase ATE cost
set1 set2

a
Primary output
b
circuit
c

clk

reset1 reset2
11
ATPG : set and reset by Shift register
• Avoid large pinout using shift registers
• Three additional I/O pins are required – Test in, Test out,
s_clk set = 1 set = 1
a
j
b
c D Q
1 e . f
D Q
i
2 sa0
d k
clk clk FF2 4
FF1
g h
3
reset = 0
reset = 0

Test in
D Q .1
D Q . 0
D Q . 1
D Q . Test out
0

s_clk FF1 s_clk FF1 s_clk FF1 s_clk FF1

12
ATPG : set and reset by Shift register
• n number of circuit FFs require 2n number of FFs in Shift
register
• 2n number of s_clk pulses to load the required data in
the shift register
• ATE time will be too expensive with this 2n number of
s_clk pulses
• S-clk faster than circuit clk
• Additional 2n number of clk pulses required to load 0s
for normal operation – 2n+2n clock to load pattern into
FF
• Extra area overhead

13
 ATPG: Time Frame Expansion VS
Shift register
• In time frame method, dseq number of time frames are
required to load the FFs and then apply the test pattern
• (dseq+1) number of test patterns
• Generally dseq ≤ n
• In Shift register (SR) based method, 2n number of extra FFs
are required
• time frame expansion method less popular
-- uses the primary inputs to set/reset the FFs, more
complex
-- May arrive at an inconsistency after some time frames
• In the case of SR method, direct access to the FFs - No
question of inconsistency 14
 Controllability and observability using
Scan Register
• Scan register – register with parallel load and shift
capability (serially connected Scan FF or scan
storage cell)
• Loading data – scan in; reading data scan out

NI
NI
Q
Q SI sout
SI
sin Scan FF
Scan FF clk
clk
M
M
 Controllability and observability using
Scan Flipflop
• Simultaneous controllability/observability
• Run circuit up to t: At t+1 make M = 1, data in SSC injected
on to z’: z loaded to SSC (Scan storage cell)
• Through serial in required data can be stored in SSC
• Through serial out data can be observed at output
z z’
C1 0
MUX C2
1
M

z
D Q
C1 C2
FF
clk
 Controllability and observability using
Scan Register
• Non Simultaneous controllability/observability
• Run circuit up to t: At t+1 if M = 1, data in SSC
injected on to z’: M=0, z’ loaded to SSC

z
C1 0 z’
MUX C2
1
M

NI
Q

FF
clk
 Controllability and observability using
Scan Register
• Observability only

z
C1 C2

NI
Q
SI
Scan FF
clk
M
 Controllability and observability using
Scan Register
• Controllability only

z
C1 0 z’
MUX C2
1
M

NI M
Q
SI
Scan FF
clk
M
 Generic scan based designs

• Full serial integrated scan

• Isolate serial scan
• Non serial scan
 Full serial integrated scan

• The concept motivated from the idea of Shift register based

testing, however reduce the problem of area overhead
• Basic idea is to convert the FFs in the circuit under test itself
to a shift register rather than using a separate one
• 2 modes – (i) test (or scan chain) mode
(ii) Working (or normal) mode
• Test mode - FFs decoupled from the circuit - connected in the
form of a shift register (called scan chain) - FFs set/reset as
required, by shifting bit values in the scan chain
• Once the FFs are set, they are removed from the scan chain
and connected back to the circuit
21
 Full serial integrated scan

Normal input D Q Sec.input

from NSF Scan out
mux clk FF (an additional pinout)
mode

Normal input D Q Sec.input

from NSF Scan out
mux clk FF
mode

Sec.input
Normal input D Q Scan out
from NSF mux clk FF

mode
Scan in
(an additional input)
 Scan chain: Advantages
• n number of clk pulses and n bit pattern are required in scan
chain method in contrast to 4n number of clock pulses and
4n bit pattern in the case of shift register method. Need for
extra 2n number of FFs is eliminated
• Required to have n number of multiplexers whose sizes are
very less compared to the size of extra FFs
• No problem of inconsistency
• FFs do not need set/reset pins, hence saving in the area
• Additional mux area is compensated by reduced sizes of FFs
• Only problem is n number of clock pulses and n bit pattern to
set/reset the FFs
• Clock can be in two different speeds
• Best method of testing of sequential circuits so far
23
ATPG and testing using scan chain:
An example
• To test the sa0 fault at net j, the signal values at nets d
and i are to be 1
Scan out

a
b j
c NI Q
1
e
. f
NI Q
i
2 D
sa0
d SI k
SI
clk 4
FF2
FF1
g h
clk 3
M
M

Scan in

24
 Scan chain: example 2
Scan out
a f
5 NI g n
b Q
SI 6
clk
FF3

M
c
d sa0 D l
e NI Q h 1
i
. j
NI
SI
Q
1
k
2
m
SI
clk 4
FF2
FF1
clk o 3 p
M
M
Scan in
25
 Scan chain: Modified application

• Scan chain can be used to set the FFs to the desired value for
testing. However, D-algorithm is required on the entire circuit
(after removing the FFs) to find the test pattern
• Scan chain eliminates the need for performing the ATPG on
the whole circuit
• Consider the input of the nearest FF from the fault site as an
output line and perform ATPG on the sub-circuit lying in the
cone of influence of that output line (i.e., inputs of the nearest
FF)

26
 Scan chain: Modified application
• Nearest FF from fault site is FF2
• Fault effect needs to be propagated to net j which is the input
of FF2
• ATPG has to be performed on the sub-circuit which lies in the
cone of influence of net j, which includes inputs d, e and AND
gate 1
• Test pattern is d=1, e=1
a f
g n
5
b 6

c
d sa0 D i l
e h 1 . j
k
2
m

4
o p 27
3
Scan chain vs. time frame expansion
method
• Time frame expansion method: dseq number of clk pulses and patterns
to set the FFs when testing
• Scan chain: n clk pulses required to set/reset ‘n’ FFs
• As n ≥ dseq, test time is higher for scan chain based testing compared
to time frame expansion method
• Also, MUXs are required in scan chain method while no extra circuitry
in time frame method
• Only ATPG complexity is less in the case of scan chain method which
is an offline exercise and test time is very expensive as patterns are
applied by an automatic test equipment
• However, scan chain method is still the most widely accepted
technology
• Time frame expansion method can’t set/reset the FFs which are cyclic.
So, scan chain based scheme or set/reset using shift register is
required for cyclic circuits
28
 Isolated serial scan
• Rs shadow register of R
• Higher overhead compared to full serial integrated
scan
• Advantage: Support some form real time and online
testing
• Single test at operational C Z
X
clock speed (else at k clock
interval) – real time test R
clk
• Online – test during normal
Sin Rs Sout
operation of circuit
 Non serial scan
• Random access scan
• Bit addressable storage cells used instead of shift
registers
• Advantage: Only selected bits can be controlled and
observed
C Z
X

Si Sin
Clocks and Addressable
control SCK
storage
element
Sout

address decoder
 Storage cells for scan design
• Clocked D-latch
• Multiplexed data flipflop (MS)
• Two port dual clock flipflop
• Multiplex data shift register latch
• Two port shift register latch
• Raceless two port D flipflop
• Polarity hold addressable latch
 Storage cells for scan design

• Clocked D-latch

NI Q

clk

• Multiplexed data flipflop (MS)

 Storage cells for scan design

• Two port dual clock flipflop

• Multiplex data shift register latch

 Storage cells for scan design

• Raceless two port D flipflop

• polarity-hold shift register latch

• Polarity hold addressable latch

 Classical Scan designs
• Scan Path: Full serial integrated scan design with
raceless master slave flipflop
• Shift register modification: Full serial integrated scan
design with multiplexed data flipflop
• Scan/set: Isolated scan
• Random access scan: use addressable storage cells
• Level sensitive scan design (LSSD)
 Level sensitive scan design (LSSD)
• Similar to scan path in concept; uses level sensitive
latches
• Absence of races and hazards
• Insensitive to rise time, fall time, delay, etc
• Lower hardware complexity as compared to scan
path design
• More complex design rules
 Polarity hold shift register latch
• Avoid delay introduced by MUX
• Normal mode: C and B clock (Master - slave)
• Shift mode: A and B clock (Master - slave)
• A and B (C and B) non overlapping – avoid race
LSSD double latch design
 LSSD single latch design
• L2 used only for shift operation
• Normal mode: C clock
• Shift mode: A and B clock (Master - slave)
• A and B non overlapping – avoid race
 Scan Overheads

• IO pins: Scan in, scan out, T, tclock

• Gate overhead: [4 nsff/(ng+10nsff)] x 100%
• Area overhead: Gate + routing
• Performance overhead: MUX delay, FF o/p
loading

40
 Routing optimization
X’
X

IO SFF
pad cell

SCANIN
Flip-
flop
cell
Y Y’

TC SCAN
OUT

Interconnects Active areas: XY and X’Y’

41
 Partial scan
• Partial scan method takes ideas both from time frame expansion
method and scan chain method
• Scan enable only in those FFs which are cyclic and keep the
remaining ones as normal
• Cyclic circuit : To get j=1, make m=1 and to get m=1, make j=1, fault
can’t be tested

m
a=1
b=1 j
c=1
D Q
1
e f
. X
D Q
i 2 X
D
sa0
X X
1 d k
clk 4
FF2
FF1
g h
clk 3

42
 Partial scan
• Two FFs are to be controlled to 1; nets d and i must be made 1
• Making net d=1 is simple and can be achieved by applying c=1 and a
clk pulse
• Control of net d via FF1 is by time frame expansion method; as dseq
=1 for FF1, one clk pulse and one pattern are enough to control it
• FF2 can’t be controlled by time frame expansion method, it must
have scan chain facility

m
a=1
b=1 j
c=1
D Q
1
e f
. X
D Q
i 2 X
D
sa0
X X
1 d k
clk 4
FF2
FF1
g h
clk 3

43
 Partial scan

• FF2 makes the scan chain

• First make m=1 and apply a 1 on scan in and a clk pulse: i=1

m
a=1
b=1 j
c=1
D Q
1 .
e f
1
NI Q
i 2 1
D
sa0
SI 1
1 d k
clk 4
FF2
FF1
g M=1 h
clk 3

Scan in

44
 Partial scan
• Now, both d and i are 1
• Make a=1, b=1, c can be X. We will get j=1, g=1 and h=0. Circuit can
be tested
• Overall sequential depth is only 1, which requires one pattern to test
it
• Some FFs set using time frame expansion and others using scan
chain based method
m
a=1
b=1 j
c=X
D Q
1 .
e f 1 NI Q
i 2 1
D
sa0 D
SI 1
1 d k
clk 4
FF2
FF1
g M=0 h
clk 3
45
 Multiple scan chains

• Mathematical complexity is higher if time frame

expansion is used; 2 test patterns and 2 clk pulses are
required in this case
• 3-bit pattern and 3 clk pulses are required if single scan
chain is used
• Multiple scan chain -- two sets of scan in and scan out
pins
• Both the chains can be loaded concurrently, thus only
two clk pulses at max. are required to set/reset the 3 FFs
• As the number of scan chains increases, number of
pinouts increases
• Trade-off between the number of pinouts and clk pulses
46
Time frame vs. single/multiple scan chains
• Time frame expansion method
 Less (dseq) number of test patterns
 Can not be used for FFs with cyclic dependency
 High Offline complexity including inconsistencies
• Full scan chain method
 Chances of collision is almost zero
 ATPG on a small sub-circuit
 n number of clk pulses and n bit pattern
• Partial scan method
 Mix of scan chain and time frame expansion
• Multiple scan chains
 Trade-off between the pinouts and clk pulses
47
 Testing of Circuit Flip-flops (Shift Test)
• Scan chain method : ability to test the FFs in the circuit
under test
• A toggle sequence 00110011…. of length n+4, where n is
the total number of FFs, applied at scan in can produce
all the 4 transitions: 0->0, 0->1, 1->1 and 1->0 in all the
FFs
• The sequence is brought out through the scan out pin
• Toggle sequence covers almost all stuck-at faults in the
FFs

48
 Automated Scan Design
Behavior, RTL, and logic
Rule
Design and verification
violations
Scan design
rule audits
Gate-level
netlist
Combinational Scan hardware
ATPG insertion
Combinational Scan
vectors netlist
Scan sequence Scan chain order Chip layout: Scan-
and test program chain optimization,
generation timing verification
Design and test
data for
Test program Mask data
manufacturing
 Commercial tools

• Scan synthesis: Encounter Test (Cadence) and

DFTMAX(Synopsys)
• Fault (opensource)
• TestMAX Advisor(Synopsis): testability analysis and
optimization
• Modus DFT (Cadence): DFT, ATPG
• Tessent FastScan (Siemens): ATPG
• Tessent RTL Pro (Siemens): analysis and insertion of test
points

50
 Boundary scan
• Developed for testing chips on a printed circuit board
(PCB)

• A chip with BS can be accessed for test from the edge

connector of PCB

• Standardization needed when different chips used for a

product

• Joint Test Action Group (JTAG) – IEEE1149

• Use wrapper to every chip to allow chip and board level

testing
51
 JTAG std.
• Allow test instruction and test data to be serially fed

• Operate system at chip, PCB or system level

• Allow other chips to collect responses

• Allow interconnect to be tested

52
Chip architecture using IEEE 1149.1 std.

53
 Boundary scan Hardware
• Test Access port (TAP)

• Four test pins - TCK, TDI, TDO and TMS

• A test controller FSM (TAP controller)

• Scan flip-flop added to each I/O pin

• n-bit instruction register(IR) holding the current

instruction

• A 1-bit Bypass register (Bypass)

• An optional 32-bit test data register: store test data or

some system-related information(such as the chip ID,
company name, etc.).
 Test Instructions

• Mandatory : BYPASS, SAMPLE, PRELOAD, EXTEST

• Optional: INTEST, RUNBIST, CLAMP, IDCODE,

USERCODE, HIGHZ

• User defined
 Typical test procedure
• Shift a boundary-scan test instruction into the IR through
the TDI

• Decode instruction - generate the required control

signals to properly configure the test logic

• Shift a test pattern into the selected data register through

the TDI - apply to the logic to be tested

• Capture the test response into some data register

• Shift captured response out through TDO – (scan in a

new test pattern through the TDI)

• Repeat steps 3 to 5
Boundary scan cell

To next
cell
To
From system
system logic
pin From 57
last cell
 Boundary scan cell
• normal =0

mode

To next
cell
To
From system
system logic
pin From 58
last cell
 Boundary scan cell
• scan =1

mode

active
To next
cell
To
From system
system logic
pin From 59
last cell
 Boundary scan cell
• update =1

mode

active
To next
cell
to
From system
system logic
pin From 60
last cell
 Boundary scan cell
• capture =0

mode

active
To next
cell
From
From system
system logic
pin From 61
last cell
Serial Board / MCM Scan
 Parallel Board / MCM Scan

Copyright 2001, Agrawal &

VLSI Test: Lecture 28 63
Bushnell
 Independent Path Board / MCM
Scan

Copyright 2001, Agrawal &

VLSI Test: Lecture 28 64
Bushnell
 Test Access Port(TAP)
• Four mandatory pins and one optional pin

• Test clock input (TCK): clock input to synchronize the

test operations (within chip/different chip on board) -
independent of the system clocks

• Test data input (TDI): test instructions and test data -

serially loaded into the instruction register/data registers

• Test data output (TDO): test data to be driven out

• Test mode select (TMS):test control input; shifting,

capturing, and updating of test data

• Test reset (TRST∗) : optional pin - asynchronous reset

 TAP Controller
TMS
 TAP Controller States
• Test–Logic–Reset: boundary-scan circuitry is disabled
-system operates in its normal mode

• Logic 0 signal applied to the TRST∗ ports

• logic 1 applied to TMS for five consecutive TCK

cycles

• Run-Test/Idle: boundary-scan circuitry waiting for

some test operations synchronized with the TCK (such
as BIST) to complete
 TAP Controller States
• Select-DR-Scan/Select-IR-Scan: temporary state in
preparation for entering the data/instruction register
manipulation column

• Capture-DR: data loaded in parallel to the data registers

selected by the current instruction

• Current test results and normal operation status

captured
 TAP Controller States
• Shift-DR: Test data scanned in series through the data
registers selected by the current instruction

• TMS = 0 - TAP controller stay in this state

• One bit of test data shifted into (out of) the selected
data register through TDI (TDO) (with each clock
cycle)

• Exit1-DR: temporary state preparing to enter the update

or pause state

• All parallel-loaded or shifted data held in the selected

data register in this state
 TAP Controller States
• Pause-DR— Pause BS function to wait for some external
operations (when a long sequence of test data is to be
loaded to the chips under test)

• TMS = 0 - TAP controller stay in this state

• Exit2-DR: indicates either completion of the current

capturing/shifting operation or the end of the Pause-DR
operation

• TAPC to enter the update state or go back to the Shift-

DR state
 TAP Controller States

• Update-DR— data are latched onto the parallel output of

selected test data registers from shift register path
 Instructions - BYPASS

• Board-level testing – send test data to or receive test

results from only one or two specific chips

• Bypass the boundary-scan registers on unused chips

• Bypass register – 1-bit register

 Instructions - SAMPLE

• Capture operation(on the rising edge of TCK in the

Capture-DR state)

• Capture signals applied to the primary inputs; capture

responses appearing at the output of the internal logic
 Instructions - PRELOAD

• Test data shifted into/out of selected data register (Shift-

DR state) without interfering with normal operation of
internal logic

• Data latched to parallel output (R2) of data registers

(falling edge of TCK in the Update-DR state)
 Instructions-EXTEST
• Test off-chip circuits and board-level interconnections

75
EXTEST-sequence
 Instructions-INTEST
• Test system logic (optional)

77
INTEST -sequence
 Other Optional Instructions
• RUNBIST: issue BIST commands to a component through
the JTAG hardware - concurrent self-test process

• CLAMP: Force component output pin signals to be driven

by the boundary-scan register (BYPASS register between
TDI and TDO)

• IDCODE: connect the component device identification

register serially between the TDI and TDO pins in the
Shift-DR TAP Controller state (only if device-ID register is
present)
 Other Optional Instructions

• USERCODE: for user-programmable components - allows

an external tester to determine the user programming of a
programmable component

• HIGHZ: puts all component output pin signals into the

high-impedance (Z) state - prevents damage to logic
when chip is not under test – TEST data bypass
 IEEE 1500 standard
• Boundary scan
standard for SoC

• One standard test

wrapper for each core

• Signal sources and

sinks for test pattern
provision and
reception

• On-chip test access

mechanism(TAM)s to
connect the wrapper to
the sources/sinks
 IEEE 1500 standard
• Wrapper serial port (WSP) - a set of I/O terminals of the
wrapper for serial operations

• wrapper serial input (WSI), the wrapper serial output

(WSO), and several wrapper serial control (WSC)
terminals

• Wrapper instruction register (WIR)

• Serial mode (without TAP controller) or parallel

mode(TAM)

• Core test language (CTL) : language for capturing and

expressing test-related information for reusable cores