ASIC Design Flow Manual using Cadence Tool Suite

for VLSI Lab – VTU

PART - B

1
 LIST OF LAB EXPERIMENTS
Exp. Name of the Experiment Page
No. No.
1 4Bit Adder 3
• Write Verilog Code
• Verify the Functionality using Test-bench.
• Synthesize the design by setting proper constraints and obtain the netlist.
• From the report generated identify Critical path, Maximum delay, Total
number of cells, Power requirement and Total area required
2 4Bit Booth Multiplier 18
• Write Verilog Code
• Verify the Functionality using Test-bench.
• Synthesize the design by setting proper constraints and obtain the netlist.
From the report generated identify Critical path, Maximum delay, Total
number of cells, Power requirement and Total area required
3 32- Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case and 27
ifstatement for ALU Behavioral Modeling
• Write Verilog Code
• Verify functionality using Test-bench.
• Synthesize the design targeting suitable library and by setting area and timing
constraints.
• Tabulate the Area, Power and Delay for the Synthesized netlist
• Identify Critical path
4 Latch and Flip-Flop 32
• Synthesize the design and compare the synthesis report (D, SR. JK)
5 UART 38
• Write Verilog Code
• Verify the Functionality using Test-bench.
• Synthesize the design targeting suitable library and by setting area and timing
constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist,
Identify Critical path
6 For synthesized netlist carry out the following: 44
• Floor planning
• Placement and Routing
• Record the parameters such as no. of metal layers used for routing, flip
method for placement of standard cells.
• Physical Verification and recording the DRC and LVS reports.
• Generate GDSII

2
 Lab 1: 4-bit Adder
Aim: To write a verilog code for 4bit adder and verify the functionality using Test bench.
• Synthesize, Analyse Reports and Netlist, Critical Path and Max Operating Frequency.
• From the report generated find the total number of cells, power requirement and total area
requirement.

Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus

Design Information and Bock Diagram:

A full adder is a combinational circuit that performs the arithmetic sum of three input bits
Ai, addend Bi and carry in C in from the previous adder. Its results contain the sum Si and the
carry out, C out to the next stage. So to design a 4-bit adder circuit we start by designing the 1 –
bit full adder then connecting the four 1-bit full adders to get the 4-bit adder as shown in the
diagram below. For the 1-bit full adder, the design begins by drawing the Truth Table for the
three input and the corresponding output SUM and CARRY.

Figure No1.1: Diagram and truth table of full adder

Figure No1.2: Diagram of 4 Bit Adder

3
Creating Source Codes

• In the Terminal, type gedit <filename>.v or <filename>.vhdl depending on the HDL

Language you are to use (ex: 4bitadder.v).
• A Blank Document opens up into which the following source code can be typed down.

Note : File name should be with HDL Extension

a) Verify the Functionality

➢ Three Codes shall be written for implementation of 4-bit Adder as follows,
✓ fa.v → Single Bit 3-Input Full Adder [Sub-Module / Function]
✓ fa_4bit.v → Top Module for Adding 4-bit Inputs.
✓ fa_test.v → Test bench

Figure No1.3: Verilog code for 4 Bit Adder

4
Functional Simulation:
➢ Invoke the cadence environment by type the below commands
✓ csh (Invokes C-Shell)
✓ source /home/install/cshrc (mention the path of the tools)
✓ (The path of cshrc could vary depending on the installation destination as
/home/install/ or /home etc.)
➢ After this you can see the window like below
➢

Figure No.1.4: Invoke the Cadence Environment

➢ To Launch Simulation tool

✓ linux:/> nclaunch -new& // “-new” option is used for invoking NCVERILOG
for the first time for any design
✓ linux:/> nclaunch& // On subsequent calls to NCVERILOG

➢ It will invoke the nclaunch window for functional simulation we can compile,elaborate
and simulate it using Multiple

➢ Figure No.1.5: Setting Multi-step simulation

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➢ Select Multiple Step and then select “Create cds.lib File” as shown in below figure
➢ Click the cds.lib file and save the file by clicking on Save option

Figure No.1.6: cds.lib file Creation

➢ Save cds.lib file and select the correct option for cds.lib file format based on the HDL
Language and Libraries used.
➢ Select “Don’t include any libraries (verilog design)” from “New cds.lib file” and click
on “OK” as in below figure
✓ We are simulating verilog design without using any libraries

Figure No. 1.7: Selection of Don’t include any libraries

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➢ A Click “OK” in the “nclaunch: Open Design Directory” window as shown in below
figure

Figure No. 1.8: Selection of OK for Creating cds.lib file

➢ A ‘NCLaunch window’ appears as shown in figure below

➢ Left side you can see the HDL files. Right side of the window has worklib and snapshots
directories listed.
➢ Worklib is the directory where all the compiled codes are stored while Snapshot will have
output of elaboration which in turn goes for simulation

Figure no1.9.: Nclaunch Window

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To perform the function simulation, the following three steps are involved Compilation,
Elaboration and Simulation.

Step 1: Compilation:– Process to check the correct Verilog language syntax and usage
Inputs: Supplied are Verilog design and test bench codes

Outputs: Compiled database created in mapped library if successful, generates report else error
reported in log file

Steps for compilation:

1. Create work/library directory (most of the latest simulation tools creates automatically)

2. Map the work to library created (most of the latest simulation tools creates automatically)

3. Run the compile command with compile options

i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v

➢ Left side select the file and in Tools : launch verilog compiler with current selection will
get enable. Click it to compile the code
➢ Worklib is the directory where all the compiled codes are stored while Snapshot will have
output of elaboration which in turn goes for simulation

Figure No1.10: Compilation Launch Option

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➢ After compilation it will come under worklib you can see in right side window.

Figure No1.11: Compiled database in worklib

➢ Select the test bench and compile it. It will come under worklib. Under Worklib you can
see the module and test-bench.

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 Figure No1.12: Compiled Test-bench Database in Worklib

The cds.lib file is an ASCII text file. It defines which libraries are accessible and where they are
located. It contains statements that map logical library names to their physical directory paths.
For this Design, you will define a library called “worklib”

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Step 2: Elaboration:– To check the port connections in hierarchical design
Inputs: Top level design / test bench Verilog codes
Outputs: Elaborate database updated in mapped library if successful, generates report else error
reported in log file
Steps for elaboration – Run the elaboration command with elaborate options
1. It builds the module hierarchy
2. Binds modules to module instances
3. Computes parameter values
4. Checks for hierarchical names conflicts
5. It also establishes net connectivity and prepares all of this for simulation

Figure No1.13: Elaboration Launch Option

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➢ After elaboration the file will come under snapshot. Select the test bench and elaborate it.

Figure No1.14: Simulation launch option

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Step 3: Simulation: – Simulate with the given test vectors over a period of time to observe
the output behaviour.
Inputs: Compiled and Elaborated top level module name
Outputs: Simulation log file, waveforms for debugging
Simulation allow to dump design and test bench signals into a waveform
Steps for simulation – Run the simulation command with simulator options

Figure No1.14: Design Browser window

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 Figure No1.15: Launching Simulation Waveform Window

Figure No1.16: Simulation Waveform Window

b) Synthesize the design using Constraints and analyse reports, critical path
and Max Operating Frequency.

Step 1: Getting Started

➢ Make sure you close out all the Incisive tool windows first.
➢ Synthesis requires three files as follows,
✓ Liberty Files (.lib)
✓ Verilog/VHDL Files (.v or .vhdl or .vhd)
✓ SDC (Synopsis Design Constraint) File (.sdc)

Step 2: Creating an SDC File

➢ In your terminal type “gedit constraints_top.sdc” to create an SDC File if you do not
have one.
➢ The SDC File must contain the following commands;

Figure No1.17: SDC file with .sdc file Extension

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Step 3 : Performing Synthesis
➢ The Liberty files are present in the below path,
/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/
➢ The Available technology nodes are 180nm ,90nm and 45nm.
➢ In the terminal, initialise the tools with the following commands if a new terminal is
being used.
✓ csh
✓ source /home/install/cshrc
➢ The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.
➢ The Following are commands to proceed,

1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl counter.v
3. elaborate
4. read_sdc constraints_top.sdc //Reading Top Level SDC
5. set_db syn_generic_effort medium //Effort level to medium for generic, mapping
and optimization
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt //Performing Synthesis Mapping and Optimisation
11. report_timing > counter_timing.rep
//Generates Timing report for worst datapath and dumps into file
12. report_area > counter_area.rep
//Generates Synthesis Area report and dumps into a file
13. report_power > counter_power.rep
//Generates Power Report [Pre-Layout]
14. write_hdl > counter_netlist.v //Creates readable Netlist File
15. write_sdc > counter_sdc.sdc //Creates Block Level SDC

15
Figure No1.18: Genus Script file with .tcl file Extension

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Synthesis RTL Schematic :

Figure No1.19: Schematic Capture of 4bit Adder

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 Lab 2: Booth Multiplier

Aim: To write a verilog code for 4bit Booth Multiplier and verify the functionality using Test
bench.
➢ Synthesize, Analyse Reports and Netlist, Critical Path and Max Operating Frequency.
➢ From the report generated find the total number of cells, power requirement and total area
requirement.

Tool Required:
➢ Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
➢ Synthesis: Genus

Design Information and Flow Chart:

The booth algorithm is a multiplication algorithm that allows us to multiply the two signed
binary integers in 2's complement, respectively. It is also used to speed up the performance of the
multiplication process. It is very efficient too. It works on the string bits 0's in the multiplier that
requires no additional bit only shift the right-most string bits and a string of 1's in a multiplier bit
weight 2k to weight 2m that can be considered as 2k+ 1 - 2m.

Figure No2.1: Flow Chart of Booth Algorithm

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 In the above flowchart, initially, AC and Qn + 1 bits are set to 0, and the SC is a sequence
counter that represents the total bits set n, which is equal to the number of bits in the multiplier.
There are BR that represent the multiplicand bits, and QR represents the multiplier bits. After
that, we encountered two bits of the multiplier as Qn and Qn + 1, where Qn represents the last bit of
QR, and Qn + 1 represents the incremented bit of Qn by 1. Suppose two bits of the multiplier is
equal to 10; it means that we have to subtract the multiplier from the partial product in the
accumulator AC and then perform the arithmetic shift operation (ashr). If the two of the multipliers
equal to 01, it means we need to perform the addition of the multiplicand to the partial product in
accumulator AC and then perform the arithmetic shift operation (ashr), including Qn + 1. The
arithmetic shift operation is used in Booth's algorithm to shift AC and QR bits to the right by one
and remains the sign bit in AC unchanged. And the sequence counter is continuously decremented
till the computational loop is repeated, equal to the number of bits (n).

Working on the Booth Algorithm

1. Set the Multiplicand and Multiplier binary bits as M and Q, respectively.

2. Initially, we set the AC and Qn + 1 registers value to 0.
3. SC represents the number of Multiplier bits (Q), and it is a sequence counter that is
continuously decremented till equal to the number of bits (n) or reached to 0.
4. A Qn represents the last bit of the Q, and the Qn+1 shows the incremented bit of Qn by 1.
5. On each cycle of the booth algorithm, Qn and Qn + 1 bits will be checked on the following
parameters as follows:
i. When two bits Qn and Qn + 1 are 00 or 11, we simply perform the arithmetic shift
right operation (ashr) to the partial product AC. And the bits of Qn and Qn + 1 is
incremented by 1 bit.
ii. If the bits of Qn and Qn + 1 is shows to 01, the multiplicand bits (M) will be added
to the AC (Accumulator register). After that, we perform the right shift operation
to the AC and QR bits by 1.
iii. If the bits of Qn and Qn + 1 is shows to 10, the multiplicand bits (M) will be
subtracted from the AC (Accumulator register). After that, we perform the right
shift operation to the AC and QR bits by 1.
6. The operation continuously works till we reached n - 1 bit in the booth algorithm.
7. Results of the Multiplication binary bits will be stored in the AC and QR registers.

There are two methods used in Booth's Algorithm

1. RSC (Right Shift Circular)
2.
It shifts the right-most bit of the binary number, and then it is added to the beginning of the binary
bits.

Figure No 2.2: Right Shift Circular

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2. RSA (Right Shift Arithmetic)

It adds the two binary bits and then shift the result to the right by 1-bit position.
Example: 0100 + 0110 => 1010, after adding the binary number shift each bit by 1 to the right
and put the first bit of resultant to the beginning of the new bit.

Example: Multiply the two numbers 7 and 3 by using the Booth's multiplication algorithm.
Ans. Here we have two numbers, 7 and 3. First of all, we need to convert 7 and 3 into binary
numbers like 7 = (0111) and 3 = (0011). Now set 7 (in binary 0111) as multiplicand (M) and 3 (in
binary 0011) as a multiplier (Q). And SC (Sequence Count) represents the number of bits, and here
we have 4 bits, so set the SC = 4. Also, it shows the number of iteration cycles of the booth's
algorithms and then cycles run SC = SC - 1 time

Qn Qn + M = (0111) AC Q Qn + SC
1 M' + 1 = (1001) & Operation 1

1 0 Initial 0000 0011 0 4

Subtract (M' + 1) 1001

1001

Perform Arithmetic Right Shift operations 1100 1001 1 3

(ashr)

1 1 Perform Arithmetic Right Shift operations 1110 0100 1 2

(ashr)

0 1 Addition (A + M) 0111

0101 0100

Perform Arithmetic right shift operation 0010 1010 0 1

0 0 Perform Arithmetic right shift operation 0001 0101 0 0

The numerical example of the Booth's Multiplication Algorithm is 7 x 3 = 21 and the binary
representation of 21 is 10101. Here, we get the resultant in binary 00010101. Now we convert it
into decimal, as (000010101)10 = 2*4 + 2*3 + 2*2 + 2*1 + 2*0 => 21.

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Source Code: booth.v

21
Testbench Code: booth_tb.v

22
Waveform:

Figure No. 2.3: Simulation waveform of Booth Multiplier

b) Synthesis and Report/Output Analysis

Step 1: Getting Started

➢ Make sure you close out all the Incisive tool windows first.
➢ Synthesis requires three files as follows,
✓ Liberty Files (.lib)
✓ Verilog/VHDL Files (.v or .vhdl or .vhd)
✓ SDC (Synopsis Design Constraint) File (.sdc)

Step 2 : Creating an SDC File

Figure No. 2.4: SDC file with .sdc file Extension

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Step 3 : Performing Synthesis
• The Liberty files are present in the below path,
/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/
➢ The Available technology nodes are 180nm ,90nm and 45nm.
➢ In the terminal, initialise the tools with the following commands if a new terminal is
being used.
✓ csh
✓ source /home/install/cshrc
➢ The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.
➢ The Following are commands to proceed,

1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {booth.v} //Reading multiple Verilog Files
3. elaborate
4. set_top_module booth.v //Differentiating Top & Sub Module
5. set_dont_use *XL //Dont Use Cells with High Driving Strength
6. set_db syn_generic_effort medium //Setting effort medium
7. set_db syn_map_effort medium
8. set_db syn_opt_effort medium
9. syn_generic
10. syn_map
11. syn_opt
//Performing Synthesis Mapping and Optimisation
12. report_timing -unconstrained > adder_timing.rep
//Generates Timing report for worst datapath and dumps into file
//-unconstrained is to be given as no timing constraints are given
13. report_area > booth_area.rep
//Generates Synthesis Area report and dumps into a file
14. report_power > booth_power.rep
//Generates Power Report [Pre-Layout]
15. write_hdl > booth_netlist.v //Creates readable Netlist File
16. write_sdc > booth_sdc.sdc //Creates Block Level SDC
17. report_qor > booth_qor.rpt // Critical slack path

Commands 1-11 are intended for Synthesis process while 12-17 for Generating reports and
Outputs.

Note 1:-

1. The Cells given in the netlist can be checked in the .lib files for their properties.
2. The Max Operating Frequency does not apply for Purely Combinational Circuit.

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read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
read_hdl booth_multiplier.v
elaborate
read_sdc input_constraints.sdc
syn_generic
syn_map
syn_opt
write_hdl > booth_netlist.v
write_sdc > output_constraints.sdc
gui_show
report timing > booth_timing.rpt
report power > booth_power.rpt
report area > booth_cell.rpt
report gates > booth_gates.rpt

Synthesis RTL Schematic :

Figure No. 2.5: Schematic Capture of Booth Multiplier

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Some Common Constraints are given below for reference

Figure No2.6: Common SDC Constraints

Note 2:-
1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints
as instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports
do not overwrite the earlier ones.

26
 Lab 3: 32-Bit ALU
Aim: Write a verilog code for 32 bit ALU supporting four logical and four arithmetic
operations, use case statement and if statement for ALU behavioral modeling.
➢ To Verify the Functionality using Test Bench
➢ Synthesize and compare the results using if and case statements
➢ Identify Critical Path and constraints

Tool Required:
➢ Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
➢ Synthesis: Genus

Design Information and Bock Diagram:

The ALU will take in two 32-bit values, and control line. An Arithmetic unit does the
following task like addition subtraction, multi-fiction and logical operations. As the input is
given in 32 bit we get 32 bit output. The arithmetic will show only one output at a time so a
selector is necessary to select one of the operator.

Figure No 3.1: Block Diagram of 32 Bit ALU

Creating a Work space :

• Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

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 a) To Verify the Functionality using Test Bench

Source Code – Using Case Statement :

module alu_32bit_case(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin
case(f)
3'b000:y=a&b; //AND Operation
3'b001:y=a|b; //OR Operation
3'b010:y=~(a&b); //NAND Operation
3'b011:y=~(a|b); //NOR Operation
3'b010:y=a+b; //Addition
3'b011:y=a-b; //Subtraction
3'b100:y=a*b; /Multiply
default:y=32'bx;
endcase
end
endmodule

Test Bench :

module alu_32bit_tb_case;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;
alu_32bit_case test2(.y(y),.a(a),.b(b),.f(f));
initial
begin
a=32'h00000000;
b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b100;
end
initial
#50 $finish;
endmodule

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Source Code - Using If Statement :

module alu_32bit_if(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin
if(f==3'b000)
y=a&b; //AND Operation
else if (f==3'b001)
y=a|b; //OR Operation
else if (f==3'b010)
y=a+b; //Addition
else if (f==3'b011)
y=a-b; //Subtraction
else if (f==3'b100)
y=a*b; //Multiply
else
y=32'bx;
end
endmodule

Test bench :

module alu_32bit_tb_if;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;
alu_32bit_if test(.y(y),.a(a),.b(b),.f(f));
initial
begin
a=32'h00000000;
b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b100;
end
initial
#50 $finish;
endmodule

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Wave Forms :

Figure No 3.2: Simulation Waveform of 32-Bit ALU

b) Synthesize Design
• Run the synthesis Process one time for each code and make sure the output File names
are changed accordingly.

Synthesis Process :
1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {alu_32bit_if.v (OR) alu_32bit_case.v} //Choose any one
3. elaborate
4. read_sdc constraints_top.sdc //Optional-Reading Top Level SDC
5. set_db syn_generic_effort medium //Setting effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt
//Performing Synthesis Mapping and Optimisation
11. report_timing > alu_timing.rep
//Generates Timing report for worst datapath and dumps into file
12. report_area > alu_area.rep
//Generates Synthesis Area report and dumps into a file
13. report_power > uart_power.rep
//Generates Power Report [Pre-Layout]
14. write_hdl > uart_netlist.v
//Creates readable Netlist File
15. write_sdc > uart_sdc.sdc
//Creates Block Level SDC

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Synthesis RTL Schematic :

Figure No 3.3: Schematic Capture of 32-Bit ALU

Note :-

1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints
as instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports
do not overwrite the earlier ones.

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 Lab 4: Latches and Flip Flops

Aim: Write a verilog code for Latch and Flip-flops (D, SR, JK), Synthesize the design and
compare the synthesis report.

Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus

Design Information and Bock Diagram:

Latches and flip-flops are the basic elements for storing information. One latch or flip-
flop can store one bit of information. The main difference between latches and flip-flops is that
for latches, their outputs are constantly affected by their inputs as long as the enable signal is
asserted.
In other words, when they are enabled, their content changes immediately when their
inputs change. Flip-flops, on the other hand, have their content change only either at the rising or
falling edge of the enable signal. This enable signal is usually the controlling clock signal. After
the rising or falling edge of the clock, the flip-flop content remains constant even if the input
changes.
There are basically four main types of latches and flip-flops: SR, D, and JK. The major
differences in these flip-flop types are the number of inputs they have and how they change state.
For each type, there are also different variations that enhance their operations.

Example: D-Flip-flop

Figure No5.1: Block Diagram and Truth Table of D-Flip Flop

Creating a Work space :

• Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

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a) Verilog Codes for D-Flip Flop, JK-Flip Flop and SR-Flip Flop.

Source code for D-Flip Flop:

Source code for D-Latch:

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Source code for SR Flip Flop :

Source Code for SR Latch:

34
Source Code for JK Flip Flop :

Source of JK Latch :

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Wave Forms for D-Flip Flop:

Figure No 4.2: Simulation Waveform of D Flip-Flop

b) Synthesize the Design & Comparing Reports

Synthesis Commands :
1. read_libs /home/install_run/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl dff.v
3. elaborate
4. read_sdc constraints_top.sdc
5. set_db syn_generic_effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt
11. report_timing > dff_timing.rep
12. report_area > dff_area.rep
13. report_power > dff_power.rep
14. write_hdl > dff_netlist.v
15. write_sdc > dff_sdc.sdc

Example for SDC:

Figure No 4.3: SDC for a D Flip-Flop

The Above is the example SDC for a D Flip Flop

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 Figure No5.4: SDC file for a D Latch

The above is an Example for SDC File for D Latch.

Synthesis RTL Schematic :

Figure No5.5: Schematic Capture of D Flip-Flop

Note :-

1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints
as instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports
do not overwrite the earlier ones.

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 Lab 9: UART

Aim: Write a verilog code for UART and carry out the following:
• To Verify the Functionality using test Bench
• Synthesize Design using constraints
• Tabulate Reports using various Constraints
• Identify Critical Path and calculate Max Operating Frequency

Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus

Design Information and Bock Diagram:

The UART is “Universal Asynchronous Receiver/Transmitter”, and it is an inbuilt IC

within a micro-controller but not like a communication protocol (I2C & SPI). The main function
of UART is to serial data communication. In UART, the communication between two devices
can be done in two ways namely serial data communication and parallel data communication.
The transmitter section includes three blocks namely transmit hold register, shift register
and also control logic. Likewise, the receiver section includes a receive hold register, shift
register, and control logic. These two sections are commonly provided by a baud-rate-generator.
This generator is used for generating the speed when the transmitter section & receiver section
has to transmit or receive the data.

Figure No3.1.: Block Diagram of UART

Creating a Workspace :
• Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

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a) Functional Verification using Test Bench

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Waveform :

Figure No 5.2: Simulation Waveform of UART

b) Synthesis and Report/Output Analysis

Step 1: Getting Started

• Make sure you close out all the Incisive tool windows first.
• Synthesis requires three files as follows,
◦ Liberty Files (.lib)
◦ Verilog/VHDL Files (.v or .vhdl or .vhd)
◦ SDC (Synopsis Design Constraint) File (.sdc)
Step 2 : Creating an SDC File
• As the Full Adder Program does not contain any Clock, SDC can be skipped as an Input
if you wish to, else you could include only Area Constraints in form of commands during
synthesis such as,
set_dont_use *XL (Indicating not to use Larger Cells)

Figure No 4.3: SDC for a UART

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Step 3 : Performing Synthesis
• The Liberty files are present in the below path,
/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/
• The Available technology nodes are 180nm ,90nm and 45nm.
• In the terminal, initialise the tools with the following commands if a new terminal is
being used.
◦ csh
◦ source /home/install/cshrc
• The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.
• The Following are commands to proceed,

1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {uart.v} //Choose any one
3. elaborate
4. read_sdc constraints_top.sdc //Reading Top Level SDC
5. set_db syn_generic_effort medium //Setting effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt //Performing Synthesis Mapping and Optimisation
11. report_timing > uart_timing.rep
//Generates Timing report for worst datapath and dumps into file
12. report_area > uart_area.rep
//Generates Synthesis Area report and dumps into a file
13. report_power > uart_power.rep
//Generates Power Report [Pre-Layout]
14. report_qor > uart_qor.rep
15. write_hdl > uart_netlist.v
//Creates readable Netlist File
16. write_sdc > uart_sdc.sdc
//Creates Block Level SDC

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Synthesis RTL Schematic :

Figure No3.3: Schematic Capture of UART Design

Note :-
1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints
as instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports
do not overwrite the earlier ones.

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 Lab 10: Physical Design

Aim: For the synthesized netlist carry out the following any two above experiments:
• Floor planning, identify the placement of pads, placement and Routing

Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus
• Physical Design: Innovus

Mandatory Inputs for PD:

1. Gate Level Netlist [Output of Synthesis]
2. Block Level SDC [Output of Synthesis]
3. Liberty Files (.lib)
4. LEF Files (Layer Exchange Format)

Expected Outputs from PD:

1. GDS II File (Graphical Data Stream for Information Interchange – Feed In for
Fabrication Unit).
2. SPEF, SDF

• Make sure the Synthesis for the target design is done and open a terminal from the
corresponding workspace.
• Initiate the Cadence tools and cmd :innovus (Press Enter)
• For Innovus tool, a GUI opens and also the terminal enters into innovus command
prompt where in the tool commands can be entered.

Physical Design involves 5 stages as following :

After Importing Design,
→ Floor Planning
→ Power Planning
→ Placement
→ CTS (Clock Tree Synthesis)
→ RoutingModule

Importing Design

To Import Design, all the Mandatory Inputs are to be loaded and this can be done either using
script files named with .globals and .view/.tcl or through GUI as shown below.

The target design considered here UART design

The procedure shall remain the same for any other design from the above discussed experiments.

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Note :

1. For Synthesis, slow.lib was read as input. Each liberty file contains a pre-defined Process,
Voltage and Temperature (PVT) values which impact the ease of charge movement.
2. Process, Voltage and Temperature individually affect the ease of currents as depicted
below.

3. Hence, slow.lib contains PVT combination (corner) with slow charge movement =>
Maximum Delay => Worst Performance
4. Similarly, fast.lib contains PVT Combination applicable across its designs to give Fast
charge movement => Minimum Delay => Best Performance.
5. When these corners are collaborated with the sdc, they can be used to analyse timing for
setup in the worst case and hold in the best case.
6. All these analysis views are to be manually created either in the form of script or using
the GUI.

Figure No6.1: Script file of Default.globals file

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Figure No6.2: Script file of Default.view (or) Default.tcl file

Note : Check the paths to properly read in the input files.

• Else, if you would like to import your design using GUI, open the Innovus tool and from
the GUI, go to File → Import Design.
• A new pop-up window appears.
• First load the netlist. You can browse for the file and select “Top cell : Auto Assign”.

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Similarly select your lef files from /home/install/FOUNDRY/digital/90nm/dig/lef/ as shown
below.

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Once LEF Files are loaded, your import design window is as follows.

Next step is to create the power supply pins both VDD and VSS

• In order to load the Liberty File and SDC, create delay corners and analysis view, select
the “Create Analysis Configuration” option at the bottom.

• An MMMC browser Pops Up.

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The order of adding the MMMC Objects is as follows.
1. Library Sets
2. RC Corners
3. Delay Corners
4. Constraints (SDC)

Once all of them are added, Analysis Views are created and assigned to Setup and Hold.

In order to add any of the objects, make a right click on the corresponding label → Select New.

• Adding Liberty Files under “Library Sets”

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• Similarly, add fast.lib with a label Fast or any identifier of your own.

• Adding RC Corners can also be done in a similar process. The temperature value can be
found under the corresponding liberty file. Also, cap table and RC Tech files can be
added from Foundry where available.

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• Delay Corners are formed by combining Library Sets with RC Corners.
• An example is shown below.

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• Similarly, SDC can be read in under the MMMC Object of “Constraints”.

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• Analysis Views are formed from combinations of SDC and Delay Corner.

• Once “Best” and “Worst” Analysis views are created, assign them to Setup and Hold.

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• Once all the process is done, Click on “Save&Close” and save the script generated with
any name of your choice.
• Make sure the file extension remains .view or .tcl
• After saving the script, go back to Import Design window and Click “OK” to load your
design.

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In the Import Design window click the save option to save the Default.globals file

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To load the complete netlist and the analysis configuration to the Innovus tool

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• A rectangular or square box appears in your GUI if and only if all the inputs are read
properly.

• If the box does not appear, check for errors in your log (Either on terminal or log file
from pwd)

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 • The internal area of the box is called “Core Area”.
• The horizontal lines running along the width of Core are “Standard Cell Rows”. Every
alternate of them are marked indicating alternate VDD and VSS rows.
• This setup is called “Flipped Standard Cell Rows”.

→ Floorplan

Steps under Floorplan :

1. Aspect Ratio [Ratio of Vertical Height to Horizontal Width of Core]
2. Core Utilisation [The total Core Area % to be used for Floor Planning]
3. Channel Spacing between Core Boundary to IO Boundary

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• Select Floorplan → Specify Floorplan to modify/add concerned values to the above
Factors. On adding/modifying the concerned values, the core area is also modified.

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 • The Yellow patch on the Left Bottom are the group of “Unassigned pins” which are to be
placed along the IO Boundary along with the Standard Cells [Gates].

→ Power Planning

Steps under Power Planning :

1. Connect Global Net Connects
2. Adding Power Rings
3. Adding Power Strings
4. Special Route

Under Connect Global Net Connects, we create two pins, one for VDD and one for VSS
connecting them to corresponding Global Nets as mentioned in Globals file / Power and Ground
Nets.

1. Select Power → Connect Global Nets.. to create “Pin” and “Connect to Global Net” as
shown and use “Add to list”.
2. Click on “Apply” to direct the tool in enforcing the Pins and Net connects to Design and
then Close the window.

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• In order to Tap in Power from a distant Power supply, Wider Nets and Parallel
connections improve efficiency. Moreover, the cells that would be placed inside the core
area are expected to have shorter Nets for lower resistance.
• Hence Power Rings [Around Core Boundary] and Power Stripes [Across Core Boundary]
are added which satisfies the above conditions.
• Select Power → Power Planning → Add Rings to add Power rings ‘around Core
Boundary’.

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• Select the Nets from Browse option OR Directly type in the Global Net Names separated
by a space being Case and Spelling Sensitive.
• Select the Highest Metals marked ‘H’ [Horizontal] for Top and Bottom and Metals
marked ‘V’ [Vertical] for Right and Bottom. This is because Highest metals have Highest
Widths and thus Lowest Resistance.
• Click on Update after the selection and “Set Offset : Centre in Channel” in order to get
the Minimum Width and Minimum Spacing of the corresponding Metals and then Click
“OK”.
• Similarly, Power Stripes are added using similar content to that of Power Rings.

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Factors to be considered under Power Stripes :
→ Nets
→ Metal and It’s Direction
→ Width and Spacing [Updated]
→ Set to Set Distance = ( Minimum Width of Metal + Min. Spacing ) x 2

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• On adding Power Stripes, The Power mesh setup is complete as shown. However, There
are no Vias that could connect Metal 9 or Metal 8 directly with Metal 1 [VDD or VSS of
Standard Cells are generally made up of Metal 1].
• The connection between the Highest and Lowest Metals is done through Stacking of Vias
done using “Special Route”.
• To perform Special Route, Select Route → Special Route → Add Nets → OK.
• After the Special Route is complete, all the Standard Cell Rows turn to the Color coded
for Metal 1 as shown below.

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The complete Power Planning process makes sure Every Standard Cell receives enough power to
operate smoothly.

→ Pre – Placement :
• After Power Planning, a few Physical Cells are added namely, End Caps and Well Taps.
• End Caps : They are Physical Cells which are added to the Left and Right Core
Boundaries acting as blockages to avoid Standard Cells from moving out of boundary.
• Well Taps : They act like Shunt Resistance to avoid Latch Up effects.

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To add End Caps, Select Place → Physical Cell → Add End Caps and “Select” the FILL’s from
the available list.
• Higher Fills have Higher Widths. As shown Below, The End Caps are added below your
Power Mesh.

• To add Well Taps, Select Place → Physical Cell → Add Well Tap → Select →FillX [X →
Strength of Fill = 1,2,4 etc] → Distance Interval [Could be given in range of 30-45u] →
OK

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→ Placement
1. The Placement stage deals with Placing of Standard Cells as well as Pins.
2. Select Place → Place Standard Cell → Run Full Placement → Mode → Enable ‘Place
I/O Pins’ → OK → OK .

• All the Standard Cells and Pins are placed as per the communication between them, i.e.,
Two communicating Cells are placed as close as possible so that shorter Net lengths can
be used for connections as Shorter Net Lengths enable Better Timing Results.

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• You can toggle the Layer Visibility from the list on the Right. The List of Layers
available are shown on the right under “Layer” tab with colour coding.

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→ Report Generation and Optimization :
1. Timing Report :
1. To generate Timing Report, Timing → Report Timing → Design Stage – PreCTS
2. Analysis Type – Setup → OK
3. The Timing report Summary can be seen on the Terminal.
2. Area Report :
1. cmd : report_area
3. Power Report :
1. cmd : report_power

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• In case of any Violating paths, the design could be optimized in the following way.
• To optimize the Design, Select ECO → Optimize Design → Design Stage [PreCTS] →
Optimization Type – Setup → OK

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 • After you run the optimization, the terminal displays the latest Timing report and updated
area and power reports can be checked.

• This step Optimizes your design in terms of Timing, Area and Power. You can Generate
Timing, Area, Power in similar way as above report Post – Optimization to compare the
Reports.

→Clock Tree Synthesis

• The CTS Stage is meant to build a Clock Distribution Network such that every Register
(Flip Flop) acquires Clock at the same time (Atleast Approximately) to keep them in
proper communication.
• A Script can be used to Build the Clock Tree as follows :

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• Source the Script as shown in the above snapshot through the Terminal and then Select
Clock → CCOpt Clock Tree Debugger → OK to build and view clock tree.

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 • The Red Boxes are the Clock Pins of various Flip Flops in the Design while Yellow
Pentagon on the top represents Clock Source.
• The Clock Tree is built with Clock Buffers and Clock Inverters added to boost up the
Clock Signal

Report Generation and Design Optimization :

• CTS Stage adds real clock into the Design and hence “Hold” Analysis also becomes
prominent. Hence, Optimizations can be done for both Setup & Hold, Timing Reports are
to be Generated for Setup and Hold Individually.

Setup Timing Analysis :

Hold Timing Analysis :

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Routing :

1. All the net connections shown in the GUI till CTS are only based on the Logical
connectivity.
2. These connections are to be replaced with real Metals avoiding Opens, Shorts, Signal
Integrity [Cross Talks], Antenna Violations etc.
3. To run Routing, Select Route → Nano Route → Route and enable Timing Driven and SI
Driven for Design Physical Efficiency and Reliability.

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Area and Power Reports :
Use the commands report_area and report_power for Area and Power Reports
respectively.

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• As an alternate to the setAnalysisMode command, you can use the GUI at Tools → Set
Mode → Set Analysis Mode → Select On-Chip-Variation and CPPR.

• The Report generation is same as shown prior to Design Optimization.

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It is recommended to save Netlist and Design at every stage.

To restore a Design Data Base, type source <DesignName>.enc in the terminal.

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 Physical Verification – Capturing DRC and LVS:

• After saving the routed Database, you can proceed for Physical Verification and capture
the DRC and LVS reports.
• Inputs Required – DRC :
◦ Technology Library and Rule Set
◦ GDS format giles of all Standard Cells (Given by Cadence at
/home/install/FOUNDRY/90nm/dig/gds for 90nm Tech node)
• Outputs – DRC :
◦ DRC Violation Report
◦ Physical Netlist (Optional)
From the Innovus GUI, select PVS → Run DRC to open the “DRC Submission Form”.

The DRC Run Submission Form begins with mentioning the Run Directory. The Run Directory
is the location where all the logs, reports and other files concerned with PVS are saved.

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The technology Library is to be loaded under “Rules tab”.

• The Technology Library is specific for PVS Tool and technology node on which the
design is created.
• On reading the tech lib, the rule set is loaded and the corresponding fabrication rules are
read in to be checked against the design.

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• The GDS format files of all standard cells available with the corresponding technology
node are also provided by the vendor. Select all of them to add.

• The output report can be named and saved as shown.

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• Hit “Submit” to run the DRC and the following windows appear.

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• All the list of DRC Errors can be seen in the above window of which the location of the
DRC Violation occuring can be highlighted dealing one to one.

• For example, in the above shown snapshot, the errors associated with N-Implant can be
seen. (Select a error occurrence and click on the right arrow below to highlight/zoom in
the location.)
• You can save the DRC Run as a “Preset” file to rerun the DRC if required at a later point
of time.
• Saving/loading the Preset File is shown below.

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 • Loading a Preset file is shown below.

Note : A Physical Netlist can be saved after the DRC Run as shown below.

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• Inputs Required – LVS :
◦ Technology Library
◦ Standard Cell GDS Files
◦ Spice Netlist of all Standard Cells (Provided by Library Vendor)
• Outputs – LVS :
◦ LVS Match/Mismatch Report

• From the Innovus GUI, Select PVS → Run LVS to open the LVS run submission form.

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• Provide the Run directory and log file name (Along with path – Optional)
• Load the Tech Lib, GDS Files and Spice Netlist of all Standard Cells under the
corresponding technology node.

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• On successful completion of LVS Run, the following windows appear.

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95
• You can create a GDS file along with Stream out file either using the GUI as File → Save
→ GDS/Oasis or use the following command.
• Cmd : streamOut <GDSFileName>.gds -streamOut <streamOut>.map or
• innovus 1> streamOut design_GDS.gds -mapFile streamOut2.map -libName Mydesign -
merge {/home/install/FOUNDRY/digital/90nm/dig/gds/*.gds} -units 2000 -mode ALL

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97

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