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8 views

Repost Lab 3

llllllllllllllll

Uploaded by

letranxuantao
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VIETNAM NATIONAL UNIVERSITY, HO CHI MINH CITY

UNIVERSITY OF TECHNOLOGY
FACULTY OF COMPUTER SCIENCE AND ENGINEERING

LAB 3
Subject: Digital Systems

Group: 4
GVHD: Tôn Huỳnh Long

Student:

Full name MSSV


Phạm Lê Ngọc Ngân 2452808
Lê Bảo Nguyên 2452847
Lê Trần Xuân Tảo 2453143
Vũ Minh Quân 2453084

INDEX
I. Experience 1 3
1. Experience request ………………………………………………………….…… 3

2. Design……………………………………………………………………………. 3

3. Simulation ……………………………………………………………………..... 4

II. Experience 2 6

1. Experience request ………………………………………………………….…… 6

2. Design…………………………………………………………………………… 6

3. Simulation ……………………………………………………………………..... 6

III. Experience 3 9

1. Experience request ………………………………………………………….…… 9

2. Design…………………………………………………………………………… 9

3. Simulation ……………………………………………………………………..... 9

I. Experience 1
1. Experience request

Design, simulate and implement a D Flip-flop using J-K Flip-flops (allowed to use
other logic gates if necessary)

2. Design
● IC Selection
To meet the requirements of the experiment, we need to use one IC 7404
and one IC 7473.
● Theory
To configure a J-K Flip-Flop to operate as a D Flip-Flop, we follow these
steps:

Figure 2. Truth Table of the D Flip-Flop Obtained Through the J-K Flip-Flop.

Karnaugh Map
Figure 3. Karnaugh Map Indicating the Input Values of J and K.

3. Simulation

Figure 4. Simulation Diagram


Net-list

II. Experience 2.
1. Experience request.

Design, simulate and implement the following logic circuit.


Observe the operation of circuits and answer the following questions.

a. Assume that QA, QB, QC are connected to the LEDs. What is the phenomenon
of the LEDs? What is the difference among LEDs?

b. How many minimum D Flip-flops required to build a circuit in which the output
frequency is 16 times less than the Clock In frequency?

2. Design.
● IC Selection
To meet the requirements of the experiment, we need to use at least 2 IC
7474 (because each IC will have 2 D flip flops) to create 3 asynchronous
D flip flops as required. It is easy to see that this is an asynchronous up
counter from 0 to 7.
3. Simulation
PIN 1 PIN 2
1 PIN 7 Pin 14 of U1
2 GND Pin 7 of U1
3 PIN 7 Pin 14 of U2
4 GND Pin 7 of U2

5 Clock Pin 3 of U1
6 Pin 5 of U1 Pin 11 of U1
7 Pin 6 of U1 Pin 2 of U1
8 Pin 6 of U1 Led 1
9 Pin 8 of U1 Pin 12 of U1
10 Pin 8 of U1 Led 2
11 Pin 9 of U1 Pin 3 of U2
12 Pin 6 of U2 Pin 2 of U2
13 Pin 6 of U2 Led 3
14 SW1 Pin 1 of U1
15 SW1 Pin 4 of U1
16 SW1 Pin 10 of U1
17 SW1 Pin 13 of U1
18 SW1 Pin 1 of U2
19 SW1 Pin 4 of U2

a. LEDs 1 2 3 correspond to QA QB QC, change according to the up-


counting principle from 0 to 7, we have the following table of LED
changes:

From the table above, we can see that the frequency of LED 1 is twice the
frequency of LED 2 and four times the frequency of LED 3.
=> Conclusion: This is an asynchronous up counter from 0 to 7.
b. For every D Flip-flop, the output frequency will be half the clock frequency.
So after n D Flip-flop, the output frequency will decrease by 2^n times.
Therefore, to decrease the output frequency by 16 times, which is equivalent
to 2^4 times, a minimum of 4 D Flip-flop is required.

III. Experience 3
1. Experience request
2. Design

3. Simulation

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