1, BOOTH MULTIPLIER

module boothmul(
input[3:0]multiplicand,
input[3:0]multiplier,
output reg[7:0]product
);
reg[3:0] A,Q,M;
reg Q_1;
integer i;
always@(multiplicand or multiplier)begin
A=4'b0;
M=multiplicand;
Q=multiplier;
Q_1=1'b0;
product=8'b0;
for(i=0;i<4;i=i+1)begin
case({Q[0],Q_1})
2'b01:A=A+M;
2'b10:A=A-M;
default: ;
endcase
{A,Q,Q_1}={A[3],A,Q};
end
product={A,Q};
end
endmodule

----------------------

module boothmul_tb;
reg[3:0] multiplicand;
reg[3:0] multiplier;
wire[7:0] product;
boothmul uut(.multiplicand(multiplicand),.multiplier(multiplier),.product(product));
initial begin
multiplicand=0;
multiplier=0;
//#10 multiplicand=4'b0011;multiplier=4'b0101;
//#10 multiplicand=4'b1101;multiplier=4'b1010;
#10 multiplicand=4'd4;multiplier=4'd3;
#10 multiplicand=4'd5;multiplier=4'd2;
#10 multiplicand=-4'd7;multiplier=4'd3;

#10 multiplicand=-4'd7;multiplier=4'd3;

$finish;
end
initial begin
$monitor($time,"multiplicand=%d,multiplier=%d,product=%d",multiplicand,multiplier,product);
end
endmodule

2, ALU

module alu (
input wire [3:0] a, // 4-bit input A
input wire [3:0] b, // 4-bit input B
input wire [2:0] op, // 3-bit operation selector
output reg [3:0] result, // 4-bit result
output reg carry_out, // Carry out for addition/subtraction
output reg zero // Zero flag
);

// Operation codes
parameter ADD = 3'b000;
parameter SUB = 3'b001;
parameter AND = 3'b010;
parameter OR = 3'b011;
parameter XOR = 3'b100;
parameter NOT = 3'b101;

always @(*) begin

case (op)
ADD: begin
{carry_out, result} = a + b; // Perform addition with carry
end
SUB: begin
{carry_out, result} = a - b; // Perform subtraction with carry
 end
AND: begin
result = a & b; // Perform bitwise AND
carry_out = 0;
end
OR: begin
result = a | b; // Perform bitwise OR
carry_out = 0;
end
XOR: begin
result = a ^ b; // Perform bitwise XOR
carry_out = 0;
end
NOT: begin
result = ~a; // Perform bitwise NOT on input A only
carry_out = 0;
end
default: begin
result = 4'b0000; // Default case
carry_out = 0;
end
endcase
zero = (result == 4'b0000); // Set zero flag if result is zero
end
endmodule

`timescale 1ns / 1ps

module tb_alu;

reg [3:0] a;
reg [3:0] b;
reg [2:0] op;
wire [3:0] result;
wire carry_out;
wire zero;

alu uut (
.a(a),
.b(b),
 .op(op),
.result(result),
.carry_out(carry_out),
.zero(zero)
);

// Test sequence
initial begin
// Initialize signals
a = 4'd0;
b = 4'd0;
op = 3'b000;

// Test Case 1: Addition

#10 a = 4'd5; b = 4'd3; op = 3'b000; // a + b = 8
#10;

// Test Case 2: Subtraction

a = 4'd5; b = 4'd3; op = 3'b001; // a - b = 2
#10;

// Test Case 3: AND

a = 4'd7; b = 4'd3; op = 3'b010; // a & b = 3
#10;

// Test Case 4: OR
a = 4'd7; b = 4'd3; op = 3'b011; // a | b = 7
#10;

// Test Case 5: XOR

a = 4'd7; b = 4'd3; op = 3'b100; // a ^ b = 4
#10;

// Test Case 6: NOT

a = 4'd5; op = 3'b101; // ~a = -6 (in 4-bit 2's complement: 1010)
#10;
 // Test Case 7: Invalid operation
a = 4'd0; b = 4'd0; op = 3'b111

4, MAC

module mac (
input wire clk,
input wire reset,
input wire [3:0] a,
input wire [3:0] b,
output reg [7:0] acc_out
);

// Multiply and accumulate on positive clock edge

always @(posedge clk or posedge reset) begin
if (reset) begin
acc_out <= 8'b0; // Reset accumulator to 0
end else begin
acc_out <= acc_out + a * b; // Perform MAC operation
end
end
endmodule

`timescale 1ns / 1ps

module tb_mac;
reg clk;
reg reset;
reg [3:0] a;
reg [3:0] b;
wire [7:0] acc_out;

// Instantiate the MAC unit

mac uut (
.clk(clk),
.reset(reset),
.a(a),
.b(b),
.acc_out(acc_out)
);

// Clock generation with 10ns period

always begin
#5 clk = ~clk;
end

initial begin
// Initialize inputs
clk = 0;
reset = 1;
a = 4'd1;
b = 4'd2;

// Apply reset pulse

#10 reset = 0;

// Test Case 1
a = 4'd3; b = 4'd4; #10;
$display("At time=%t, a=%d, b=%d, acc_out=%d", $time, a, b, acc_out);

// Test Case 2
a = 4'd5; b = 4'd6; #10;
$display("At time=%t, a=%d, b=%d, acc_out=%d", $time, a, b, acc_out);

// Test Case 3
a = 4'd7; b = 4'd8; #10;
$display("At time=%t, a=%d, b=%d, acc_out=%d", $time, a, b, acc_out);

// Finish simulation
$finish;
end

// Monitor changes in acc_out for debugging

initial begin
$monitor("Time=%t | a=%d | b=%d | acc_out=%d", $time, a, b, acc_out);
 end
endmodule

5, UPC

module syn_counter(
input clk,
input reset,
input up_down,
output [3:0] counter
);
wire [3:0] d;
wire [3:0] q;

// Instantiate D flip-flops for each bit of the counter

d_flip_flop dff0 (.clk(clk), .reset(reset), .d(d[0]), .q(q[0]));
d_flip_flop dff1 (.clk(clk), .reset(reset), .d(d[1]), .q(q[1]));
d_flip_flop dff2 (.clk(clk), .reset(reset), .d(d[2]), .q(q[2]));
d_flip_flop dff3 (.clk(clk), .reset(reset), .d(d[3]), .q(q[3]));

// Connect the output

assign counter = q;

// Next state logic for up/down counter

assign d = up_down ? (q - 4'b0001) : (q + 4'b0001); // Decrement if up_down=1, increment if
up_down=0

endmodule
(structural)
module counter (
input wire up_down, // Direction control: 1 for up, 0 for down
input wire clk, // Clock input
input wire rst, // Reset input
output reg [3:0] counter // 4-bit counter output
);

// Synchronous reset and counter logic

always @(posedge clk or posedge rst) begin
if (rst)
 counter <= 4'b0000; // Reset counter to 0 on rst
else if (up_down)
counter <= counter + 1'b1; // Increment counter if up_down is 1
else
counter <= counter - 1'b1; // Decrement counter if up_down is 0
end
endmodule

`timescale 1ns / 1ps

module tb_up_down_counter_structural;
reg clk;
reg reset;
reg up_down;
wire [3:0] counter;

// Instantiate the up-down counter

syn_counter uut (
.clk(clk),
.reset(reset),
.up_down(up_down),
.counter(counter)
);

// Clock generation with a period of 10 time units

always #5 clk = ~clk;

initial begin
// Initialize signals
clk = 0;
reset = 1;
up_down = 0;

// Apply reset for 10 time units

#10 reset = 0;
 // Test counting up
up_down = 0;
#100; // Let counter increment for 100 time units

// Test counting down

up_down = 1;
#100; // Let counter decrement for 100 time units

// End simulation
$stop;
end

// Monitor the counter value, up_down, reset, and clk for debugging
initial begin
$monitor("Time = %0t | Counter = %b | Up_Down = %b | Reset = %b | CLK = %b", $time,
counter, up_down, reset, clk);
end
endmodule

6, MEALY

`timescale 1ns / 1ps

module seq_detector(
input x,
input clk,
input reset,
output reg z
);
// State encoding
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
reg [1:0] PS, NS;

// Sequential state register block

always @(posedge clk or posedge reset) begin
if (reset)
PS <= S0;
else
PS <= NS;
end
 // Sequential output block
always @(posedge clk or posedge reset) begin
if (reset)
z <= 1'b0;
else
z <= (PS == S3) && x;
end

// Combinational state assignment block

always @(*) begin
case (PS)
S0: NS = x ? S1 : S0;
S1: NS = x ? S1 : S2;
S2: NS = x ? S3 : S0;
S3: NS = x ? S1 : S2;
default: NS = S0;
endcase
end
endmodule

`timescale 1ns / 1ps

module testbench;
// Inputs
reg x;
reg clk;
reg reset;
// Outputs
wire z;

// Instantiate the Unit Under Test (UUT)

seq_detector uut (
.x(x),
.clk(clk),
.reset(reset),
.z(z)
);

// Clock generation
 always #5 clk = ~clk;

initial begin
// Set up the waveform dump
$dumpfile("dump.vcd");
$dumpvars(1, testbench);

// Initialize inputs
clk = 1'b0;
reset = 1'b1;
#15 reset = 1'b0;

// Apply test sequence

#12 x = 0;
#10 x = 0;
#10 x = 1;
#10 x = 0;
#12 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#12 x = 1;
#10 x = 0;
#10 x = 0;
#10 x = 1;
#12 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 $finish;
end

// Monitor to observe changes

initial begin
$monitor("Time = %0t | x = %b | PS = %b | z = %b", $time, x, uut.PS, z);
end
endmodule

(structural)
module d_ff(
 input d,
input clk,
input reset,
output reg q
);
always @(posedge clk or posedge reset) begin
if (reset)
q <= 0;
else
q <= d;
end
endmodule

(JUST WRITE FOR MEALY)

7, USR
module UniversalShiftRegister_4bit (
input clk, // Clock signal
input reset, // Asynchronous reset signal
input [2:0] control, // Control word input (3 bits)
input serial_in_left, // Serial input for left shifting
input serial_in_right, // Serial input for right shifting
input [3:0] parallel_in, // Parallel input data (4 bits)
output reg [3:0] data_out // 4-bit Output data
);

always @(posedge clk or posedge reset) begin

if (reset) begin
data_out <= 4'b0000; // Reset the register to 0
end
else begin
case (control)
3'b000: data_out <= data_out; // No operation
3'b001: data_out <= {data_out[2:0], serial_in_left}; // SISO (left shift with serial input)
3'b010: data_out <= {serial_in_right, data_out[3:1]};// SISO (right shift with serial input)
3'b011: data_out <= {data_out[2:0], serial_in_left}; // SIPO (left shift with serial input)
3'b100: data_out <= {serial_in_right, data_out[3:1]};// SIPO (right shift with serial input)
3'b101: data_out <= {parallel_in[3], data_out[3:1]}; // PISO (parallel-in, left-out)
3'b110: data_out <= {data_out[2:0], parallel_in[0]}; // PISO (parallel-in, right-out)
3'b111: data_out <= parallel_in; // PIPO (parallel load)
default: data_out <= data_out; // Default case (no operation)
endcase
end
end
endmodule

module tb_UniversalShiftRegister_4bit;
reg clk;
reg reset;
reg [2:0] control;
reg serial_in_left;
reg serial_in_right;
reg [3:0] parallel_in;
wire [3:0] data_out;

// Instantiate the Universal Shift Register

UniversalShiftRegister_4bit uut (
.clk(clk),
.reset(reset),
.control(control),
.serial_in_left(serial_in_left),
.serial_in_right(serial_in_right),
.parallel_in(parallel_in),
.data_out(data_out)
);

// Clock generation
always #5 clk = ~clk;

initial begin
// Initialize inputs
clk = 0;
reset = 1;
control = 3'b000;
serial_in_left = 1;
serial_in_right = 0;
parallel_in = 4'b1010;

// Reset the register

#10 reset = 0;

// Test parallel load (PIPO)

 control = 3'b111;
#10;

// Test left shift (SISO with serial input from the left)
control = 3'b001;
serial_in_left = 1;
#10;

// Test right shift (SISO with serial input from the right)
control = 3'b010;
serial_in_right = 0;
#10;

// Test parallel-in, left-out (PISO)

control = 3'b101;
#10;

// Test parallel-in, right-out (PISO)

control = 3'b110;
#10;

// Complete simulation
$stop;
end

initial begin
$monitor("Time = %0t | Control = %b | Data_out = %b | Serial_in_left = %b | Serial_in_right
= %b | Parallel_in = %b",
$time, control, data_out, serial_in_left, serial_in_right, parallel_in);
end
endmodule