International Journal of Computer and Communication Engineering, Vol. 2, No.

6, November 2013

FPGA Implementation of 8-bit Multiplier with Reduced

Delay Time
Dhanabalan and Tamil Selvi

addition to generate carry. This increases delay time with

Abstract—This paper proposes a design method for an 8-bit increase in size of addition. Carry look-ahead adder is the
multiplication with reduced delay time. Normally, two numeric best adder when speed is given more importance.
data can be multiplied by repeated addition. In case of binary
multiplication, combinational circuit can be designed using
manual multiplication method which requires binary addition.
Carry generated because of addition affects the speed of II. ARRAY MULTIPLIER
multiplication since the present addition depends on the value
of previous carry. To overcome this problem, addition with the Based on performance comparison [5], [6], array
help of multiplexer is introduced and the result is an increased multiplier is selected for the purpose of evaluation. Fig. 1
speed in multiplication. Even though the proposed design is shows a 5X5 multiplication. In array multiplier,
mainly for FPGA implementation, it can also be implemented in multiplication is achieved in three steps. In the first step, each
ASIC as the logical delay is reduced when compared the result multiplicand bit is logically and with each multiplier bit. This
in Xilinx device.
logical AND operation can be done simultaneously. In the
Index Terms—Multiplexer, delay time, incrementer, FPGA.
second step, partial product in each row is shifted by its row
position minus one. In the third step, partial products are
added to get the end result. Now, this addition can be
I. INTRODUCTION performed depending on designer’s choice. Effective design
of adder circuit decides multiplier efficiency. A 5×5
Multiplication is generally used in almost all applications
multiplier requires, 20 AND gates, 15 shifters and 16 full
or designs like digital signal processing [1], image processing,
adders. It is also possible to perform multiplication with
embedded system, design of Arithmetic Logic Unit etc., [2].
repeated addition using a single adder circuit. Hardware
In this fast moving life, researchers are competing with the
requirement will be further increased if the designer chooses
speed of technology. When a typical algorithm is
carry look-ahead adder. However, pipeline method of
implemented in FPGA, it provides better execution speed
multiplication reduces delay time. Logical and in partial
than the one which is implemented in a DSP or any other
product is also responsible for increase in delay time. Delay
processor. It is because; processor utilizes its hardware
time logarithmically varies in proportion to the bit size of
architecture through sequential instructions. Whereas, FPGA
multiplicand and multiplier.
activates its hardware at the same time to do a job. Hence,
many of the applications are being replaced by FPGA
nowadays. VLSI technology is categorized into ASIC or
FPGA implementation. FPGA is chosen widely since it has
the flexibility of implementing different types of applications
in a single chip [3]. Type of an application can be changed by
writing HDL program into it.
Adder is the basic circuit that is needed to do
multiplication. Efficiency of multiplication automatically
improves when the efficiency of adder is increased. In case of
VLSI design, efficiency speaks in terms of area, speed &
power. Since there is a trade-off among these parameters,
only one of the parameter is considered for optimization and
the other two parameters shall be brought up to the
satisfactory level [4]. Delay time of multiplexer is reduced in Fig. 1. Array Multiplier Block diagram
this paper since many applications require high speed
operation. Delay time of adder circuit mainly depends on
processing carry generation when two bits are added. In III. MULTIPLIER DESIGN
ripple carry adder, the present addition waits for its previous Multiplication of two binary numbers involve logical and
OR operation. As in array multiplier, partial products are
Manuscript received December 28, 2012; revised July 5, 2013.
G. Dhanabalan is with the Kamaraj College of Engineering and obtained by logically and in each bit of multiplicand with
Technology, Virudhunagar, India (e-mail: [email protected]). each bit in multiplier [7]. After generating product terms,
S. Tamil Selvi is with National Engineering College, Kovilpatti, India addition is done using suitable adder circuit. Now, in this
(e-mail: [email protected]).
design the product terms are grouped together so that all the

DOI: 10.7763/IJCCE.2013.V2.270 665

 International Journal of Computer and Communication Engineering, Vol. 2, No. 6, November 2013

addition operations are done [8] simultaneously as shown in multiplexer is designed as a 4-bit adder. By having two 4 bit
Fig. 2(a). r1, r2, r3 & r4 are the resultant additions. These adders implemented into FPGA, 8-bit addition is done with
results are again grouped for addition to get x1 and x2 as lesser delay time as shown in Fig. 3.
shown in Fig. 2(b). The final result from Fig. 2(a) is x1, x2. Multiplexer design for four bit addition is derived from
truth table as shown in Table I.

TABLE I: 4-BIT ADDER - TRUTH TABLE

Fig. 2 (a) The final result is achieved after adding x1 and x2.

IV. DESIGN IMPLEMENTATION AND VERIFICATION

The design is written in verilogHDL program and verified
for correct output using ModelSim-Altera 6.6c simulation
Fig. 2 (b) software. Figure 4 shows simulated result for sample data
(0d×15, 8d ×55 & ff× ff). Using test bench, outputs for all the
possible combination of inputs are verified.

Fig. 2(c)
Fig. 2. (a), (b) & (c) Different stages of multiplication

Fig.4. Simulated output

Fig. 3. 8-bit addition using 4-bit adder
For implementing multiplier into hardware, we used
Because of parallel addition, this design requires seven Spartan 3E FPGA board [9]. Synthesize and comparison is
8-bit additions for 8 bit multiplication. done using the target device xc5vlx30-3-ff324. The Cell
usage is shown in Table II.
A. Adder Using Multiplexer
Addition is achieved in three stages. In the first stage, 8 bit TABLE II: CELL USAGE
data is divided into two 4 bit data and added simultaneously LUTs & IO Buffers In numbers
using two 4-bit adder. In the second stage, Sum from the LUT2 4
addition of a0-a3 & b0-b3 and carry from the addition of LUT3 13
a4-a7 & b4-b7 are added using 4 bit incrementer. Carry from LUT4 13
LUT5 41
incremented & carry from the addition of a4-a7 & b4-b7 are LUT6 62
logically ORed to get final carry in the third stage. MUXF7 10
Adder circuit using multiplexer is designed from the adder IBUF 16
truth table. For an 8-bit addition, truth table will have 65,536 OBUF 17
rows. In this design, we have segregated 8-bit addition into
two 4-bit addition and hence the truth table will have 256 To have comparison, multiplication is done using *
rows only. Six inputs are used as selector lines. Hence 64:1 symbol in program for the same target device. Cell usage for

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this design is shown in Table III.

TABLE III: CELL USAGE

LUTs/IO Buffers/Other Cells In numbers
DSP48E 1
IBUF 16
OBUF 17

The RTL & Technological schematic of proposed

multiplier is shown in Fig. 6, 7, 8 & 9.

Fig. 9. RTL Schematic of adder

V. EVALUATION OF THE PROPOSED DESIGN

Array multiplier performs better with reference to other
multipliers. Its delay time is 14.4ns. Delay time of proposed
multiplier when synthesized using Virtex5 FPGA is 12.294ns.
Hence the proposed design is able to execute multiplication
faster than array multiplier.
The proposed design is also compared with the
multiplier that is included as the standard cell by the vendor
[10] – [11]. It is shown in Table IV. Delay time in the
Fig. 5. Multiplier implemented in Spartan 3E board proposed design is higher than standard cell multiplier. Delay
time is the addition of logic delay and route delay. Now, logic
delay in proposed design is 1.525 ns less than standard cell
multiplier. If logic delay of proposed design and route delay
of standard cell multiplier is combined, then delay time
would be than 5.622ns.

TABLE IV: DELAY TIME - COMPARISON

Device Logic delay Route delay Delay time
Virtex 5 Proposed design 3.670ns 8.624ns 12.294ns
Virtex 5 Using DSP48E 5.195ns 0.427ns 5.622ns

Fig. 6. RTL Schematic of multiplier

VI. CONCLUSION
In this paper, we concentrated on how to increase the speed
of multiplication. Logic delay in this design is reduced.
Hence, the design can also be looked for ASIC
implementation. In case of FPGA implementation, route
delay is higher than the implementation using DSP48E.
Route delay can be reduced with the help of an efficient
algorithm. Defining a mechanism for routing algorithm in
FPGA may pave way for reduced route delay and hence delay
time.

Fig. 7. Technological schematic of multiplier REFERENCES

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[5] K. Mohammed and S. Agaian, “Efficient FPGA implementation of G. Dhanabalan received his B.E in instrumentation &
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IETE India.

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