AN ABSTRACT OF THE DISSERTATION OF

Siladitya Dey for the degree of Doctor of Philosophy in Electrical and Computer

Engineering presented on November 27, 2018.

Title: Design Techniques for Wide-bandwidth Continuous-time Delta-sigma

Modulators with Noise-shaping Quantizers

Abstract approved:

Kartikeya Mayaram Terri. S. Fiez

Noise-shaping multibit quantizers in a ΔΣ modulator oer extra orders of noise shap-

ing without increasing the loop-lter order and without compromising the stability

of the modulator. This dissertation presents two new architectures for improving the

overall performance of continuous-time ΔΣ modulators using noise-shaped quantiz-

ers.

The rst modulator architecture is motivated towards achieving high sampling fre-

quencies using a VCO quantizer. The VCO based quantizer provides the benets

of rst-order noise shaping, inherent DWA, and high sampling frequencies but suf-

fers from a highly nonlinear voltage-to-frequency transfer characteristic leading to

performance degradation. In this work, a dual-path VCO quantizer nonlinearity can-

cellation technique is proposed that improves the overall modulator performance by

cancelling the VCO quantizer non-linearity. The prototype modulator fabricated in

a 65 nm CMOS technology achieves 76.1 dB DR, 73.5 dB SNDR and 88 dB SFDR

over a 50 MHz signal bandwidth with an OSR of 15 and 51.8 mW of power.

nd
The second modulator architecture, on the other hand, achieves 2 order noise

shaping from the quantizer itself, thus, reducing the needed loop-lter order by two

and saving on active RC-OTA based integrator power. This new SAR-VCO based

hybrid quantizer solves the VCO quantizer nonlinearity issue and also provides sec-

ond order noise shaping. By using this SAR-VCO quantizer as an internal quantizer

nd th
in a 2 order ΔΣ loop, 4 order noise shaping is achieved using only two OTAs.

The pipeline operation of the SAR quantizer and the VCO quantizer makes the delay

of the hybrid quantizer equal to the delay of the SAR quantizer only. This reduces

the excess-loop-delay introduced by the quantizer when used in a ΔΣ loop. Also, the

quantization error leakage due to gain mismatch between the SAR path and the VCO

path in the quantizer is noise shaped. The prototype modulator fabricated in a 65

nm CMOS process achieves 83 dB DR, 80 dB SNDR and 84 dB SFDR for a 12 MHz

signal bandwidth with an OSR of 25 and 16.5 mW of power.

©Copyright by Siladitya Dey
November 27, 2018
All Rights Reserved
Design Techniques for Wide-bandwidth Continuous-time Delta-sigma
Modulators with Noise-shaping Quantizers
by

Siladitya Dey

A DISSERTATION

submitted to

Oregon State University

in partial fulllment of
the requirements for the
degree of

Doctor of Philosophy

Presented November 27, 2018

Commencement June 2019
Doctor of Philosophy dissertation of Siladitya Dey presented on November 27, 2018.

APPROVED:

Co-Major Professor, representing Electrical and Computer Engineering

Co-Major Professor, representing Electrical and Computer Engineering

Head of the School of Electrical Engineering and Computer Science

Dean of the Graduate School

I understand that my dissertation will become part of the permanent collection of

Oregon State University libraries. My signature below authorizes release of my
dissertation to any reader upon request.

Siladitya Dey, Author

 ACKNOWLEDGEMENTS

Fall in love with some activity, and do it! Nobody ever gures out what life is all

about, and it doesn't matter. Explore the world. Nearly everything is really inter-

esting if you go into it deeply enough. Work as hard and as much as you want to on

the things you like to do the best. Don't think about what you want to be, but what

you want to do. Richard P. Feynman

To me, this quote by Richard P. Feynman aptly describes the mindset for a fulll-

ing life, which is also very relevant to the context of a PhD student life. This journey

of mine as a PhD student have been with its highs and lows, and that's what has

made it interesting and worth pursuing. On the way, I have met many great people

who have inspired me and enriched my life in various ways. I would like to take this

opportunity to thank them.

First of all, I would like to thank Professor Terri Fiez and Professor Karti Ma-

yaram for giving me the opportunity to carry out research in the group and provide

the necessary fundings throughout my studies. Professor Fiez and Professor Mayaram

have always been supportive when we faced hurdles in research and provided neces-

sary encouragement to focus and nd solutions. I am immensely thankful to them

for their valuable feedback in research and in writing papers. I would also like to

thank my committee members, Professor Gabor Temes, Professor Arun Nataranjan

and Professor Sharmodeep Bhattacharyya for their supervision. My sincere appre-

ciation goes to Professor Un-Ku Moon for nominating me for the graduate Laurels

scholarship for the rst year of my studies at OSU. He has always been an inspiration
to us for his unparalleled knowledge combined with a great sense of humor. I would

like to thank my former advisor (during my M.Tech at IIT Madras, India) Professor

Nagendra Krishnapura for introducing me to analog & mixed signal IC design and

Dr. Sunil Rafeeque (Texas Instruments, India) for his support and encouragement

for higher studies.

During my PhD, I came across many fellow graduate students. Some of them

deserve special mention here. I would like to thank Kartikeyan Reddy for his contri-

bution and inuence on my PhD work. His directions and advice on various occasions

have helped me immensely during my research. Moreover, his PhD work did help me

set the ground for my research in analog-to-digital converter design. I would also

like to thank my friend Ankur Guha Roy, who has helped me in various occasions

during this time. I would like to thank my past and present group members: Hossein

Mirzaie, Hamidreza Maghami, Hui Zhang, Justin Goins, Raviteja Gajula, Kyle Gray

and Brian Miller. Also, I would like to thank students from other groups: Pedram

Payandehnia, Yanchao Wang, Tao He, Manjunath Kareppagoudr, Jason Muhlestein,

Spencer Leuenberger, Calvin Lee, Praveen K Venkatachala, Robin Garg, Sanket Jain,

Siddarth Mahendra, Soumya Bose, Narayana Bhagirath, Ajmal V Kayyil, Kamala R

Sadagopan, Mahmoud Sadollahi, Manoj Johnson and many others. It was great to

know you all. If I have not included someone in this list, it is unintentional. I also

have enjoyed interacting with many undergraduate students being the teaching assis-

tant for several courses taught by Professor Mayaram over the years. In this time, I

have met with many people outside the department who have enriched my life outside

research and help me grow as a person. Thank you all. I am specially thankful to
Sudeshna, Somdev and Sumit for being a great company.

Lastly, but foremost, I would like to express my deepest gratitude to my parents,

Basudev and Tapati. They are the unwavering support I always had by my side. My

dad have always motivated me to reach for higher goals in life being an inspiration

himself. I also would like to thank my younger brothers Siddhartha and Soumyadeep

and my sister Swatilekha. Love you all. Finally, I would like to extend my gratitude

to other members of my family, specially my dear grandma, who always have been

unconditionally loving and caring to me.

 TABLE OF CONTENTS
Page

1 Introduction 1

1.1 Scope of this work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Thesis orginazation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 A 50 MHz BW, 76.1 dB DR, Two-stage Continuous-time ΔΣ Modulator with

VCO Quantizer Nonlinearity Cancellation 4

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 MODULATOR ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 6

2.2.1 Sensitivity Analysis of the Two Stage Architecture . . . . . . . 11
2.2.2 MATLAB behavioral simulations . . . . . . . . . . . . . . . . 18
2.2.3 Comparison with a standalone fourth-order modulator . . . . . 20
2.2.4 The impact of STF2 on harmonic attenuation . . . . . . . . . 22
2.2.5 Improving harmonic attenuation by digital ltering . . . . . . 23
2.2.6 The eect of interstage gain . . . . . . . . . . . . . . . . . . . 26
2.2.7 Number of Quantizer levels . . . . . . . . . . . . . . . . . . . . 28
2.2.8 First stage power scaling . . . . . . . . . . . . . . . . . . . . . 31

2.3 CIRCUIT DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.3.1 Loop Filter Ampliers . . . . . . . . . . . . . . . . . . . . . . 35
2.3.2 VCO Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.3.3 Feedback DACs . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.4 MEASUREMENT RESULTS . . . . . . . . . . . . . . . . . . . . . . . 38

2.5 CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.6 APPENDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
nd
2.6.1 Justication for a 2 order NTF for the rst stage . . . . . . 50
2.6.2 Eect of Second Stage Input Delay Compensation . . . . . . . 53

th
3 A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4 order CT-ΔΣ modulator with a

nd
2 order noise-shaping and pipelined SAR-VCO based quantizer 56

3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.2 QUANTIZER AND MODULATOR ARCHITECTURE . . . . . . . . . 58

3.2.1 Hybrid SAR-VCO based quantizer architecture . . . . . . . . . 58
3.2.2 Sensitivity analysis of the SAR-VCO quantizer . . . . . . . . . 60
th
3.2.3 4 order CT-ΔΣ modulator architecture . . . . . . . . . . . . 63
 TABLE OF CONTENTS (Continued)
Page

3.2.4 Sensitivity analysis of the CT-ΔΣ modulator . . . . . . . . . 67

3.2.5 Pipeline operation with timing details . . . . . . . . . . . . . . 70

3.3 CIRCUIT DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.3.1 SAR-VCO Quantizer . . . . . . . . . . . . . . . . . . . . . . . 75
3.3.2 Feedback DACs . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.4 MEASUREMENT RESULTS . . . . . . . . . . . . . . . . . . . . . . . 77

3.5 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.6 APPENDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.6.1 Improving SNR by digital post-processing in presence of gain
errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4 Conclusions and future work 90

4.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Bibliography 93
 LIST OF FIGURES
Figure Page

1.1 Block diagram of a wireless receiver. . . . . . . . . . . . . . . . . . . 1

2.1 Block diagram of the proposed VCO-based two-stage CT ΔΣ modula-

tor architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Block diagram of a ΔΣ modulator with a VCOQ. . . . . . . . . . . . 8

2.3 (a) Block diagram of a VCOQ based ΔΣ modulator with VCOQ and
DAC errors. (b) Equivalent model for the modulator. . . . . . . . . 11

2.4 Block diagram of the proposed two stage modulator with VCOQ and
DAC errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5 Block diagram of the proposed two-stage modulator. . . . . . . . . . 16

2.6 Simulated PSD for a 4 MHz -3 dBFS input signal for (a) an open loop
VCO. Proposed two-stage modulator (b) rst stage output, (c) second
stage output, and (d) nal output of the proposed two-stage modulator. 17

2.7 SNDR vs DAC gain mismatches from the two-stage modulator MAT-
LAB model for a -3 dBFS 4 MHz input signal. . . . . . . . . . . . . . 19

2.8 Block diagram of the standalone fourth-order modulator. . . . . . . . 19

2.9 SNR/SNDR vs input amplitude plot for the proposed two-stage mod-
ulator and the standalone fourth-order modulator in Fig. 2.8 for a 4
MHz input signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.10 SNR/SNDR vs input frequency for the proposed two-stage modula-

tor and the standalone fourth-order modulator for a -3 dBFS input
amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.11 Maximum attenuation of harmonic component vs harmonic component

frequency for the proposed two-stage CT-ΔΣ modulator. . . . . . . . 22

2.12 Block diagram of the modulator with the digital post-processing lter
H(z). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.13 PSDs for a 10 MHz -3 dBFS input signal for the proposed two-stage
modulator (a) without digtal ltering, and (b) with digital ltering. . 25

2.14 Block diagram of the modulator with interstage gain G. . . . . . . . . 26

 LIST OF FIGURES (Continued)
Figure Page

2.15 (a) SNDR vs interstage gain. (b) Required number of VCOQ levels for
the second stage vs interstage gain. . . . . . . . . . . . . . . . . . . . 27

2.16 Block diagram of the (a) residue signal generation at the second stage
input, and (b) residue signal generation by subtracting a delayed signal
from itself. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.17 Signal component at the second stage input vs input frequency. . . . 29

2.18 Histogram of the output code for (a) the proposed two-stage modula-
tor, and (b) the standalone fourth-order modulator for a 50 MHz, 0
dBFS input signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.19 Simulated PSD of the proposed two-stage modulator at the rst stage
output, second stage output, and the nal output. . . . . . . . . . . . 32

2.20 Simulated PSD of the proposed two-stage modulator and the stan-
dalone fourth-order modulator. . . . . . . . . . . . . . . . . . . . . . 32

2.21 Schematic of the proposed architecture. . . . . . . . . . . . . . . . . . 33

2.22 Schematic of a two-stage feedforward compensated opamp. . . . . . . 35

2.23 VCO and summer amplier. . . . . . . . . . . . . . . . . . . . . . . . 37

2.24 (a) Schematic of a DRZ DAC current cell. (b) Timing waveforms for
the DAC switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.25 Photograph of the test-board, the package, and the die. . . . . . . . . 40

2.26 Block diagram of the test setup. . . . . . . . . . . . . . . . . . . . . . 41

2.27 (a) SNR/SNDR plot vs input amplitude. (b) Measured PSD for a 1
MHz -3 dBFS input signal. . . . . . . . . . . . . . . . . . . . . . . . . 42

2.28 Measured PSD for a 10 MHz -4 dBFS input signal at (a) rst stage
output, (b) second stage output, and (c) nal output. . . . . . . . . . 45

2.29 (a) Block diagram of the single stage standalone modulator. (b) Mea-
sured PSD for a 10 MHz -4 dBFS input signal for the proposed two-
stage modulator (in blue) and the single stage modulator (in red). . . 46
 LIST OF FIGURES (Continued)
Figure Page

2.30 Measured PSD with and without digital ltering for a 10 MHz (a) -4
dBFS input signal, and (b) 0 dBFS input signal. . . . . . . . . . . . . 47

2.31 (a) Measured SNDR vs DAC gain mismatches for a 1 MHz -3 dBFS
input signal. (b) Measured SNDR vs temperature for a 1 MHz -0.5
dBFS input signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2.32 Block diagram of a two-stage modulator with open loop VCOQ based
rst stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.33 SNR vs DAC gain mismatches for the proposed two-stage modulator
and the modulator in Fig. 2.32 for a -3 dBFS 4 MHz input signal. . 51

2.34 Magnitude of the signal transfer function and the noise transfer func-
tion for the rst stage of the modulator. . . . . . . . . . . . . . . . . 52

2.35 Block diagram of the proposed modulator with an input delay com-
pensation block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

2.36 Signal component at the second stage input vs input frequency with
and without input delay compensation. . . . . . . . . . . . . . . . . . 54

2.37 Simulated SNDR vs input frequency with and without input delay
compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.1 (a) Conceptual block diagram of the hybrid SAR-VCO based quantizer.
(b) Simulated PSDs of a 3-bit VCO quantizer and the proposed SAR-
VCO quantizer. (c) PSD of the NS-SAR stage. (d) PSD of the VCOQ
stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.2 (a) Error model of the quantizer. (b) SQNR vs α. (c) SQNR vs β. . 62

th
3.3 Conceptual block diagram of the 4 order CT ΔΣ modulator. . . . . 64

3.4 (a) Simulated PSD of the modulator output with thermal noise in-
cluded. (b) PSD of the NS-SAR stage. (c) PSD of the VCOQ stage. . 66

3.5 ΔΣ modulator SNR vs (a) NS-SAR feedback gain error, (b) VCO gain
error, and (c) VCO-DAC gain error. . . . . . . . . . . . . . . . . . . . 68
 LIST OF FIGURES (Continued)
Figure Page

3.6 Timing diagram for dierent blocks shows one clock period ELD (Steps
2 to 4) and the pipeline operation of the SAR-VCO quantizer. . . . . 70

3.7 Detailed schematic of the modulator with loop-lter implementation. 72

3.8 Schematics of (a) two-stage feedforward compensated OTA, and (b)

buer amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.9 Detailed schematic of (a) the NS-SAR, and (b) the VCOQ. . . . . . . 75

3.10 Test-board, package, and die micrograph. . . . . . . . . . . . . . . . . 78

3.11 Block diagram of the test setup. . . . . . . . . . . . . . . . . . . . . . 79

3.12 (a) Modulator power breakdown and measured SNR/SNDR plot vs the
input amplitude, and (b) measured 64k-point PSD for a 4 MHz input
signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.13 Measured STF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.14 (a) Measured SNDR/SNR vs temperature with digital gain optimized

0
for 50 C and (b) measured SNDR/SNR vs VCO-DAC (DRZ-DAC2)
gain mismatch before and after digital gain correction (Vin = -3.8
dBFS @ 1MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.15 Block diagram of the modulator with the digital post-processing lter
H(z). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.16 (a) PSDs with (blue) and without (red) digital calibration in the pres-
ence of gain errors. (b) SNR vs NS-SAR feedback gain error before
and after digital calibration. . . . . . . . . . . . . . . . . . . . . . . 89
 LIST OF TABLES
Table Page

2.1 Second stage ΔΣ modulator specications with looplter coecients. 16

2.2 PERFORMANCE COMPARISON . . . . . . . . . . . . . . . . . . . 43

3.1 Target specications with loop-lter coecients. . . . . . . . . . . . 63

3.2 PERFORMANCE SUMMARY AND COMPARISON. . . . . . . . . 85

 Chapter 1: Introduction

Increasing demand for a high signal bandwidth and dynamic range in modern wireless

receivers is one of the major driving forces behind the development of wide-bandwidth

analog-to-digital converters (ADC). The block diagram of a typical wireless receiver

is shown in Fig. 1.1. The three building blocks of the receiver are, an analog RF

front-end, an analog-to-digital converter and a digital baseband processor. The RF-

front end performs the amplication of the signal at the antenna input followed by

ltering and down-conversion to the baseband. The ADC converts the RF front-end

output to digital data bits for processing by the digital baseband processor. Digital

signal processing techniques are applied in the digital baseband processor to generate

the nal output from the wireless receiver. In advanced CMOS processes, the digital

baseband processor operates at a signicantly higher speed, along with a reduction in

area and power consumption. Thus it has been possible to implement more advanced

and complex signal processing algorithms in the digital baseband processor. This

Figure 1.1: Block diagram of a wireless receiver.

 2

has created a demand for wider bandwidth ADC implementations in these advanced

CMOS processes to improve the receiver throughput. Moreover, due to the limited

ltering characteristic of the RF front-end, large unwanted signals (blockers) could

be present at the ADC input. Therefore, a high dynamic range of more than 70 dB is

often necessary to detect a low amplitude desired signal mixed with a high amplitude

blocker signal. Thus, wide bandwidth and high dynamic range are important charac-

teristics of ADCs intended for high data-rate wireless receivers. Continuous-time ΔΣ

modulators are often an attractive choice for ADCs in such applications due to their

implicit anti-alias ltering, resistive input, high dynamic range and excellent power

eciency. However, to achieve a high dynamic range along with a wide bandwidth,

third or higher orders of noise-shaping along with multibit quantizers are necessary.

Noise shaping quantizers are relevant in this context. Noise shaping quantizers in a

ΔΣ modulator add extra orders of noise shaping without increasing the loop-lter

order and without compromising the stability of the modulator. Moreover, multibit

quantizers relax the loop lter linearity requirements which allows for a lower over-

sampling-ratio and relaxes the feedback DAC clock-jitter requirements compared to

a single bit quantizer.

1.1 Scope of this work

Various implementations of noise-shaping quantizers have been proposed [1, 2, 3].

Among them, VCO-based multibit quantizers [1] have gained signicant attention

due to their rst-order noise shaping, digital nature, inherent DWA, and high sam-
 3

pling frequencies. However, they suer from the highly nonlinear voltage-to-frequency

(V-to-F) transfer characteristic of a VCO quantizer (VCOQ) which leads to a degra-

dation in performance. In this work two new solutions have been presented. First,

a two-stage VCO quantizer nonlinearity cancellation technique is proposed that im-

proves the overall modulator performance by cancelling the VCOQ non-linearity. Here

the rst stage does not contribute to the noise shaping provided by the overall mod-

ulator but improves the linearity through harmonic cancellation. Even when highly

nonlinear VCOQs are used in both the stages, the two-stage modulator oers im-

proved linearity compared to a standalone single stage modulator with a VCOQ. The

nd
second modulator architecture presented here achieves 2 order noise shaping from

th
the quantizer itself, thus, a 4 order noise shaping is achieved using only two opamps.

The pipeline operation of the SAR and the VCOQ reduces the excess-loop-delay in

the ΔΣ loop which allows for high sampling frequencies.

1.2 Thesis orginazation

The rest of the thesis is organized as follows. In Chapter 2, a two-stage continuous-

time ΔΣ modulator architecture is presented that overcomes the VCO quantizer

nonlinearity issue. Chapter 3 presents a ΔΣ modulator with a 2nd order noise shaping
SAR-VCO based quantizer that overcomes the VCO quantizer nonlinearity issue and

th
achieves 4 order noise-shaping using a second-order loop lter. Chapter 4 concludes

the dissertation with a summary of this work and recommendations for future research

directions.
 4

Chapter 2: A 50 MHz BW, 76.1 dB DR, Two-stage Continuous-time

ΔΣ Modulator with VCO Quantizer Nonlinearity Cancellation

2.1 INTRODUCTION

In modern wireless standards such as LTE-Advanced, the required ADC bandwidth

due to carrier aggregation (CA) can be higher than 20 MHz. Also, due to the limited

ltering capability of the RF frontend, a high amplitude blocker signal can be present

at the ADC input. Therefore, high dynamic range (DR > 70 dB) and wide bandwidth

(BW > 20 MHz) ADCs are essential components in these receivers. Continuous-time

(CT) ΔΣ modulators [4, 5] provide implicit anti-alias ltering and excellent power

eciency while achieving more than 70 dB DR with tens of MHz of bandwidth [6, 7].

However, to achieve a high DR along with a high bandwidth, these modulators are

often designed with a third or higher order loop-lter along with multibit quantizers

and GHz sampling frequencies [8, 9, 10, 11, 12, 13]. Designing precise analog com-

parators at GHz sampling frequencies in deep sub-micron processes is a challenging

task. Moreover, mismatch shaping in a multibit feedback DAC requires explicit dy-

namic element matching (DEM) which introduces additional delay in the feedback

path and limits the maximum achievable sampling frequency.

With the development of time-based quantization techniques, VCO quantizers

(VCOQ) have become a popular choice for replacing conventional voltage-based multi-
 5

bit quantizers [1, 14, 8, 15, 16, 17, 10, 18, 19]. When used as a voltage-to-frequency

converter, VCOQs have the desirable properties of high sampling frequency, inher-

ent rst-order noise shaping and implicit DEM [1]. Despite the above advantages,

the highly nonlinear voltage-to-frequency (V-to-F) transfer characteristic of a VCOQ

leads to performance degradation. When the VCOQ is used in a ΔΣ modulator, this

nonlinearity degrades the distortion performance and limits the achievable SNDR [1].

In order to suppress the distortion, the order of the loop lter has to be increased

more than that required for meeting the quantization noise specication, leading to

a higher power consumption and stability issues. To overcome this nonlinearity is-

sue, the VCOQ has also been used as a voltage-to-phase converter [14, 8]. Although

voltage-to-phase conversion solves the VCOQ nonlinearity problem, it requires an ex-

plicit DEM which is one of the major power dissipating blocks at GHz range sampling

frequencies. Also, introducing a DEM in the feedback path increases the excess-loop-

delay (ELD) and degrades the stability of the modulator.

In this chapter, a two-stage continuous-time (CT) ΔΣ modulator with VCOQ is

presented. The proposed architecture [20] implements an overall fourth-order NTF

to achieve a high DR with a low oversampling ratio (OSR). This two stage archi-

tecture oers the benet of VCOQ nonlinearity cancellation [16] which improves the

SFDR when compared to a single stage fourth-order VCOQ based ΔΣ modulator

with frequency feedback. As an added advantage, this architecture exhibits robust

performance against DAC gain mismatches between the two stages. In this modula-

tor, the VCOQs are used with frequency feedback, thus, they benet from having an

implicit DEM. The implicit DEM enables implementation of the modulator with a
 6

Figure 2.1: Block diagram of the proposed VCO-based two-stage CT ΔΣ modulator

architecture.

multibit quantizer and reduced ELD to operate at GHz sampling frequencies. More-

over, the dual return-to-zero (DRZ) DAC [21, 8] makes the modulator immune to

data related inter-symbol interference (ISI) which often limits the performance in CT

ΔΣ modulators operating at GHz sampling frequencies.

The chapter is organized as follows. Section 2.2 details the modulator architecture,

VCO nonlinearity cancellation principle, sensitivity analysis highlighting the eect

of gain mismatch between the two stages and design choices for the two stages with

MATLAB simulations. Section 2.3 describes the circuit design details of the two-stage

CT ΔΣ modulator. Section 2.4 presents the measurement results of a prototype ADC

fabricated in a 65 nm CMOS process. Section 2.5 concludes the chapter.

2.2 MODULATOR ARCHITECTURE

In a ΔΣ modulator with VCOQ, the inability of the ΔΣ loop to completely suppress

the VCO nonlinearity is attributed to the large voltage swing at the VCOQ input.
 7

The two stage architecture shown in Fig. 2.1 provides a solution to reduce the impact

of a VCO's V-to-F nonlinearity. Here, the input is fed into the rst stage ΔΣ ADC1.
Since ΔΣ ADC1 processes the full scale input signal, the output of ΔΣ ADC1 consists
of shaped quantization noise and the harmonic components generated due to VCOQ

V-to-F nonlinearity. The output of the ΔΣ ADC1 is then subtracted from the input

using an inter-stage DAC to generate a residue voltage. This residue voltage consists

of the shaped quantization noise and the harmonic components generated by ΔΣ

ADC1, thus, the residue voltage is small in amplitude and random in nature as shown

in Fig. 2.1. Since the second stage ΔΣ ADC2 processes this residue signal, the second
stage VCOQ does not generate harmonic distortion. The nal output is the sum of

the outputs from both the stages. In this architecture, the quantization error and

VCOQ nonlinearity from the rst stage ΔΣ ADC1 is cancelled and the nal output

consists of the input signal and the shaped quantization error from the second stage

ΔΣ ADC2 as demonstrated by the following analysis. For this analysis, ΔΣ ADC1

and ΔΣ ADC2 are considered to be discrete time (DT) modulators with discrete time
representations of the loop transfer function L(z), signal transfer functions (STF) and

the noise transfer functions (NTF). By making this assumption, the anti alias ltering

property of a continuous time implementation is not taken into account. However,

the analysis demonstrates the inband properties of the proposed two-stage modulator.

The block diagram of a ΔΣ modulator with a VCOQ is shown in Fig. 2.2. Here, q
represents the VCOQ quantization noise and h represents the harmonic component

arising from the V-to-F nonlinearity of the VCOQ. The output Do of the modulator

is given by:
 8

Figure 2.2: Block diagram of a ΔΣ modulator with a VCOQ.

Do = Vin ST F + (q(1 − z −1 ) + h)N T F (2.1)

L(z) 1
where ST F = 1+L(z)
is the signal transfer function and NT F = 1+L(z)
is the noise

transfer function of the modulator. As expected, the quantization noise q gets an

extra order of noise shaping than the order of the NT F determined by L(z) as shown
by Eq. (2.1).

Similarly, for the proposed two-stage modulator as shown in Fig. 2.1 with VCOQs

in both the stages, the output Dout1 of the 1st stage is:

Dout1 = Vin ST F1 + (q1 (1 − z −1 ) + h)N T F1 (2.2)

where ST F1 and N T F1 are the rst stage signal transfer function and noise transfer

function, respectively, q1 represents the rst stage VCOQ quantization noise and h
represents the harmonic component arising from the V-to-F nonlinearity of the rst
 9

stage VCOQ. Also, the output of the second stage Dout2 is given by:

Dout2 = (Vin − Vin ST F1 )ST F2

−(q1 (1 − z −1 ) + h)N T F1 ST F2

+q2 (1 − z −1 )N T F2 (2.3)

where ST F2 and N T F2 are the second stage signal and noise transfer functions,

respectively, and q2 represents the second stage VCOQ quantization noise. Note that

the second stage VCOQ does not contribute to the generation of harmonic distortion.

The nal output is the sum of the two stages given by:

Dout = Vin (ST F1 + ST F2 − ST F1 ST F2 )

+(q1 (1 − z −1 ) + h)N T F1 (1 − ST F2 )

+q2 (1 − z −1 )N T F 2 (2.4)

From Eq. (2.4) we see that (q1 (1 − z −1 ) + h)N T F1 is scaled by a factor of (1 − ST F2 ).

By design, the in-band |1 − ST F2 | is small enough so that the eect of (q1 (1 − z −1 ) +
h)N T F1 (1 − ST F2 ) can be neglected. Therefore we can approximate 2.4 by:

Dout : Vin + q2 (1 − z −1 )N T F 2 (2.5)

From Eq. (2.5) it is observed that the nal output consists ideally of the input signal

and the quantization noise from the second stage shaped by (1 − z −1 )N T F 2 . Here
 10

the rst stage acts as a redundant stage and does not contribute to the noise shaping

provided by the overall modulator. The utility of the rst stage is to improve the

linearity of the overall modulator through harmonic cancellation. Even when highly

nonlinear VCOQs are used in both the stages, the two-stage modulator oers im-

proved linearity compared to the standalone second stage with a VCOQ. This is in

contrast to multistage ΔΣ modulator architectures like MASH [4] or Sturdy-MASH

(SMASH) [22] ΔΣ modulators. For a MASH ΔΣ modulator, the rst stage quantiza-
tion noise gets cancelled at the output and the second stage quantization noise gets

shaped by the product of the NTFs of the two stages. For a SMASH ΔΣ modulator,

the quantization noise from both the stages gets shaped by the product of the NTFs

of the two stages at the output. Thus MASH and SMASH architectures provide eec-

tive higher order noise shaping using low order individual stages. However, both the

MASH and the SMASH architectures rely upon the extraction of the quantization

error of the rst stage quantizer, which is not readily available for a VCOQ. The

proposed architecture on the other hand enables the use of a VCOQ in a high order

ΔΣ modulator (second stage) and solves the VCOQ nonlinearity problem by using a

redundant rst stage without adding extra order of quantization noise shaping. Next,

the eects of VCO's V-to-F gain variations and the eects of DAC gain variations on

the two-stage architecture are analyzed.

 11

Figure 2.3: (a) Block diagram of a VCOQ based ΔΣ modulator with VCOQ and
DAC errors. (b) Equivalent model for the modulator.

2.2.1 Sensitivity Analysis of the Two Stage Architecture

The block diagram of a ΔΣ modulator with VCOQ is shown again in Fig. 2.3(a).

Here αV is the VCOQ conversion gain and αD is the feedback DAC conversion gain.

Here, αV is equal to [15]:

2N KV CO
αV = (2.6)
Fs

where KV CO denotes the V-to-F gain of the VCO, N is the number of VCO phases,

and Fs is the sampling frequency. Because KV CO is very sensitive to process, voltage,

and temperature (PVT) variations, it is dicult to ensure a stable value of αV in

practice. Also, αD depends on the DAC bias current, which is also sensitive to PVT

variations. The output Do of the modulator is given by:

 12

Figure 2.4: Block diagram of the proposed two stage modulator with VCOQ and
DAC errors.

1 αD αV L(z) q(1 − z −1 ) + h
Do = Vin ( ) + (2.7)
αD 1 + αD αV L(z) 1 + αD αV L(z)

0 0
Do = Vin βD ST F + (q(1 − z −1 ) + h)N T F (2.8)

0 αD αV L(z) 0 1
where ST F = 1+αD αV L(z)
is the modied STF and NT F = 1+αD αV L(z)
is the modi-

1
ed NTF of the modulator. Also βD = αD
is the inverse of the feedback DAC gain.

In Eq. (2.7) the product αD αV should ideally be equal to unity. From Eq. (2.8) it is

0
observed that a variation in αD leads to a gain error in the ST F of the modulator.

Thus the ΔΣ modulator can be modelled as shown in Fig. 2.3(b) in the presense of

VCO and DAC gain errors.

Similarly, the proposed two-stage modulator can be modelled as shown in Fig.

1 1
2.4. Here βD1 = αD1
and βD2 = αD2
are the inverse of the feedback DAC gains for

ΔΣ ADC1 and ΔΣ ADC2, respectively. Also, αD is the inter-stage DAC gain. The

outputs from the rst stage, second stage, and the nal combined output are given

by Eqs. (2.9), 2.10, and 2.11, respectively:

0 0
Dout1 = Vin βD1 ST F1 + (q1 (1 − z −1 ) + h)N T F1 (2.9)
 13

0 0
Dout2 = (Vin − Vin βD1 αD ST F1 )βD2 ST F2
0 0
−(q1 (1 − z −1 ) + h)N T F1 αD βD2 ST F2
0
+q2 (1 − z −1 )N T F2 (2.10)

0 0
Dout = Vin βD1 ST F1 + q2 (1 − z −1 )N T F 2
0 0
+Vin βD2 ST F2 (1 − αD βD1 ST F1 )
0 0
+(q1 (1 − z −1 ) + h)N T F1 (1 − αD βD2 ST F2 ) (2.11)

0 0 0
where ST F1 and N T F1 are the ΔΣ ADC1 modied STF and NTF, and, ST F2 and

0
N T F2 are the ΔΣ ADC2 modied STF and NTF, respectively. Ideally, the product

0
αD βD2 ST F2 should be equal to 1. Under this condition, from Eq. (2.11), the rst

αD
stage quantization error q1 gets perfectly cancelled at the output. Since αD βD2 = αD2

is the ratio of the gains of the two DACs having the same reference current, this ratio

is unity in this architecture. Moreover, this ratio is insensitive to the variation in DAC

conversion gains due to PVT variations. Thus the proposed two stage architecture

shows robust performance across PVT variations and DAC gain variations. Eq. (2.11)

reduces to the following:

 14

0 0
Dout = Vin βD1 ST F1 + q2 (1 − z −1 )N T F 2
0 0
+Vin βD2 ST F2 (1 − αD βD1 ST F1 )
0 0
+(q1 (1 − z −1 ) + h)N T F1 (1 − ST F2 ) (2.12)

From Eq. (2.12), to achieve a fourth order noise shaping from the proposed two-

0
stage modulator, N T F2 needs to have a third order noise shaping. Thus the second

stage needs to have a third order loop lter and q2 gets fourth-order noise shaped.

0 0
Since, N T F2 = 1 − ST F2 , from Eq. (2.12), the rst stage quantization noise to the

0 0 0 0
nal output is given by q1 (1 − z −1 )N T F1 (1 − ST F2 ) = q1 (1 − z −1 )N T F1 N T F2 . q1
must have higher order noise shaping than q2 so that the inband quantization noise is

0
determined by q2 . Thus N T F1 needs to provide at least rst order noise shaping so

that q1 is overall fth order noise shaped. For this reason, a rst-order loop lter is

used for the rst stage. N T F1 and N T F2 for the two stages are given by Eq. (2.13)

0 0
and Eq. (2.14), respectively. Note that N T F1 = N T F1 and N T F2 = N T F2 when

αD1 αV 1 = 1 and αD2 αV 2 = 1, respectively.

N T F1 = 1 − z −1 (2.13)

(1 − z −1 )(1 − 1.969z −1 + z −2 )
N T F2 = (2.14)
(1 − 0.664z −1 )(1 − 1.674z −1 + 0.7705z −2 )

The proposed two stage architectute is shown in Fig. 2.5. The two stages of the
 15

modulator are described next.

2.2.1.1 Modulator First Stage

The rst stage of the two stage architecture is a ΔΣ modulator with a rst-order

0
loop lter and a 20 level VCOQ. Here, N T F1 provides rst-order noise shaping. A

0
rst-order N T F1 ensures that the rst stage quantization error has an extra order

of noise shaping compared to the noise shaping of the second stage quantization

error. Thus, the modulator becomes robust against performance degradation due to

the rst stage quantization error leakage to the output due to a gain mismatch in

the interstage DAC. This is validated in Section 2.2.2 through MATLAB behavioral

simulations. It is to be noted that an open loop VCOQ can also be used as the rst

stage. A two-stage modulator with an open loop VCOQ in the rst stage is discussed

in Appendix 2.6.1. The two-stage ΔΣ modulator with an open loop VCOQ based

rst stage exhibits higher variation of SQNR with DAC gain variations compared to

the proposed two-stage modulator. Moreover, by putting the VCOQ in a ΔΣ loop

in the rst stage, the rst stage signal transfer function is made independent of the

changes in KV CO due to PVT variations as shown in Eq. (2.8).

2.2.1.2 Modulator Second Stage

Since the second stage of the modulator denes the overall modulator performance,

a third-order loop lter has been selected for the second stage to achieve more than
 16

Figure 2.5: Block diagram of the proposed two-stage modulator.

Table 2.1: Second stage ΔΣ modulator specications with looplter coecients.

 17

Figure 2.6: Simulated PSD for a 4 MHz -3 dBFS input signal for (a) an open loop
VCO. Proposed two-stage modulator (b) rst stage output, (c) second stage output,
and (d) nal output of the proposed two-stage modulator.
 18

13 bit resolution with an OSR of 15 and a 20 level quantizer. This leads to an

SNR of 84 dB. The loop lter coecients of the second stage are calculated using an

impulse invariance transformation [23] and tabulated in Table I along with the target

specication for the second stage CT ΔΣ modulator.

2.2.2 MATLAB behavioral simulations

The power spectral density (PSD) of the open loop VCOQ from a MATLAB simu-

lation is shown in Fig. 2.6(a). The nonlinear coecients of the pesudo dierential

VCO are extracted from Cadence schematic level simulations and incorporated into

the MATLAB VCO model. The simulated PSDs of the rst stage output, second

stage output, and the nal combined output for the proposed two-stage modulator

are shown in Fig. 2.6(b), (c) and (d), respectively, for a 4 MHz -3 dBFS input tone.

The two stage modulator architecture has a 87.6 dB SFDR and a peak SNR/SNDR

of 81.8 dB/80.7 dB for a 50 MHz signal bandwidth. The third harmonic component

at the rst stage output Fig. 2.6(b) due to the VCOQ nonlinearity is suppressed

at the nal output Fig. 2.6(d) and improves the SFDR by 27.1 dB. Also, from Fig.

2.6(c) it is observed that the input signal gets attenuated by 35.5 dB at the input to

the second stage. This validates the assumption that the residue signal is small in

amplitude and random in nature. Thus the second stage does not contribute to the

generation of harmonic distortion. Next, the robustness of the modulator against the

gain mismatch between the two stages is analyzed. The SNDR variation with DAC

gain error for the proposed two stage modulator is shown in Fig. 2.7. The proposed
 19

Figure 2.7: SNDR vs DAC gain mismatches from the two-stage modulator MATLAB
model for a -3 dBFS 4 MHz input signal.

Figure 2.8: Block diagram of the standalone fourth-order modulator.

architecture shows 2.5 dB variation in SNDR for ±10% gain mismatch between the
two stages. In comparison, the two-stage architecture in [16] degrades the SNDR by

4.5 dB for the same variation in the DAC gain mismatch. Thus the proposed archi-

tecture with second-order and fourth-order NTF provides improved sensitivity to the

DAC gain mismatches over the rst-order and second-order NTF based architecture

in [16]. This is further validated through measurements in Section 2.4.

 20

Figure 2.9: SNR/SNDR vs input amplitude plot for the proposed two-stage modulator
and the standalone fourth-order modulator in Fig. 2.8 for a 4 MHz input signal.

2.2.3 Comparison with a standalone fourth-order modulator

The proposed two stage architecture and a standalone fourth-order modulator (second

stage is used as an independent modulator) as shown in Fig. 2.8 are compared

through MATLAB simulations. The SNR/SNDR vs the input amplitude for the two

modulators are shown in Fig. 2.9 for a 4 MHz input frequency. It is observed that

although the SNR and the DR of the two modulators are identical, the proposed two

stage architecture improves the peak SNDR by 6.2 dB. For a -3 dBFS input signal,

the SNDR is improved by 15 dB compared to the single stage modulator in Fig. 2.8.

The simulated SNR/SNDR with input frequencies in the range from 1 MHz to 16

MHz and -3 dBFS input amplitude is shown in Fig. 2.10 for the proposed two stage

modulator (in blue) and the standalone fourth-order modulator (in red). Since the

third-order harmonic distortion (HD3) is the dominant distortion component due to

 21

Figure 2.10: SNR/SNDR vs input frequency for the proposed two-stage modulator
and the standalone fourth-order modulator for a -3 dBFS input amplitude.
 22

Figure 2.11: Maximum attenuation of harmonic component vs harmonic component

frequency for the proposed two-stage CT-ΔΣ modulator.

pesudo-dierential VCOQs, the SNR/SNDR is shown for input frequencies upto 16

MHz so that the third harmonic falls inband (50 MHz bandwidth). It is observed

that the proposed two stage modulator has less variation in SNDR over the input

frequency range when compared to the standalone fourth-order modulator. Another

observation here is that the SNDR improves for input frequencies near 14 MHz for

both the modulators which is explained in the next subsection.

2.2.4 The impact of STF2 on harmonic attenuation

0 0
In Eq. (2.12), (q1 (1 − z −1 ) + h)N T F1 (1 − ST F2 ) represents the rst stage quantiza-

tion noise and harmonic components leakage to the nal output. Here, (q1 (1 − z −1 ) +
0
h)N T F1 , which represents the shaped quantization noise and harmonic components
 23

0 0
at the rst stage output, is scaled by a factor of (1 − ST F2 ). |1 − ST F2 | represents the
0
magnitude of (1 − ST F2 ) shown by the dotted line in Fig. 2.11. Also, MATLAB sim-

ulation results for maximum possible attenuation of the harmonic components from

the rst stage for the proposed twostage CT-ΔΣ modulator is shown by the solid

0
blue line across the bandwidth. As expected, with lower magnitude of (1 − ST F2 ),
the harmonic attenuation increases. The worst case attenuation of the harmonic com-

ponents by the second stage is 20 dB in the signal bandwidth. Also, the harmonic

cancellation improves for harmonic frequencies around 42 MHz. This explains the

improved SNDR for input frequencies near 14 MHz (third harmonic component at

42 MHz) as shown by the solid blue line in the Fig. 2.10 for the proposed two-stage

modulator.

2.2.5 Improving harmonic attenuation by digital ltering

For the proposed two-stage modulator, adding a digital lter before the nal addition

as shown in Fig. 2.12 will improve the harmonic cancellation. This is explained with

the help of 2.12. With the added digital lter at the output of the rst stage, Eq.

(2.12) gets modied as follows:

0 0
Dout = Vin βD1 ST F1 H + q2 (1 − z −1 )N T F 2
0 0
+Vin βD2 ST F2 (1 − αD βD1 ST F1 )
0 0
+(q1 (1 − z −1 ) + h)N T F1 (H − ST F2 ) (2.15)
 24

Figure 2.12: Block diagram of the modulator with the digital post-processing lter
H(z).

0 0 0
By selecting H = ST F2 , the term (q1 (1 − z −1 ) + h)N T F1 (H − ST F2 ) can be cancelled
out. Thus, the suppression of quantization noise and the harmonic components from

0
the rst stage is no longer limited by the attenuation provided by |1 − ST F2 | and the
0
cancellation is improved. Here, ST F2 is the signal transfer function of the DT-ΔΣ

modulator with third-order loop lter from which the loop lter coecients for the

equivalent CT-ΔΣ modulator is derived using an impulse invariance transformation.

0 0 0
Thus, H = ST F2 = 1 − N T F2 , where N T F2 is given by Eq. (2.14) when αD2 αV 2 = 1.
The MATLAB simulated PSDs with and without digital ltering block H(z) are

shown in Fig. 2.13. For a 10 MHz -3 dBFS input signal, without digital ltering (Fig.

2.13(a)), the third harmonic is attenuated by 24.8 dB. With the added digital lter

(Fig. 2.13(b)), the third harmonic is further attenuated by 18 dB. The improvement

in SNDR and SFDR by using digital post-processing is also shown from measured
 25

Figure 2.13: PSDs for a 10 MHz -3 dBFS input signal for the proposed two-stage
modulator (a) without digtal ltering, and (b) with digital ltering.
 26

Figure 2.14: Block diagram of the modulator with interstage gain G.

results in Section 2.4.

2.2.6 The eect of interstage gain

In this subsection, the eect of having an interstage gain G as shown in Fig. 2.14

on the performance of the proposed modulator is discussed. The SQNR/SNDR vs

the interstage gain for the proposed two stage modulator from MATLAB simulations

is plotted in Fig. 2.15(a) for a 4 MHz -3 dBFS input signal. With thermal noise

and the VCOQ nonlinearity disabled, the SQNR increases with interstage gain. With

thermal noise disabled and the VCOQ nonlinearity enabled, the SNDR saturates for

interstage gains more than 2. This is due to the third harmonic distortion limiting

the SQNR. With both the thermal noise and the VCOQ nonlinearity enabled, the

SNDR improves for an interstage gain of 2 and then saturates. The number of levels
 27

Figure 2.15: (a) SNDR vs interstage gain. (b) Required number of VCOQ levels for
the second stage vs interstage gain.
 28

Figure 2.16: Block diagram of the (a) residue signal generation at the second stage
input, and (b) residue signal generation by subtracting a delayed signal from itself.

needed for the second stage VCOQ for interstage gains values 1 to 5 is shown in Fig.

2.15(b) for a 50 MHz 0 dBFS input signal. The required number of levels needed for

the second stage quantizer increases linearly with interstage gain. When the second

stage is designed for higher interstage gain (say 2), the DR of the second stage will

reduce by 6 dB when the second stage is used as a standalone fourth-order modulator

with the same number of quantizer levels. Due to the reduced DR for the standalone

fourth-order modulator with higher interstage gains, the design choice was to keep

the interstage gain at unity.

2.2.7 Number of Quantizer levels

The block diagram of the residue signal generation at the second stage input is shown

in Fig. 2.16(a). The input to the second stage is the dierence between the direct

input signal and the delayed input signal through the rst stage and DACCONN . This
 29

Figure 2.17: Signal component at the second stage input vs input frequency.

delay is equal to one sampling clock Ts . Another residue signal generation is shown

in Fig. 2.16(b) by subtracting a delayed signal from itself. The power of the signal

0
component present at the input to the second stage ve is shown in red in Fig. 2.17

for dierent input frequencies. It is observed that the signal component at the input

to the second stage increases at a rate of 20 dB/dec. The blue line plots the signal

component in the residue signal ve where the residue signal is generated by subtracting
the signal from a delayed version of itself (the delay being equal to one clock period

Ts ). These two plots are in close agreement. From Fig. 2.17 it is observed that for the

highest frequency input signal the signal component present at the second stage input

is attenuated by 12 dB. Thus the number of quantizer levels needed for the second

stage is also less compared to the number of quantizer levels in the rst stage. From

Fig. 2.9 it is also observed that for an input signal amplitude less than 10 dBFS,

the standalone second stage provides high linearity. Thus for the proposed two stage

modulator, the input signal component present at the second stage input even for the
 30

Figure 2.18: Histogram of the output code for (a) the proposed two-stage modulator,
and (b) the standalone fourth-order modulator for a 50 MHz, 0 dBFS input signal.

highest input frequency is small enough not to generate harmonic tones. It is to be

noted that the input signal component at the input to the second stage can further

be reduced by using an input delay compensation network as in [24]. In [24] a high

interstage gain of 10 was used. Thus it was necessary to attenuate the input signal

component to avoid the saturation of the second stage quantizer. In this design,

since the interstage gain is unity, even without using an explicit delay compensation

network the amplitude of the signal component at the input to the second stage is

small enough (12 dB attenuated) not to saturate the second stage. Thus, no delay

compensation network is used in this design. The eect of having an explicit delay

compensation network in this design is discussed in Appendix 2.6.2.

Fig. 2.18(a) and (b) are the histograms of the output codes using 16k output

samples from the proposed two stage modulator and the standalone fourth-order

modulator, respectively. For a 0 dBFS 50 MHz input signal, the second stage uses
 31

only 11 levels of the quantizer. This observation is in aggreement with the attenuation

of the signal level observed from Fig. 2.17. When the second stage is used as a

standalone fourth-order modulator, all the 20 levels of the second stage quantizer are

used. Thus having a 20 level quantizer for the second stage enables the operation

of the second stage as a standalone fourth-order modulator with the same full scale

input signal range as that of the two-stage modulator. This is not optimum in terms

of overall modulator power and area but provides exibility during testing to measure

the second stage performance. If this feature is not needed, the number of levels for

the second stage VCOQ, DACSTG2A and DACSTG2B can be reduced (to 11 levels) to

optimize the second stage power without compromising the performance.

2.2.8 First stage power scaling

The two stages of the proposed modulator are designed for dierent thermal and the

icker noise requirements. The thermal noise, icker noise, and the shaped quanti-

zation noise and harmonic components from the rst stage are input to the second

stage and then cancelled at the nal output. Thus the thermal and icker noise re-

quirements from the rst stage can also be relaxed similar to the relaxed quantization

noise and linearity requirements. In this design, the input resistance of the second

stage determines the overall modulator thermal noise level and the value of this re-

sistor is kept low enough to meet the overall noise requirement. The rst stage input

resistance is scaled higher (4 times the second stage input resistance). Scaling the

input resistance of the rst stage helps to reduce the rst stage opamp power due
 32

Figure 2.19: Simulated PSD of the proposed two-stage modulator at the rst stage
output, second stage output, and the nal output.

Figure 2.20: Simulated PSD of the proposed two-stage modulator and the standalone
fourth-order modulator.
Figure 2.21: Schematic of the proposed architecture.
33
 34

to a reduced capacitive feedback load and the DACSTG1 current. The PSDs of the

outputs from each stage are overalyed in Fig. 2.19 to get a better visibility of the

rst stage thermal noise cancellation eect. The PSDs in Fig. 2.19 indicate that the

thermal noise along with the quantization noise from the rst stage gets cancelled at

the nal output. In Fig. 2.19, the rst stage SNR is 67.8 dB due to higher thermal

and quantization noise levels and the nal output SNR improves to 81.8 dB after

cancellation. The standalone second stage PSD is plotted along with the proposed

two stage modulator PSD in Fig. 2.20. The inband quantization and thermal noise

oor is the same for both cases. This veries that for the proposed modulator the

SNR is determined by the second stage SNR, thus, the rst stage is optimized for

power with relaxed thermal noise and linearity requirements.

2.3 CIRCUIT DETAILS

The schematic diagram of the two-stage CT ΔΣ modulator is shown in Fig. 2.21.

The rst stage consists of a rst-order loop lter followed by a VCO and frequency

encoder. DACSTG1 is the feedback DAC for the rst stage. The third-order loop lter

of the second stage is implemented as a hybrid of feedforward and feedback paths. The

second stage loop lter is also followed by a VCO and frequency encoder. DACSTG2A is

the main feedback DAC and DACSTG2B is the ELD compensation DAC for the second

stage. DACCONN is the inter-stage DAC which subtracts the output of the rst stage

from the input to generate the residue. Both the loop lters are implemented using

two-stage feedforward compensated opamp based active-RC integrators for linearity

 35

Figure 2.22: Schematic of a two-stage feedforward compensated opamp.

requirements [25]. The RC time-constants can be tuned by the 4 bit capacitor banks.

Both stages are designed with half a clock cycle ELD. The VCOQs in both the stages

are clocked with the rising edge of the clock and all the DACs are clocked with the

falling edge of the clock. Next, the key building blocks of the modulator are described.

2.3.1 Loop Filter Ampliers

The ampliers in the integrator have a two-stage feedforward compensated architec-

ture as shown in Fig. 2.22. Feed-forward compensation conserves the gain bandwidth
 36

product of the opamp and minimizes the ELD caused by the integrator. A telescopic

cascode amplier is used in the rst stage, and the second stage is implemented with

a common source amplier. Two separate common-mode feedback circuits are used

to set the output common-mode voltages of both the stages independently. The rst

stage uses a self-biased common-mode feedback and the second stage uses a common-

mode feedback amplier to set the common-mode voltages. AC coupling capacitors

are used to implement the feed-forward path from the input to the second stage. The

ampliers consume 4 mA of current and achieve 60 dB DC gain with a 4 GHz unity

gain bandwidth.

2.3.2 VCO Quantizer

The quantizers in both the stages use a pseudo-dierential VCO architecture, each

consisting of two VCOs. Each of these VCOs is a 10-delay stage ring oscillator. A

single delay cell is a cross coupled inverter as shown in Fig. 2.23. The supply rails

of the VCO are controlled by the adder dierential output VP and VN . I0 provides

dc oset voltages for VP and VN which are set to 250 mV above the common mode

voltage. Additionally, the VCO's nominal current IVCO is provided at VP and VN . The

output of the VCO's phase is quantized using sense amplier ip-ops. The quantized

phase is then fed to a frequency encoder. The positive and negative outputs from a

pseudo dierential quantizer are then subtracted in the current domain at the DAC

outputs.
 37

Figure 2.23: VCO and summer amplier.

 38

2.3.3 Feedback DACs

In this design, DACCONN , which subtracts the rst stage output from the input to

generate the residue is the most critical DAC in terms of static and dynamic errors.

The output of the VCOQ is barrel shifted, which shapes the static mismatches in the

DAC current elements. To reduce sensitivity to dynamic errors caused by clock jitter

and data dependent ISI, DACCONN uses DRZ DACs to create a non-return-to-zero

(NRZ) pulse shape [8, 21]. A single current element of DACCONN is shown in Fig.

2.24(a) and the timing waveforms for the switches are shown in Fig. 2.24(b). Here,

DIN is the input data for the DAC. Depending upon DIN being 0 or 1, the switches

are controlled according to Dp1 , Dp2 , Dn1 and Dn2 to generate the DRZ current pulse

shape. For simplicity, the control signals for the switches connected to the common-

mode voltage are not shown. They turn on when the other two switches connected

to the same current source are o.

The rst stage feedback DACSTG1 error gets cancelled at the nal output. Also,

the second stage feedback DACSTG2A processes the quantization error from the rst

stage, which is random in nature. Thus, the linearity requirements of DACSTG1 and

DACSTG2A are less stringent and standard NRZ DACs are used.

2.4 MEASUREMENT RESULTS

The prototype ADC was fabricated in TSMC 65 nm GP CMOS process and

 39

Figure 2.24: (a) Schematic of a DRZ DAC current cell. (b) Timing waveforms for
the DAC switches.
Figure 2.25: Photograph of the test-board, the package, and the die.
40
 41

Figure 2.26: Block diagram of the test setup.

 42

Figure 2.27: (a) SNR/SNDR plot vs input amplitude. (b) Measured PSD for a 1
MHz -3 dBFS input signal.
Table 2.2: PERFORMANCE COMPARISON
43
 44

assembled in a 60-pin QFN package. It occupies an active area of 0.35mm2 . The

test-board, package and die micrograph are shown in Fig. 2.25. A four-layer PCB

was used to characterize the chip. The test setup is shown in Fig. 2.26. A passive

band-pass lter (Allen Avionics F4526-10P0) was used to eliminate distortion from

the input signal source. The sinusoid was then converted into a dierential signal

using a balun (Minicircuits-ADT1-6T). The modulator output, which was brought

out of the chip at full rate was captured using a logic analyzer (Tektronix TLA7012).

The modulator was clocked by a clock source generated from an arbitrary waveform

generator (Tektronix AWG7122B). This clock was also used by the logic analyzer to

synchronously capture the output data.

Clocked at 1.5 GHz, the ADC consumes 51.8 mW. The power breakdown is 25.3

mW for opamps, 13.5 mW for DACs, 7.8 mW for VCOQs, 2 mW for clock generation

and 3.2 mW for digital buers. The measured SNR and SNDR are plotted as a

function of the input amplitude as shown in Fig. 2.27(a) and the output PSD with a

1 MHz -3 dBFS input signal is shown in Fig. 2.27(b). For a -3 dBFS, 1 MHz input

signal, the ADC achieves 88 dB SFDR and peak SNR/SNDR of 76.1 dB/73.5 dB

for a 50 MHz signal bandwidth. The resulting Walden and Schreier FoMs are 134

fJ/conv-step and 166 dB, respectively. The performance of the ADC is summarized

in Table II. The measured output waveform and the PSD of the rst stage output,

second stage output, and the nal combined output are shown in Fig. 2.28(a), (b)

and (c), respectively, for a 10 MHz -4 dBFS input tone. The ADC achieves 77.7 dB

SFDR and peak SNR/SNDR of 76.1 dB/69.1 dB for a 50 MHz signal bandwidth. The

third harmonic component at the rst stage output Fig. 2.28(a) due to the VCOQ
45
 46

Figure 2.29: (a) Block diagram of the single stage standalone modulator. (b) Mea-
sured PSD for a 10 MHz -4 dBFS input signal for the proposed two-stage modulator
(in blue) and the single stage modulator (in red).

nonlinearity is suppressed at the nal output Fig. 2.28(c) and improves the SFDR

by 21.2 dB. The architectural benets of the proposed two-stage CT ΔΣ modulator

are demonstrated by comparing it with a single stage modulator. The single stage

modulator is formed by switching o the DACCONN and using the second stage as a

standalone modulator as shown in Fig. 2.29(a). The measured PSD of the two-stage

modulator (in blue) and the single stage modulator (in red) are shown in Fig. 2.29(b)

for a 10 MHz -4 dBFS input signal. As expected, both the modulators have the

same SNR and the proposed two-stage architecture improves the linearity by 17.9 dB

compared to the single stage VCOQ based modulator with frequency feedback. The

measured SNR is 76.1 dB for the standalone second stage and 81 dB from MATLAB

system level simulations. Increased clock jitter due to the ringing of the internal

supplies and ground nodes is most likely a cause for the degradation of the noise
 47

Figure 2.30: Measured PSD with and without digital ltering for a 10 MHz (a) -4
dBFS input signal, and (b) 0 dBFS input signal.
 48

Figure 2.31: (a) Measured SNDR vs DAC gain mismatches for a 1 MHz -3 dBFS input
signal. (b) Measured SNDR vs temperature for a 1 MHz -0.5 dBFS input signal.
 49

oor.

The measured PSDs with and without digital backend ltering for a 10 MHz input

signal are shown in Fig. 2.30(a) and (b) for -4 dBFS and 0 dBFS input amplitudes,

respectively. With added digital ltering, the third harmonic component is attenuated

and the SNDR is no longer limited by the third harmonic from the VCOQ nonlinearity.

The SNDR improves from 65.4 dB to 72.4 dB for the 10 MHz 0 dBFS input signal. The

peak SNDR improves from 69.1 dB (for -4 dBFS input amplitude) without ltering

to 72.4 dB (for 0 dBFS input amplitude) with ltering.

The robustness of the modulator against the gain mismatch between the two

stages is validated through measurement by varying the DAC gains by ±10% and
measuring the SNDR for a 1 MHz -3 dBFS input signal in Fig. 2.31(a). Less than

1.5 dB variation of SNDR is observed for ±10% gain mismatch between the two

stages. Although the SNDR variation is 2.5 dB from MATLAB simulations, the

increased noise oor from the second stage overshadows the eect of the DAC gain

mismatch. Thus, the measured variation of SNDR with the DAC gain mismatch

appears to be less than that observed in simulation. The sturdiness of the modulator

with temperature variation over 00 C − 800 C is shown in Fig. 2.31(b). Less than 1 dB

variation of SNDR is observed over the temperature range. Table II also compares

this design with state-of-the-art CT ΔΣ modulators having similar bandwidth and

resolution. The proposed modulator achieves the highest SNR among the reported

VCO based ΔΣ ADCs. Also, compared to [16], the proposed modulator oers higher

DR and improved robustness against DAC gain mismatches.

 50

2.5 CONCLUSIONS

The proposed two-stage CT ΔΣ modulator with VCOQs and implicit DEM provides

the benets of high sampling frequency and wide bandwidth and improves linearity

through VCOQ nonlinearity cancellation. This architecture with a second-order NTF

for the rst stage and a fourth-order NTF for the second stage exhibits strong immu-

nity to the rst stage quantization error leakage to the output due to gain mismatches

between the two stages and temperature variations. Furthermore, a dual-RZ DAC

makes the modulator robust against DAC dynamic errors due to clock-jitter and data

dependent ISI. The prototype modulator fabricated in a 65 nm CMOS technology

achieves 73.5 dB SNDR and 88 dB SFDR over the 50 MHz bandwidth. Finally, the

measured SNDR variation remains within 1.5 dB for ±10% gain mismatch between
the two stages and a temperature variation of 00 C − 800 C .

2.6 APPENDIX

2.6.1 Justication for a 2nd order NTF for the rst stage

Another variant of the two stage architecture is shown in Fig. 2.32 in which an open

loop VCOQ is used for the rst stage. Here, the rst stage provides a rst-order

NTF. SNR variations with DAC gain errors are shown in Fig. 2.33 for the proposed

two-stage modulator and the modulator shown in Fig. 2.32. For the architecture in

Fig 2.32, higher in-band quantization noise from the rst stage results in an overall

modulator SNR below 80 dB. Also, the proposed two stage modulator shows 2.5 dB
 51

Figure 2.32: Block diagram of a two-stage modulator with open loop VCOQ based
rst stage.

Figure 2.33: SNR vs DAC gain mismatches for the proposed two-stage modulator
and the modulator in Fig. 2.32 for a -3 dBFS 4 MHz input signal.
 52

Figure 2.34: Magnitude of the signal transfer function and the noise transfer function
for the rst stage of the modulator.

variation in SNR for ±15% gain errors between the two stages. In comparison, an

open loop VCOQ based two stage modulator degrades the SNR by 9 dB for the same

variation in the DAC gain errors. This indicates that the proposed architecture is less

sensitive to the DAC gain errors compared to the two-stage modulator architecture

variant shown in Fig. 2.32.

The magnitudes of the signal transfer function and the noise transfer function for

the rst stage of the modulator are shown in the Fig. 2.34. The rst stage quantization

error has a second order noise shaping. The STF1 for the inband frequencies is almost

at with a 0.4 dB peaking at the band edge. Since no excess loop delay compensation

is used for this stage, the STF1 peaks at higher frequencies. This can be problematic in

the presence of out-of-band signals and needs to be addressed by appropriate ltering

prior to the modulator.

 53

Figure 2.35: Block diagram of the proposed modulator with an input delay compen-
sation block.

2.6.2 Eect of Second Stage Input Delay Compensation

An input delay compensation network with a delay of one sampling period Ts is added
to the residue generation network as shown in Fig. 2.35 and simulated in MATLAB.

The power of the signal component present at the input to the second stage with and

without the delay is plotted in Fig. 2.36 for dierent input frequencies and a 0 dBFS

input amplitude. With an added delay of Ts to the direct signal path to match the

combined delay of the rst stage and DACCONN , the signal component in the residue

signal is reduced as shown by the plot in the dotted line. For both cases, the signal

component increases at a rate of 20 dB/dec. Next, the eectiveness of the delay

compensation network to improve the ovearall modulator SNDR is evaluated. The

SNDR as a function of the input frequency is shown in Fig. 2.37 with and without

the input delay compensation. As expected, the SNDR of the proposed two stage
 54

Figure 2.36: Signal component at the second stage input vs input frequency with and
without input delay compensation.

Figure 2.37: Simulated SNDR vs input frequency with and without input delay com-
pensation.
 55

modulator with and without the delay compensation are in agreement. This is due

to the fact that even without the delay compensation network, the signal component

present at the second stage input is small enough not to generate any harmonic

components and only a limited number of quantizer levels are used for a full scale

input signal. In conclusion, even though adding a delay to the direct input path to

the second stage decreases the signal component at the second stage input, it does not

aect the SNDR or DR of the modulator. Thus in this design no delay compensation

network was added which also helped to reduce the modulator design complexity.
 56

Chapter 3: A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4th order CT-ΔΣ

modulator with a 2nd order noise-shaping and pipelined SAR-VCO
based quantizer

3.1 INTRODUCTION

Noise shaping quantizers in a single-loop ΔΣ modulator oer one [1, 15] or two

[26, 27] extra orders of noise shaping without increasing the loop-lter order and

without compromising the stability of the modulator. VCO-based quantizers (VCOQ)

provide rst-order noise shaping, inherent DWA, and fast sampling but are highly non-

linear [1]. The ash-VCO based residue cancelling quantizer in [15] solves the non-

linearity issue by coarse quantizing the input using a ash quantizer and then using

the VCOQ as a ne quantizer to provide rst-order noise shaping. Here, an additional

DAC is used to extract the coarse quantization error. The delay of this quantizer is

equal to the added delay of the ash quantizer, the DAC, and the VCO quantizer.

Quantization error in a SAR quantizer on the other hand, is naturally generated as a

residue voltage at the end of the SAR conversion cycle without additional circuitry.

This residue voltage is used to implement noise shaping by the noise coupling [28, 29]

technique in [2, 26]. Alternatively, this residue voltage from the SAR quantizer is used

as the input to a second stage VCOQ in a SAR-VCO based ADC in [30] to overcome

the VCO non linearity issue and provide 1st order noise shaping. The combination of
 57

SAR and VCO quantizers presents an attractive opportunity for higher order noise

shaping.

This work introduces a new SAR-VCO based hybrid quantizer which solves the

VCO nonlinearity issue and provides second order noise shaping. In this hybrid

quantizer, the SAR and the VCOQ operate in pipeline. The pipeline operation oers

two advantages. First, due to the pipeline operation, the delay of the hybrid quantizer

is equal to the delay of the SAR quantizer only. Thus, the additional VCO path in

the quantizer adds one extra order of noise shaping without aecting the throughput

of the hybrid quantizer. Secondly, the pipeline operation ensures that the VCO does

not need to be stopped between conversions, thus, a simple ring oscillator is used

instead of a gated ring oscillator [27]. Moreover, the quantization error leakage due

the gain mismatch between the SAR path and the VCO path in the quantizer arising

from the VCO gain variations across PVT is noise shaped. By using this SAR-VCO

nd th
quantizer as an internal quantizer in a 2 order ΔΣ loop, 4 order noise shaping is

achieved using only two OTAs. Thanks to the inherent DWA nature of the VCOQ

output bits, the VCOQ feedback DAC static errors get shaped without an explicit

DEM block. The prototype modulator fabricated in a 65 nm CMOS process achieves

84 dB SFDR, 83 dB DR and peak SNR/SNDR of 82.26/80 dB for a 12 MHz signal

bandwidth and OSR of 25 with FOMW of 84.12 fJ/conv-step and FOMS-SNDR of 168.6

dB. Measured SNR remains the same across a temperature range of 200 C − 800 C and

indicates the robust performance of the ΔΣ modulator against quantization error

leakage to the output due to the VCO gain variation. The chapter is organized as

follows. Section 3.2 details the hybrid SAR-VCO based quantizer architecture, the
 58

CT-ΔΣ modulator architecture, the eects of gain mismatch between the two stages

of the quantizer and the pipeline operation. Section 3.3 describes the circuit design

details of the modulator. Section 3.4 presents the measurement results of a prototype

modulator. Section 3.5 concludes the chapter.

3.2 QUANTIZER AND MODULATOR ARCHITECTURE

3.2.1 Hybrid SAR-VCO based quantizer architecture

The proposed hybrid quantizer, shown in Fig. 3.1(a), consists of an asynchronous

SAR quantizer as a course quantizer followed by VCOQ as a ne quantizer. The

quantization error q1 from the coarse SAR is naturally generated at the end of the

SAR conversion as a residual voltage on the SAR capacitor bank. This error is fed

back to the SAR input to implement noise shaping in the SAR quantizer (NS-SAR).
 59

Figure 3.1: (a) Conceptual block diagram of the hybrid SAR-VCO based quantizer.

(b) Simulated PSDs of a 3-bit VCO quantizer and the proposed SAR-VCO quantizer.

(c) PSD of the NS-SAR stage. (d) PSD of the VCOQ stage.

The output of the NS-SAR is given by D1 .

D1 = VIN Q + q1 (1 − z −1 ) (3.1)

Additionally, q1 is ne quantized by VCOQ and is followed by a (1 − z −1 ) lter.

 60

The inter-stage gain is G. The VCOQ output is given by D2 where q2 represents the

VCOQ quantization noise.

q2
D2 = q1 z −1 (1 − z −1 ) + (1 − z −1 )2 (3.2)
G

The hybrid quantizer output is given by D0 .

q2
D0 = VIN Q + (q1 − )(1 − z −1 )2 (3.3)
G

Here, the rst stage quantization noise q1 and the attenuated second stage quantiza-

q2
tion noise are second-order noise shaped at the quantizer output. The open loop
G

VCOQ output PSD and the proposed SAR-VCO quantizer PSD are shown in red

and blue in Fig. 3.1(b). Compared to the standalone VCOQ, the hybrid quantizer

oers high linearity and second order noise shaping. In this design G=2 and a 3-bit

VCOQ ensures that the overall SQNR is dominated by q1 . The PSDs of the NS-SAR

and the VCOQ outputs are shown in Fig. 3.1(c) and (d), respectively. They exhibit

st
1 order noise shaping as indicated by Eqs. (3.1) and (3.2).

In the next section, the eects of circuit non-idealities on the performance of the

SAR-VCO quantizer is discussed.

3.2.2 Sensitivity analysis of the SAR-VCO quantizer

An error model of the SAR-VCO quantizer that includes the gain errors of the SAR

feedback and the VCO gain is shown in Fig. 3.2(a). The feedback gain of the SAR is
 61

denoted by α and the VCO gain is denoted by β. Using this model, the outputs D1 ,
D2 and D0 are given by:

D1 = VIN Q + q1 (1 − αz −1 ) (3.4)

q2
D2 = βq 1 z −1 (1 − z −1 ) + (1 − z −1 )2 (3.5)
G

p −1 2 q2 p
D0 = VIN Q + q1 (1 − βz ) − (1 − z −1 )2 + q1 (2 β − α − β)z −1 (3.6)
G

Ideally, the SAR feedback gain α and the VCOQ conversion gain β must be equal to
q2
unity. Under this condition, q1 and
G
are second order noise shaped at the quantizer
√
output and the leakage term q1 (2 β −α−β)z −1 in Eq. (3.6) goes to zero. When α6=1,
the quantization error q1 leaks to the output and degrades the quantizer performance.

The SQNR vs gain error in α and β is shown in Figs. 3.2(b) and (c), respectively.
 62

Figure 3.2: (a) Error model of the quantizer. (b) SQNR vs α. (c) SQNR vs β.

In reality, because the VCO gain KVCO is very sensitive to PVT variations, varia-

tions of β from its nominal value lead to the gain errors between the two paths. The

SAR feedback gain α is implemented as a capacitive ratio and does not change across
PVT. Considering α=1, the output D0 is given by:

q2
D0 = VIN Q + q1 (1 − z −1 )(1 − βz −1 ) − (1 − z −1 )2 (3.7)
G
 63

which shows that in the presence of VCO gain variations, q1 is noise shaped by the

factor (1 − z −1 )(1 − βz −1 ). Fig. 3.2(c) shows that the SQNR varies by 4.5 dB for a

±15% variation in K VCO .

3.2.3 4th order CT-ΔΣ modulator architecture

To achieve more than second-order noise-shaping, the SAR-VCO quantizer is used as

an internal quantizer in a ΔΣ modulator as shown in Fig. 3.3. The target specica-

tions and the loop-lter coecients are shown in Table 3.1.

Table 3.1: Target specications with loop-lter coecients.

Loop-lter order = 2 Loop-lter Coecients
Noise-shaping order= 4 K0 = 1.6
OSR = 25 K1 = 2.082
SAR Quantizer = 4 bits K2 = 0.996
VCOQ = 3 bits
Interstage gain (G) = 2
 th
Figure 3.3: Conceptual block diagram of the 4 order CT ΔΣ modulator.
64
 65

The output of the ΔΣ modulator is given by DOU T , where STF is the signal

nd
transfer function and NTF is the noise transfer function of the 2 order loop-lter.

q2
DOU T = VIN ST F + (q1 − )(1 − z −1 )2 N T F (3.8)
G

q2
Thus, (q1 − G
) is fourth-order noise shaped as shown in Fig. 3.4(a). The VCOQ
output D2 is given by:

q2
D2 = q1 z −1 (1 − z −1 ) + (1 − z −1 )2 (3.9)
G

and the NS-SAR quantizer output D1 is given by D1 = DOU T + D2

q2 q2
D1 = VIN ST F + q1 z −1 (1 − z −1 ) + (1 − z −1 )2 + (q1 − )(1 − z −1 )2 N T F (3.10)
G G

The PSDs of D1 and D2 are shown in Figs. 3.4(c) and (d), respectively. They

nd
show 2 order noise shaping as per Eqs. (3.9) and (3.10).
 66

Figure 3.4: (a) Simulated PSD of the modulator output with thermal noise included.

(b) PSD of the NS-SAR stage. (c) PSD of the VCOQ stage.
 67

3.2.4 Sensitivity analysis of the CT-ΔΣ modulator

From Eq. (3.6), the modulator output in presence of gain errors is given by:

p −1 2 q2 p
DOU T = VIN ST F +q1 (1− βz ) N T F − (1−z −1 )2 N T F +q1 (2 β−α−β)z −1 N T F
G
(3.11)

The variations of SNR with α and β are shown in Figs. 3.5(a) and (b), respectively.
Figure 3.5: ΔΣ modulator SNR vs (a) NS-SAR feedback gain error, (b) VCO gain error, and (c) VCO-DAC
gain error.
68
 69

From Fig. 3.5(a), the SNR degradation is less than 0.5 dB for a ±5% variation in α
which can easily be ensured with a switched capacitor implementation. Furthermore,

the degradation in SNR due to the variation in α can be corrected by digital ltering

the output as shown in Appendix 3.6.1.

Considering α=1, the output DOU T is given by:

q2
DOU T = VIN ST F + q1 (1 − z −1 )(1 − βz −1 )N T F − (1 − z −1 )2 N T F (3.12)
G

which shows that in the presence of a VCO gain variation, q1 is noise shaped by

the factor (1 − z −1 )(1 − βz −1 )N T F . As expected, Fig. 3.5(b) shows that the SNR

remains the same for a ±15% variation in KVCO . Thus, the modulator exhibits

robust performance with VCO gain variations across PVT. The performance of the

modulator is veried across temperature in Section 3.4.

Finally, when used in a ΔΣ loop, there could be a gain error in the SAR-DAC

(DRZ-DAC1 ) and VCO-DAC (DRZ-DAC2 ). Ideally, the ratio of the VCO-DAC gain

1
and the SAR-DAC gain is equal to the digital recombination gain of . In the presence
G
γ
of a gain error γ in the VCO-DAC gain, the ratio of the DAC gains become
G
. The

SNR vs gain error is shown in Fig. 3.5(c) in blue. This is corrected by scaling the

1 γ
digital recombination gain from to and the SNR vs gain error is shown in red.
G G

This is also veried through measurements in Section 3.4.

 70

3.2.5 Pipeline operation with timing details

Figure 3.6: Timing diagram for dierent blocks shows one clock period ELD (Steps

2 to 4) and the pipeline operation of the SAR-VCO quantizer.

The pipeline operation of the hybrid quantizer is shown in Fig. 3.6 with the help of

the modulator timing diagram. Here, the SAR and the VCOQ operate in parallel

th
with the SAR converting the n quantizer input and the VCOQ converting the (n-

th
1) SAR residue to generate DOUT as elaborated next. CLKIN is the master clock

at twice the sampling frequency from which other clocks are generated. The SAR

tracking phase starts at the rising-edge of CLKQ (Step 1) and samples the quantizer
 71

input at the falling edge of CLKQ (Step 2). 0.75Ts is allocated for the SAR conversion

(TSAR ). At the end of the SAR conversion, CLKQA goes high (Step 3) and latches the

th
n SAR conversion output D1 . At the same instant, the VCOQ nishes converting

th
the (n-1) SAR residue and the output D2 is latched. Φi and Φq are two phases which
alternate every VCOQ sampling period to sample and hold the previous SAR residue

for conversion using two sets of residue holding capacitors (CATT in Fig. 3.9(a)). Note

that CLKQA precedes CLKQ by ∆T to ensure that the CATT capacitors are switched

before the next rising-edge of CLKQ , avoiding corruption of the residual charge on

CATT . Finally, the feedback DRZ DACs are clocked at the rising-edge of CLKD (Step

4) with D1 and D2 data bits. 0.25Ts is allocated for the binary-to-thermometer (B-to-

T) conversion and the DWA delay combined (TB-to-T +TDWA ). The ELD (delay from

Steps 2 to 4) is equal to one sampling period (TSAR +TB-to-T +TDWA =TS ). Therefore,

the addition of the VCOQ path in the quantizer increases the noise shaping order

without aecting the ELD and does not limit the maximum sampling frequency of

the modulator. Moreover, the VCOQ operates in a continuous mode and does not

need to be gated.
 3.3 CIRCUIT DETAILS

Figure 3.7: Detailed schematic of the modulator with loop-lter implementation.

72
 73

The schematic of the modulator is shown in the Fig. 3.7. The second-order loop lter

is implemented with two RC-OTA based integrators. The OTAs have a two-stage

nd
feedforward compensated architecture as shown in Fig. 3.8(a). The 2 OTA also

performs the summing operation for the feed-forward path, the SAR residue feedback,

and the excess loop delay (ELD) compensation. The buer amplier of gain 4, shown

in Fig 3.8(b), is followed by VCOQ with an STF of 0.5z −1 . This makes the eective

STF of the VCOQ path equal to 2z −1 . Thus, a digital recombination gain of

1
G
= 0.5
is used while combining D1 and D2 .
Figure 3.8: Schematics of (a) two-stage feedforward compensated OTA, and (b) buer amplier.
74
 75

3.3.1 SAR-VCO Quantizer

Figure 3.9: Detailed schematic of (a) the NS-SAR, and (b) the VCOQ.
 76

The NS-SAR shown in Fig. 3.9(a) is a 4-bit asynchronous SAR with two sets of atten-

uation capacitors (CATT ) which work in a ping-pong fashion [26]. In one conversion,

one set of CATT is connected to the SAR capacitor array during SAR sampling and

conversion phases, while the other set is used to hold the residual charge from the pre-

vious SAR conversion at the buer amplier input. In the next conversion cycle, their

roles alternate. The pseudo dierential VCOQ processes the residue voltage using the

positive and negative half circuits as shown in Fig. 3.9(b). Each half circuit consists

of a 4-stage current starved ring oscillator followed by a phase quantizer (SA-FF) and

st
1 order digital dierentiator. A delayed version of the digital dierentiator is also

generated. Control bits DKVCO <2:0> tune the VCO if needed for PVT variations.

3.3.2 Feedback DACs

Dual Return-to-Zero (DRZ) DACs [8, 21, 31] are used to eliminate the DAC ISI error

and for lower jitter sensitivity characteristics of a NRZ DAC. The (1 − z −1 ) operation
after the VCOQ is implemented by subtracting the delayed VCOQ output samples in

the current domain inside DRZ DAC2 . In the feedback path, the SAR binary output

bits are converted to thermometer code and then passed through a DWA block for

DAC static mismatch error shaping. The VCOQ feedback path does not require an

explicit DEM block due to the inherent DWA nature of its output bits. Note that

1
the digital gain should match the ratio of the DRZ-DAC2 and DRZ-DAC1 gains.
G

This is ensured by foreground digital gain calibration. By generating both the DAC

currents from the same reference, the DAC gains will track across PVT and the ratio
 77

will remain the same.

3.4 MEASUREMENT RESULTS

The prototype ADC was fabricated in a 65 nm CMOS process. Fig. 3.10 shows

the test-board, package and the die photo of the modulator which occupies an active

2
area of 0.22 mm . The test setup is shown in Fig. 3.11. Clocked at 0.6 GHz, the

ADC consumes 16.5 mW power. The power breakdown is shown in Fig. 3.12(a)

with the measured SNR and SNDR versus the input amplitude. The output PSD

is shown in Fig. 3.12(c). For a -1 dBFS, 4 MHz input signal, the ADC achieves

84 dB SFDR, 83 dB DR and peak SNR/SNDR of 82.26/80 dB for a 12 MHz signal

bandwidth. The resulting Walden and Schreier FOMs are 84.12 fJ/conv-step and

168.6 dB, respectively. The modulator with SAR-VCO based quantizer achieves an

th
80 dB/decade slope of the noise shaping, indicating an overall 4 order noise shaping

nd
attained with a 2 order loop lter.
Figure 3.10: Test-board, package, and die micrograph.
78
Figure 3.11: Block diagram of the test setup.
79
 80

Figure 3.12: (a) Modulator power breakdown and measured SNR/SNDR plot vs the

input amplitude, and (b) measured 64k-point PSD for a 4 MHz input signal.

The measured STF is shown in Fig. 3.13. The STF peaking is 4.5 dB around 50

MHz. The measured SNR versus temperature shown in Fig. 3.14(a) demonstrates the

robustness of the modulator across a temperature range of 200 C − 800 C . The digital

gain was calibrated at 500 C and kept constant for other temperature measurements.
 81

The measured variation of the SNR/SNDR with DRZ-DAC2 gain variations is shown

in Fig. 3.14(b). A 3 dB variation in SNDR is observed for a ±10% DAC gain variation,
1
which is corrected by changing the digital gain by the same percentage.
G
Figure 3.13: Measured STF.
82
Figure 3.14: (a) Measured SNDR/SNR vs temperature with digital gain optimized for 500 C and (b) mea-
83

sured SNDR/SNR vs VCO-DAC (DRZ-DAC2) gain mismatch before and after digital gain correction (Vin

= -3.8 dBFS @ 1MHz).

 84

Table 3.2 compares this design with CT ΔΣ modulators having a similar DR and

bandwidths of 10 MHz and higher. The proposed modulator achieves state-of-the-art

nd
DR and SNDR using the 2 order noise shaping quantizer.
Table 3.2: PERFORMANCE SUMMARY AND COMPARISON.
85
 86

3.5 CONCLUSION
nd
In this work, a new SAR-VCO based hybrid quantizer is introduced that provides 2

order noise shaping. The residue voltage from the SAR quantizer is naturally gener-

ated at the end of the SAR conversion cycle without using extra hardware. Moreover,

the input to the VCOQ stage is this quantization noise, thus VCOQ does not generate

harmonic distortion. Additionally, the SAR and VCOQ work in a pipeline fashion,

thus, the maximum sampling frequency is determined by the SAR quantizer conver-

nd
sion time only. By using this SAR-VCO quantizer as an internal quantizer in a 2

th
order ΔΣ loop, 4 order noise shaping is achieved using only two OTAs. The proto-

type modulator achieves 83 dB DR and 80 dB SNDR in a 12 MHz signal bandwidth

and exhibits robust performance against quantization error leakage to the output due

to VCO gain variations across a temperature range of 200 C to 800 C .

3.6 APPENDIX

3.6.1 Improving SNR by digital post-processing in presence of gain er-

rors

In the presence of quantizer gain erros as discussed in Section 3.2.4, Eq. (3.11) can

be re-written as,

q2
DOU T = VIN ST F + q1 (1 − (α + β)z −1 + βz −2 )N T F − (1 − z −1 )2 N T F (3.13)
G
 87

The output of the VCOQ before the digital lter (1 − z −1 ) is given by:

q2
DV COQ = βq1 z −1 + (1 − z −1 ) (3.14)
G

Using a digital lter H(z), as shown in Fig. 3.15, with a transfer function given by:

(1 − (α + β)z −1 + βz −2 )N T F
H(z) = (3.15)
βz −1

0
the nal output DOU T is given by:

0
D OU T = DOU T − H(z)DV COQ (3.16)

0 q2 q2 (1 − (α + β)z −1 + βz −2 )N T F
DOU T = VIN ST F − (1 − z −1 )2 N T F − (1 − z −1 )2
G G βz −1
(3.17)

0 th q2
Thus, the nal output DOU T consists of the 4 and higher order noise shaped
G
terms

and the q1 term is cancelled. The PSD without and with digital ltering is shown

in Fig. 3.16(a) with α=1.15, β=0.85 and γ = 1. The simulated SNR in presence of

the analog gain errors is improved from 84.3 dB to 87.3 dB. The variation of SNR

with α is shown in Fig. 3.16(b) in blue. The SNR degradation is 2.5 dB for a ±15%
variation in α. This degradation in SNR due to the variation in α is corrected in the

digital domain and is shown in red. Thus, in the presence of analog gain errors in the

quantizer, the SNR is improved through digital post-processing to remove the eect

of quantization error leakage as shown here.

Figure 3.15: Block diagram of the modulator with the digital post-processing lter H(z).
88
 89

Figure 3.16: (a) PSDs with (blue) and without (red) digital calibration in the presence

of gain errors. (b) SNR vs NS-SAR feedback gain error before and after digital

calibration.
 90

Chapter 4: Conclusions and future work

4.1 Conclusions

Wide-bandwidth continuous-time delta-sigma modulators are an active area of re-

search recently due to the high demand for wireless transceivers. The digital nature

of VCO based quantizers benets from technology scaling and presents an attractive

alternative to conventional ash based quantizers in wide-bandwidth ΔΣ modula-

tors. This work has explored design techniques for wide-bandwidth continuous-time

delta-sigma modulators with noise-shaping quantizers.

In Chapter 2, a two-stage continuous-time ΔΣ modulator with a VCO quantizer

was presented. The presented modulator suppresses the VCO quantizer voltage-

to-frequency nonlinearity through dual path cancellation to achieve high linearity.

This architecture preserves the desirable properties of a VCO quantizer such as a

high sampling frequency, rst-order noise shaping, and implicit DEM. It also exhibits

strong immunity to the rst stage quantization error leakage to the output due to

gain mismatches between the two stages and temperature variations. The prototype

modulator fabricated in a 65 nm CMOS technology achieves 73.5 dB SNDR and 88

dB SFDR over the 50 MHz bandwidth with an OSR of 15. Finally, the measured

SNDR variation remains within 1.5 dB for ±10% gain mismatch between the two
stages and a temperature variation of 00 C − 800 C .
 91

nd
In Chapter 3, a new 2 order noise shaping, SAR-VCO based hybrid quantizer

is introduced. The quantization error of the SAR quantizer is the input to the VCO

quantizer, thus the VCO quantizer does not generate harmonic distortion and the

hybrid quantizer exhibits high linearity. Additionally, the SAR and VCOQ operate

in a pipeline fashion and the maximum sampling frequency of the hybrid quantizer

is determined by the SAR quantizer conversion time only. By using this SAR-VCO

nd th
quantizer as an internal quantizer in a 2 order ΔΣ loop, 4 order noise shaping

is achieved using only two opamps. The ΔΣ modulator exhibits robust performance

in the presence of gain mismatch between the SAR path and the VCO path in the

quantizer due to VCO gain KVCO variations across PVT. The prototype modulator

fabricated in a 65 nm CMOS process achieves 84 dB SFDR, 83 dB DR and 80 dB

SNDR for a 12 MHz signal bandwidth with an OSR of 25. Measured SNR remains the

same across a temperature range of 200 C − 800 C . This indicates robust performance

of the ΔΣ modulator against quantization error leakage to the output due to the

VCO gain variations.

4.2 Future work

The non-linearity cancelling architecture presented in Chapter 2 could be used to

extend the signal bandwidth beyond 50 MHz at smaller technology nodes. The DRZ-

DAC used in this design limits the maximum sampling frequency of the modulator,

thus, new methods for the DAC dynamic error calibration [32, 33] need to be explored

for future designs. For the SAR-VCO based quantizer presented in Chapter 3, the
 92

nd rd
noise shaping order of the SAR-VCO quantizer could be increased from 2 to 3 order

by increasing the SAR noise-coupling order to 2

nd
order [26] and using a (1 − z −1 )2
digital lter at the VCO quantizer output. This opens up an opportunity for power

ecient higher-order SAR-VCO based quantizer architectures. Moreover, the pipeline

operation ensures that the delay of overall quantizer is equal to the delay of the SAR

quantizer only. A higher operating speed in advanced technology nodes will lead

to a higher speed of operation for the SAR. Thus, multi-GHz sampling frequencies

with multi-order noise shaping could be achieved with the SAR-VCO based quantizer

architecture in advanced technology nodes.

 93

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