This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2014.2304561, IEEE Transactions on Power Electronics

Survey on Fault-Tolerant Techniques for Power

Electronic Converters
Wenping Zhang, Student Member, IEEE, Dehong Xu, Fellow, IEEE, Prasad N. Enjeti, Fellow, IEEE, Haijin Li,
Student Member, IEEE, Joshua T. Hawke, Student Member, IEEE, and Harish S. Krishnamoorthy, Student Member

Abstract—With wide-spread application of power electronic In critical applications, such as military, financial markets and
converters in high power systems, there has been a growing hospitals, system interruptions could lead to immeasurable
interest in system reliability analysis and fault-tolerant economic losses [5], [7]. Therefore, discussion of fault-
capabilities. This paper presents a comprehensive review of tolerant power systems and enhanced system reliability
conventional fault-tolerant techniques regarding power
electronic converters in case of power semiconductor device
attracts much attention among researchers.
failures. These techniques can be classified into four categories References [8]-[9] define some metrics to evaluate power
based on the type of hardware redundancy unit: switch-level, leg- electronic system reliability, such as failure rate, mean time
level, module-level and system-level. Also, various fault-tolerant between failures (MTBF), mean time to repair (MTTR), and
methods are assessed according to cost, complexity, performance, availability. Since a precise mathematical model is helpful
etc. The intent of this review is to provide a detailed picture when verifying whether a fault-tolerant design meets expected
regarding the current landscape of research in power electronic requirements, empirical-based model and physics-of-failure
fault-handling mechanisms. model are employed while designing components of power
Index Terms—Fault-tolerance, power electronic converters, electronics systems [10]. With regard to system-level
system reliability, post-fault operation. configurations, the markov model is widely adopted [11].
For a fault-tolerant system, the fault diagnosis is the first
step once a fault occurs [12]. An accurate and timely detection
I. INTRODUCTION and protection can prevent fault propagations and catastrophic
consequences. The fault-tolerant operation, consisting of fault-
ower electronic converters—featuring higher efficiency
P and higher power density—play an increasingly important
role in adjustable-speed drives, utility interface of renewable
isolation and fault-reconfiguration is the next counter-measure,
which is always based on hardware redundancy design and
corresponding fault-tolerant control. As for fault-tolerant
energy resources, flexible high-voltage direct current (HVDC) operations, numerous solutions are reported by past literatures.
transmission systems, and electric or hybrid electric vehicles Based on the type of the hardware redundancy, these methods
(HEVs) [1]-[3]. However, field experiences have are classified into four categories: 1) switch-level, 2) leg-level,
demonstrated that electrolytic capacitors and power switching 3) module-level and 4) system-level. For the first solution,
devices in power electronics converters, such as insulated gate various fault-tolerant methods, such as inherently redundant
bipolar transistors (IGBTs) and metal-oxide field-effect switching states [18]-[32], DC-bus midpoint connection [33]-
transistors (MOSFETs), are the most vulnerable components, [57] and redundant parallel or series switches installation [58]-
which challenge the reliability of the system [4]-[5]. Since [63], are investigated extensively. In leg-level solutions, the
most of the power electronic converters do not exhibit main approach is to add redundant legs in parallel or series
redundancy, any fault that occurs to components or connection to main legs [64]-[74]. Among them, the redundant
subsystems will result in interruption of the operation. In parallel leg solution achieves a better compromise between the
certain applications related to personal safety, such as electric system cost and performance, thus becoming a hot area of
drives for vehicles, this unexpected system shutdown will fault-tolerant research. Cascade multilevel converters (CMCs)
place passengers into areas of potential risks [6]. and modular multilevel converters (MMCs) are typical
This work is supported by the National High Technology Research and topologies with module-level redundancy. Three scenarios
Development Program of China 863 Program (2012AA053601, including neutral-shift, DC-bus voltage reconfiguration and
2012AA053602, and 2012AA053603), the National Natural Science redundant modules installation are employed [75]-[88]. In
Foundation of China (51277163), the Specialized Research Fund for the
Doctoral Program of Higher Education of China (20120101130010), and industry fields, the parallel redundancy converter approach is
Zhejiang Key Science and Technology Innovation Group Program widely employed due to higher reliability. Among the above
(2010R50021). approaches, some system performances during post-fault are
W. Zhang, D. Xu and H. Li are with the Institute of Power Electronics, degraded. Therefore, these methods can only be applied in
College of Electrical Engineering, Zhejiang University, Hangzhou 310027,
China. (e-mail: [email protected]) fields where a “limp-home” function is allowable after faults.
P. Enjeti, J. Hawke and H. Krishnamoorthy are with Department of Additionally, it is necessary to explore more practical
Electrical & Computer Engineering, Texas A&M University, Hangzhou modified topologies endowed with a full redundant capability,
College Station, Texas, 77840, USA. (e-mail: [email protected])
Digital Object Identifier

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and therefore can potentially be applied within the industry in Section III. Section IV summarizes switch-level hardware
the future. reconfigurations. Leg-level and module-level for hardware
Due to the growing importance and extensive research reconfigurations are presented in Section V and Section VI,
surrounding the fault tolerance of power converters, the respectively. Section VII introduces system-level solutions.
authors feel that this is the right time to put forth a systematic The concluding remarks and discussion are summarized in
perspective on the status of the fault-tolerant research. Section VIII.
Altogether, this paper presents a comprehensive overview of
the fault-tolerant techniques in the case of power II. GENERAL CLASSIFICATION
semiconductor failures. Section II introduces general The prevailing fault-tolerant methods for power electronics
classification of conventional fault-tolerant techniques and the converters are presented in Fig.1, which are categorized into
relevant assessment criteria. Several existing methods for the switch-level, leg-level, module-level and system-level.
hardware fault-isolation are presented and compared in
Fault-Tolerant Methods for Power Electronics Converters

Switch-Level Leg-Level Module-Level System-Level

Redundant DC-Bus Midpoint Redundant Series Redundant Series Dc-Bus Voltage Redundant Series Redundant Series or
Neutral-Shift
Switching States Connection or Parallel Switch or Parallel Leg Regulation or Parallel Module Parallel Converter

Fig. 1. State-of-the-art fault-tolerant methodology chart

Most of multilevel converters are considered switch-level extra modules in series with other modules. The redundant
redundant circuits, since some switches are added compared to module substitutes the damaged one, maintaining the original
basic 2-level converters. Consequently, an inherent outputs [87]-[88]. Similarly, the redundant module can be
redundancy that multiple switching combinations of three- designed for online- or offline-mode based on applications.
phase correspond to the same three-phase outputs is formed. More costly techniques, such as using an extra converter
Therefore, the fault-tolerance can be realized by exploring reserved for system fault-reconfigurations have been
these inherently redundant switching states [18]-[32]. The employed in industrial applications. Two common topologies
second solution for the switch-level reconfiguration is to are the cascaded redundant converter and the parallel
connect the faulty converter to the midpoint of the DC-bus via redundant converter [89]-[95]. The additional converter can be
additional auxiliary switches [33]-[57]. The two-phase control operated in either cold or hot backup mode.
are normally applied in the remaining two phases to maintain In order to assess the above techniques, the comparison
balanced outputs during post-fault operations. Another criteria used in this paper are presented as follows.
scenario comes from the use of redundant switches in parallel 1) Cost. The cost will increase if extra fuses or devices are
or series connection to main switches [58]-[63]. Based on added for system fault-tolerance. Furthermore, semiconductor
whether or not the redundant switch is operated in normal devices in some basic topologies may need to be overdesigned
conditions, two schemes are developed: online strategy and for fault-tolerant operation, which increases costs as well.
offline strategy. 2) Output performance. The output capability should be
As for leg-level scenarios, a powerful solution currently in evaluated first. Also, other factors, such as the total harmonic
use is to apply extra legs in parallel with main legs. Since the distortion (THD) of output voltages or currents, system
redundant leg can substitute the damaged leg, the normal efficiency, and dynamic response should be taken into
behavior of the converter can be guaranteed after faults [64]- consideration as well. A topology with full fault-tolerance
[70]. Alternately, the redundant legs can be in series should behave after faults identically to normal operations.
connection to the main legs for fault reconfigurations [71]- 3) Reliability. How many types of faults are covered and
[74]. Similar to switch-level solutions, the redundant leg can how much reliability is enhanced are also important metrics
be designed for online mode or offline mode based on used to evaluate overall performance of fault-tolerant topology.
different applications.
Module-level solutions are primarily for CMCs or MMCs. III. FAULT ISOLATION TECHNIQUES
The first strategy is neutral-shift method. After faults, the For most of fault-tolerant solutions, the physical fault-
number of the operative modules in each phase is unequal; the isolation is the first step, especially in the case of short-circuit
phase shifts among three phase-voltage references is adjusted fault. The fault-isolation unit forces damaged switches or
to maintain balanced line-to-line voltages [75]-[82]. Another poles to be electrically isolated from the system first which
technique is the DC-bus voltage configuration method, which can eliminate its influence over the system behavior. Then the
attempts to sustain an unchanged output voltage by raising the post-fault reconfiguration can be activated. The following
input voltage. The increased voltage can be normally shared requirements should be taken into consideration for the design:
by three phases via combining the neutral-shift scenario [83]- 1) Rapidity. 2) Fault coverage. 3) Precision. The excellent
[86]. A more powerful solution currently in use is to apply isolation scheme should only isolate damaged components,

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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while leaving all the healthy switches operational. 4) Impact IV. FAULT-RECONFIGURATIONS: SWITCH-LEVEL
on the normal operation of the system. 5) Complexity and cost. After the fault-isolation, fault reconfiguration is activated.
Fig. 2 shows five typical isolation schemes. Although these This process relies on hardware redundancy design and
schemes are based on two-level circuits, the concept can be corresponding fault-tolerant control. This section introduces
generally applied to other topologies as well. three types of switch-level hardware redundancies and
Strategy 1 is shown in Fig. 2(a) [13]. This method can associated control strategies.
disconnect either a single switch or entire phase-leg from the
system. For instance, S2 isolation is implemented by triggering A. Redundant Switching States
the semiconductor-controlled rectifier (SCR) T1 which creates
a shoot-through loop across the DC-bus and blows the fuse F2. Multilevel converters are in essence one type of switch-
Note that the size of auxiliary capacitors is critical to the level redundant circuits, where some switches are added into
duration of the fault-isolation process. The main disadvantages basic 2-level converters. Due to these additional switches, the
of this strategy are as follows. 1) The presence of the fuses in redundancy of output switching states is created. Therefore,
the DC-bus side will increase the parasitic inductance. 2) The the fault-tolerance can be realized by exploring these
component count is relatively high, increasing the system cost. redundant switching states. Note that the method is normally
C1 F1 F1
implemented based on the space-vector modulation (SVM)
F1
T1 S1 S1 S1
algorithm [18]-[19].
S1 S1
T1
F1 Li et al. proposed a control scheme of utilizing the voltage
R1
TN vector redundancy for neutral-point clamped (NPC) inverters
S2 S2 S2
T2 S2 S2 [20]. Assuming that Sa1 fails in short-circuit, phase-A cannot
C2 F2 F2 F2 output zero-level due to the shoot-though path as shown in Fig.
(a) (b) (c) (d) (e) 3(a). As a result, the voltage vectors involving zero-level of
Fig. 2. Five typical fault-isolation schemes (a) Strategy1 (b) Strategy 2 (c) phase-A are invalid as shown in Fig. 3(b). The converter is
Strategy 3 (d) Strategy 4 (e) Strategy 5
still able to output a full voltage with the help of redundant
Strategy 2—a simplified version of Strategy 1—has only vectors. However, the other issues are introduced [21].
two fuses and one triode for alternating current (TRIAC) Specifically, Sa2 has to withstand the total dc-bus voltage,
incorporated and is shown in Fig. 2(b) [14]. Here, in the case which leads to the oversized design of the semiconductors. A
of S1 short-circuit, S2 is blocked and TN is triggered to clear the similar approach is applied in other 3-level topologies, like T-
fuse F1. However, this strategy still has the drawback of type [22], active NPC [23], etc. It is worth mentioning that,
increased parasitic inductances. when the middle switches fail in open-circuit in T-type three-
Strategy 3 is presented in Fig. 2(c). In order to eliminate the level converters, it can be degraded into two-level without any
parasitic inductance due to the added fuses, the fuses are loss of output voltage.
β
removed to the output of each phase [15]. Since the fuses are npn ×
opn ppn
in series with output filter inductors, the effect of parasitic Sa1 Sb1 Sc1
inductances is not important. When a short-circuit fault occurs Da5 Db5 Dc5 npo opo
× ppo pon
in one of the switches, the complementary switch is blocked Sa2 Sb2 Sc2
non ×
oon
A
and the TRIAC is triggered on. Consequently, the fuse can be B
C
npp opp
× ppp poo pnn α
noo ×
ooo
nnn ×
onn
cleared. Still, the main drawbacks are as follows. 1) It cannot
handle the fault where two switches in one pole fail Sa3 Sb3 Sc3 nop ×
oop
nno
pop
×
ono pno
Da6 Db6 Dc6
simultaneously. 2) This approach isolates the whole leg, even
if just one switch fails. That means, as long as one switch fails, Sa4 Sb4 Sc4 nnp ×
onp pnp
the healthy switch in the same leg cannot continue operating. (a) (b)
Strategy 4 is shown in Fig. 2(d). Here, the fuse in strategy 3 Fig. 3. 3-level neutral-point clamped topology (a) Sa1 short-circuit failure (b)
is replaced by a controllable switch [16]-[17]. The switch can Voltage vectors diagram after the failure
be relays, TRIACs or bi-IGBTs. Compared to fuses, these
switches increase costs and losses. Also, different switches The fault-tolerant operation based on the vector redundancy
have special characteristics to accommodate. For instance, the is also employed in CMCs [24]-[25]. When some switches in
time response of relays is slow. The turn-off process of the circuit fail, the corresponding space vectors become
TRIACs is uncontrollable and the overload capability of invalid and the output voltage is decreased. In [26], the faulty
IGBTs is low [17]. Additionally, this approach still cannot cells also participate in the operation and contribute output
handle the fault of simultaneous two-switch failure. levels depending on specific faulty switches. In addition, in
Strategy 5 is presented in Fig. 2(e). Recently, new power order to solve the computational complexity with the increase
switches with high short-circuit capabilities and fast fuses of number of modules, the space vectors are defined in a 60°
have been developed. With the help of such power devices, it g-h coordinate system [27]. Based on the 60°g-h coordinate
is possible to implement a simple isolation [14]. When a short system, a pulse width modulation (PWM) pattern called large-
circuit occurs in either one of the switches, the complementary small alternation (LSA) is proposed [28]-[30]. Compared to
switch is turned on to cause a shoot-though loop, blowing out other methods, the LSA modulation results in output line-to-
the fuses. Still, the parasitic inductances of fuses exist. line voltages with the lowest THD in the post-fault [28].

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Note that this inherent redundancy exists in not only 3- 1) The performance in post-fault operations is degraded.
phase switching combinations, but also switching states of a Either the output voltage is reduced, or the blocking voltage of
single phase in some converters. For instance, in multilevel devices is increased, or suboptimal output THD occurs.
active clamped (MAC) converters, when the output is 1Vdc, 2) The fault coverage of this approach is limited.
two conduction paths can be selected as shown in Fig. 4(a), 3) The approach utilizing 3-phase redundant vectors can
which can be utilized for redundancy [31]. However, it only be employed in a three-phase three-wire system.
implies an increase of the blocking voltage of some devices in
some fault conditions. For instance, Sn31 has to withstand 2Vdc B. DC-Bus Midpoint Connection
when the output level is 3Vdc in the case of Sn21 short-circuit As for three-phase converters, if one phase fails, the
(see Fig. 4(b)). Alternatively, a scheme is proposed [31] to remaining two phases can maintain continuous operations.
maintain the original device blocking voltage but at the Three typical fault-tolerant topologies with additional switches
expense of some output levels. employed in motor applications are presented in Fig. 6 [33].
3Vdc 3Vdc
Sa1 Sb1 Sc1 Sa1 Sb1 Sc1 Sa1 Sb1 Sc1
C C C
Sp31 Sp31
Ta
O Tb O
Sn33 Sp21 Sn33 Sp21 Tc
2Vdc 2Vdc C C C
Sp22 Sn32 Sp11 Sp22 Sn32 Sp11 Sa2 Sb2 Sc2 Sa2 Sb2 Sc2
Sa2 Sb2 Sc2
TN TN
Sn22 Sp12 Sn31 Sn22 Sp12 Sn31 (a) (b) (c)
1Vdc 1Vdc Fig. 6. Switch-level fault-tolerant motor drives (a) Topology 1 (b) Topology 2
2Vdc
Sp13 Sn21 Sp13 Sn21 (c) Topology 3

0Vdc Sn11 Sn11 The first fault-tolerant topology shown in Fig. 6(a) forces
0Vdc
(a) (b) the faulty phase to connect to the midpoint of the DC-link via
Fig. 4.Multilevel active clamped topology (a) Output is 1Vdc (b) Sn31 the additional TRIACs [15], [34]. After faults, the
overvoltage when Sn21 is short-circuit reconfigured system is similar to the structure where only four
In order to further improve the fault-tolerance, some switches are used to drive a three-phase machine [35]. Note
auxiliary switches are added, which increase the number of that since the inverter is still capable of providing the full
redundant switching states. Fig. 5(a) presents a modified 5- rated current, the torque production will be preserved.
level MAC topology [31], where two auxiliary devices are Nevertheless, the main disadvantages are as follows.
added at terminals #2 and #4. A similar approach is applied in 1) The maximum balanced line-to-line output voltage in
general multilevel converters proposed by Chen et al [32]. post-fault operations is reduced to half of its nominal value.
This method can tolerate any single device failure without loss 2) This approach is only applied in situations where the
of any output-voltage levels. Nevertheless, the main midpoint of DC-link capacitors can be accessed.
disadvantages lie in these aspects. 1) An increased number of 3) Since the phase-current flows into the midpoint of the
conduction devices lead to higher conduction losses. 2) The DC-bus, oversized DC-bus capacitors are mandatory.
blocking voltage of some devices is unavoidably doubled. For The second method connects the neutral-point of the motor
instance, when Sp13 fails in short-circuit, Sp22 has to withstand to the DC-bus midpoint via the incorporated TRIAC TN as
2V shown in Fig. 5(b). 3) The modified architecture loses the shown in Fig. 6 (b) [36]-[37]. Note that only one TRIAC is
features of good symmetry compared to the original circuit. added for the fault-tolerance. In case of loss of one phase (e.g.
#5 #5 phase-A) as shown in Fig. 7(a), the magnitude of phase-B and
+ +
Sp41
V
Sp41
V phase-C currents is increased by √ and the phase shift
Sa1 - Sa1 -
Sp31 Sn44 #4
Sp31 Sn44 #4
between these two is regulated to 60°in post-fault operations
Sp32 + Sp32 + as shown in Fig. 7(b) [6]. Note that the modified control
Sp21 Sn43 V Sp21 Sn43 V
- - strategy leads to a zero-sequence current. Therefore, TN needs
Sp11 Sn42 Sp22 Sn33 #3 Sp11 Sn42 Sp22 Sn33 #3 to be turned on after faults to flow the neutral current.
Sn41 Sp12 Sn32 Sp23 + Sn41 Sp12 Sn32 Sp23 + Sa1 Sb1 Sc1

Sn31 Sp13 Sn22

V
-
#2 Sn31 Sp13 Sn22
V
-
#2
× ia A
Ic´
√3 pu Ic Pre-Fault
Sa2 + Sa2 + ib 30°
Sn21 Sn14 V Sn21 Sn14 V
O B vN Ia
- - ic C Post-Fault 1pu×
°
Sn11 #1 Sn11 #1 30
(a) (b) √3 pu Ib
Sa2 Sb2 Sc2
Fig. 5. Fault-tolerant multilevel active clamped topology (a) Normal Ib´
Operation (b) Output is 0V in the case of Sp13 short-circuit failure TN
(a) (b)
In summary, the main disadvantages of redundant switching Fig. 7. (a) Phase-A failure (b) Phasor diagram in the pre- and post-fault
states approach are as follows.
Nevertheless, the drawbacks of this approach can be
identified as follows.
1) The oversized semiconductors are necessitated.

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2) The maximum speed of the machine in post-fault is 2) Since the healthy phases have to withstand over-current
reduced to 0.5 of its nominal value because the equivalent after faults, oversized devices are necessary. Also, the over-
line-to-line voltages are decreased to 0.5pu. current is decreased with an increase of the phase number.
3) This approach can only be applied when the DC-bus 3) For a three-phase machine, a neutral connection is
midpoint and the motor neutral-point can both be accessed. necessary. If the neutral current flows into the DC-bus, it
4) The neutral-current is significantly increased, which necessitates oversized capacitors.
necessitates oversized DC-bus capacitors. A similar idea can be applied in 3-phase voltage source
The third method connects the neutral-point of a motor to inverters (VSIs). As shown in Fig. 9(a), the basic idea is to
an additional fourth leg [38]-[39]. As shown in Fig. 6 (c), an constantly force the output voltage of the faulty phase to zero
extra leg and a TRIAC are incorporated. It is worth and regulate the phase-angle of the other two phase voltages,
mentioning that the fourth pole can be permanently connected maintaining balanced line-to-line voltages in post-fault. As
to the converter even in normal operations without TRIACs shown in Fig. 9(b), the phase angles of phase-B and -C will be
[38]-[39]. Compared to the previous two solutions, this shifted by 30°away from the faulty phase (phase-A) [19]. Note
topology yields the following good features. that the equivalent balanced phase-voltages in post fault
1) The system is free of the DC-bus midpoint balancing conditions (vAE', vBE', vCE') are only ⁄√ of those in normal
problems and minimum capacitance sizing. conditions as shown in Fig. 9 (b).
2) The line-to-line voltage can be increased to 1pu Sa1 Sb1 Sc1 VC
compared to previous methods.
A similar principle can be applied in five-phase motors as × VC´

30°
shown in Fig. 8. However the solution for generating the O
vA VCE´
unchanged rotating magneto motive force (MMF) is not vB VA
×
VAE´
unique. Normally, two strategies are employed [40]-[42], (see vC
VBE´ 30°
Fig. 8(b)-(c)). In the first scheme, there is an attempt to Post-Fault Pre-Fault
generate the unchanged rotating MMF with the minimum Sa2 Sb2 Sc2 VB´
possible current magnitude of the remaining healthy phases. (a) VB (b)
All the current references are increased by 1.314 times and Fig. 9. Two-phase control in voltage source inverters (a) Phase-A failure (b)
shifted by 18 degrees as shown in Fig. 8(b). However this Phasor diagram in the pre- and post-fault
solution exhibits a zero-sequence current component. In the
second strategy, the current references of the healthy phase are Following a similar approach, TRIACs are added to 6-leg
modified to achieve undisturbed MMF and eliminate zero- AC-DC-AC converters [45], 5-leg converters [46], nine-
sequence current components. In this case only two current switch converters [47], and matrix converters [48]-[50] for
reference vectors are rotated by 36 degree (see Fig. 8(c)). fault-tolerance. Note that the matrix converter is treated as a
However, the magnitude of the remaining phase has to two-stage rectifier/inverter [51]-[52]. The existing modulation
increase by 1.38 times to achieve the unchanged MMF. A techniques for the inverter stage can be used. As for multilevel
similar approach can be applied in other multi-phase motors, converters, an additional TRIAC TN is employed in NPC
like six-phase [43], four-phase [44], etc. converters to connect the output to the mid-point as shown in
Sa1 Sb1 Sc1 Sd1 Se1 Fig. 10(a) [20], [53]. An alternative scheme is the active-NPC
× topology as shown in Fig. 10(b) [23], [54], which utilizes
ib
ia IGBTs to replace clamped diodes, such that the output
O
ic
id
terminal of the faulty phase can be connected to the mid-point
ie via S2/S5 or S3/S6. However, the output voltages in these two
approaches both are reduced after faults. In an attempt to
Sa2 Sb2 Sc2 Sd2 Se2
TN
overcome this problem, some fast fuses and thyristors are
added as shown in Fig. 10(c) [55]-[56]. In case of a short-
(a) circuit fault, the corresponding thyristor is triggered to clear
Ie´ I d´
18° Ie´ the associated fuse. Consequently, the faulty leg is
36°
18° reconfigured into a two-level structure. However, some
Id´
× Ia × Ia semiconductors have to withstand overvoltages. A similar
Ic´ 18° Ic´
18° 36°
I b´ approach is applied in active-NPC [55]-[56] shown in Fig.
I b´ 10(d). Due to the additional switching states provided by the
(b) (c) extra switches S5/S6, the faulty leg is still able to achieve three
Fig. 8. Five-phase machine (a) Phase-A failure (b) Strategy 1 in case of phase-
voltage levels in some fault conditions. However, the main
A failure (c) Strategy 2 in case of phase-A failure
drawback remains the oversized semiconductors.
The disadvantages of this approach in motor applications In additional, Ma et al. applied the two-phase control in
are as follows. general multilevel converters, which combined dc-component
1) The method only can handle open-circuit failures injection as well [57]. However, the reduced output voltage is
happening in the signal-phase or multiple phases. still the primary issue during post-fault conditions.

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S1 S5 S1 T1 S1 T1 S5 S1
2) In the offline scheme, one redundant unit is shared by
multiple main switches, which can reduce the system cost.
F1 S2 F1
S2 S2 S2 However, more linking switches are introduced.
3) In the offline scheme, the linking switches increase the
TN S6
S3 S3 S3 S3 conduction loss in post-fault. In the online scheme, the parallel
F2 F2
switches can reduce conduction losses in normal conditions.
S4 S6 S4 T2 S4 T2 S4
2) Redundant Series Switch
(a) (b) (c) (d) The two-level voltage source converter with IGBTs directly
Fig. 10.Switch-level fault-tolerant multilevel converters (a) Topology 1 (b) in series is widely used in flexible HVDC transmissions [60].
Topology 2 (c) Topology 3 (d) Topology 4 The redundant devices are connected in series with main
switches for short-circuit failures as shown in Fig. 12(a) [61].
C. Redundant Parallel or Series Switches Installation The overall conduction losses are doubled in normal
1) Redundant Parallel Switch operations. Also, the voltage sharing issue among the series
This approach places extra switches in parallel with the devices has to be addressed. In addition, some switches have
main switches. Based on whether or not the redundant switch to withstand overvoltages after short-circuit failures. In order
is operated in normal conditions, this method is implemented to further handle open-circuit failures, this topology is
in two ways: offline scheme and online scheme. modified by adding parallel thyristors as shown in Fig. 12(b)
In the offline scheme, the redundant switch is not operated [62]. However, this scenario is at the expense of higher costs.
in normal conditions. When a fault occurs, the redundant Another topology providing the series redundancy is flying
switches are activated to replace faulty switches. As shown in capacitor multilevel converters (FCMCs). As shown in Fig. 12
Fig. 11 (a), the traditional MC is accompanied by a (c), an fault-tolerant design for three-cell 4-level FCMC is
bidirectional switch and a series of relays [58]. The redundant proposed in [62]-[63]. When a single-switch fault occurs, the
switch can replace any of the switches via selecting relays. In faulty switch and its counterpart are bypassed. The
order to increase the system availability, more redundant corresponding capacitor is isolated from the system or
switches can be added [58]. A similar approach is introduced constantly connected in parallel with another capacitor.
into two-level inverters [59]. Thyristors can replace relays to However, the primary disadvantages are the following.
reduce the transition time due to their short turn-on time. 1) Some switches need to withstand the full DC-link
voltage after failures.
SR SR11
R1 R2 R3
2) The series switches (K1, K2) experience on-state losses
SR12
R4 R5 R6 during normal operations.
SR13
SaU SaV SaW K1 S1
SR1 SR1
SR14
SbU SbV SbW K2 S2
SR24
S1 S1 S3
SR23 + + +
ScU ScV ScW 3V - 2V- V
SR22 -
S4
Relay SR21
S2 S2
S5
(a) (b)
Fig. 11. Redundant parallel switch (a) Offline-switch scheme (b) Online- SR2 SR2 S6
switch scheme
(a) (b) (c)
Unlike the offline scheme, the redundant switch in the Fig. 12. Redundant series switch (a) Topology I (b) Topology II (c) Topology
online scheme participates in normal operations. Reference III
[31] connects two devices in parallel for MAC converters
shown in Fig. 11(b). Note that the redundant switches are only V. FAULT-RECONFIGURATIONS: LEG-LEVEL
placed in the highest-level and lowest-level paths because the
In this section, two types of leg-level hardware
redundancy of the middle levels is achieved by the redundant
redundancies and associated control strategies are introduced,
switching states discussed above. The parallel devices can
which are redundant parallel leg and redundant series leg.
reduce the overall conduction losses in normal operations.
However, the current sharing issue has to be addressed.
A. Redundant Parallel Leg
To sum up, the main features of the redundant parallel
switch approach are as follow. This approach is implemented via adding a parallel
1) Relays and SCRs are normally selected as linking redundant leg. Depending on whether or not the redundant
switches. Compared to relays, SCRs have faster transient time, parallel leg functions in pre-fault, there are two schemes:
potentially shortening the system reconfiguration process. offline leg scheme and online leg scheme.
Fig. 13(a) presents a solution based on an offline parallel
leg [64]. Since the number of the redundant leg is only one,
three main legs share it together which reduces the entire cost.

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Meanwhile, three TRIACs, e.g. TA~TC, are added as linking 4) The backup leg can operate in online or offline mode.
switches. Before faults, the additional leg is inactive. When a The loss is higher in the online mode due to the fact that the
fault occurs, the spare leg replaces the faulty leg. Note that the additional leg is operating. However, the online backup leg
topology can only cover the fault happening in a single phase. can help improve the output quality in normal conditions.
A similar approach is applied in doubly fed induction
generator (DFIG) systems [65] and HEVs [16], [66]. It is B. Redundant Series Leg
observed that multiple converters share one redundant leg to The series redundancy leg is widely applied in 3-phase
reduce system costs. In order to increase the system motor drives [71] as shown in Fig. 15(a). Note that the voltage
availability, the number of the redundant legs is increased up space vectors are the same as 3-level inverters [72]. In case of
to three [61] as shown in Fig. 13(b). Since relays have a short- or open-circuit failures, the faulty leg stops working,
considerable amount of delay, they can be replaced with bi- while the two remaining phases continue operating to maintain
directional switches to shorten the dynamic process [67]. the original flux. However, the output voltage is reduced
Sa1 Sb1 Sc1 SR1 Sa1 SRa1 Sb1 SRb1 Sc1 SRc1
during post-fault operations. Therefore, an alternative
configuration using the same number of switches with two
isolated and unequal dc-link voltages (Vdc1,Vdc2) is reported as
Sa2 Sb2 Sc2 SR2
shown in Fig. 15(b) [73]-[74]. The output capability of the
Sa2 SRa2 Sb2 SRb2 Sc2 SRc2
TA system can be increased to some extended. However, the
TB
TA TB TC oversized semiconductors are still necessitated.
TC
Sa1 Sa2 Sb1 Sb2 Sc1 Sc2
A B C Sa1 Sb1 Sc1 Sa3 Sb3 Sc3
A B C
(a) (b) Vdc
Vdc1 Vdc2
Fig. 13. Offline parallel redundancy leg solutions (a) One redundant leg (b) Sa3 Sa4 Sb3 Sb4 Sc3 Sc4
Three redundant legs
B Sa2 Sb2 Sc2 Sa4 Sb4 Sc4
C
In the online leg scheme, the redundant leg operates even in A

normal conditions to improve the system behavior. Two

(a) (b)
modified topologies based on the 3-level NPC topology are Fig. 15. Series redundancy leg solutions (a) Topology 1 (b) Topology 2
presented in Fig. 14 [68]-[70]. Taking the circuit in Fig. 14(a)
as an example, the fourth leg adopts a flying capacitor VI. FAULT-RECONFIGURATION: MODULE-LEVEL
topology different from the main legs. In normal conditions,
this additional leg provides a stiff neutral-point voltage. When CMCs and MMCs are typical circuits with module-level
a fault occurs (e.g. phase-A), the fuses Fa and F are blown out redundancy. If some modules fail, the other modules
first. Then, SR5, SR6 and Ta are activated. Consequently, the implement the fault-tolerant reconfiguration to maintain
faulty leg is substituted by the fourth leg and the system is continuous operations. The main approaches are neutral-shift,
reconfigured as a standard NPC converter. A similar principle dc-bus regulation and redundant module installation.
can be applied in the circuit in Fig. 14(b).
Sa1
A. Neutral-Shift
SR1 SR1 Sa1
C1
C1 Sa2 SR2 Sa2 After faults, an unequal number of modules are applied in
Phase C

S2
Phase B

SR2
Phase B

Phase C

Fa Fa
SR5 SR6 F L F Ta three phases. Therefore, this method is attempted to modify
SR3
Ta SR3 Sa3 phase shifts among phase-voltage references to maintain
C2 Sa3
C2 SR4
balanced line-to-line voltages in post-fault. It functions as
SR4 Sa4
Sa4 though the equivalent neutral-point is shifted after faults, so it
(a) A (b) A is called neutral-shift (NS) method.
Fig. 14. Online parallel redundancy leg topologies (a) Flying capacitor Taking the 5-module 11-level CMC as an example, when a
redundant leg (b) Inductor redundant leg fault occurs with two faulty modules in phase-b and one faulty
To sum up, the principle features of the parallel leg module in phase-c, the unbalanced line-to-line voltages are
approach are identified as follow. applied. To keep balanced line-to-line voltages, the simplest
1) The number of the redundant legs can be from 1 to 3. solution is to bypass an equal number of modules per phase as
The number is a balance of offsetting the improved reliability shown in Fig. 16(a) [75]. However, this approach results in
with the increased costs. very low output voltages. Therefore, [76] introduces the NS
2) In the offline scheme, the linking switches are required. method to maximize the line-to-line voltages, where the
The added linking switches increase the conduction loss in angles of the phase voltages are recalculated after faults. The
post-faults. Therefore, it is significant to apply semiconductors phase-shift angles for different faults [77] are
with a lower on-state resistance as the linking switches.
Va  Vb  2VaVb cos    Vb  Vc  2VbVc cos     Va  Vc  2VaVc cos  
 2 2 2 2 2 2
3) The topology of the redundant legs could be the same, or 
      360

different, as that of legs in the original circuit. Hence, it can  (1)
select its own topology based on the specific requirements.

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where Va, Vb, Vc are the magnitudes of three phase voltages, In summary, the NS method is easy to be implemented.
and α, β, γ are the angles between every two phase-voltages. Nevertheless, the primary disadvantages are as follows.
Va Va 1) This approach cannot be employed in the application of
×
a 5 a5
three-phase 4-wire systems.
×
a 4 a4
2) The full voltage in normal situations still cannot be
a3 a3
a2 6.67 6.67 achieved during post-fault conditions.
a2
5.2 3) In post-fault conditions, the load power factor not only
120 °

113 °
5.2

ɑ=
ɑ=

a1 a1

97
depends on the load characteristic, but also on how much the
120
γ=

°
γ=
c1 b1 c1 b1 b2 b3
°

c3
c2 b
β=120° 2 b3 c3
c2 β=150° b4 b5 Vb
× neutral-point is shifted.
×× ×× ××
c 4 5.2 b4 c4 6.67 Va Zero-Sequence Injection Va(2)
Vc c5 b5 Vb Vc c5
a3 Va(1) Neutral-Shift
(a) (b) a2 2.3 Va(2) 1 Va(1)
Fig. 16. (a) Bypass equal number of modules (b) Neutral-shift approach
120
c1
° a1
120°
b1
120° 120°
120°
+ Vc(2) 1
60° =
°
Based on (1), the output voltages based on the NS method c2 b2 2.3 2.3 120° 120
c3 120° × Vc(1) Vb(1)
b3 Vc(1) Vb(1) 120°
are shown in Fig. 16(b). Compared to the method in Fig. 16(a), Vc Vb Vc(2)
the output line-to-line voltages are increased by 28%. (a) (b)

However, Fig. 18. (a) One module in phase-b failure (b) Vector diagram for post-fault
1) Since (1) is nonlinear and the number of possible faults is Since the injected zero-sequence component is all
limited, the use of a pre-calculated table is recommended to fundamental frequency, the NS method limits the range of
avoid complex online calculations [19]; load power factor [82]. Therefore, some alternative zero-
2) According to [77], (1) may have multiple solutions for sequence component injection methods with non-fundamental
some fault conditions. Also it does not always result in the frequency based on the carrier-PWM are proposed to
maximum possible value of the output line-to-line voltages. eliminate the adverse effect of the NS method [80]-[81].
To overcome these problems, an extension of NS method is Furthermore, Carnielutti et al. analyzed a formal
proposed [77], where the angle between the two voltages with mathematical derivation to establish a theoretical background
the lowest amplitude values is forced to be 180°, and both the [82]. For a given fault condition, the optimum zero-sequence
magnitude and the phase of the other phase are adjusted to components for the output line-to-line voltages are obtained.
achieve maximum output voltages as shown in Fig. 17(a). Fig. However, the process of obtaining the zero-sequence
17(b) and (c) present an example with 3 faulty modules in component in this method is relatively complex.
phase-b and 2 faulty modules in phase-c with two methods.
Compared to the traditional NS method, the extension of the B. DC-Bus Voltage Reconfiguration
NS method can increase the output voltage by 15%.
Va Va
It is noted that a common drawback of the previous method
Va a5 a5 is the reduced output voltage during post-fault operations.
a4 a4 Therefore, in an attempt to sustain an unchanged output
a3
4.36 a3 voltage, an alternative approach is to increase the input DC-
4.36 5 5
a2 Vb
a2 bus voltage. The DC-bus voltage reconfiguration is generally
Vc 4.36 b3 a1 categorized by whether the overvoltage is withstood only by
γ α c2 a1 b2 Vc ° 84° Vb
° 60°
c1 60 b1 c2 c196 b1 b2 b3 the faulty phase or shared among three phases.
Vc Vb
(a) (b) (c) In applications of static compensators [83]-[84], H-bridge
Fig. 17. (a) Extension of neutral-shift method (b) Result of traditional neutral- modules in a CMC are used as active rectifiers. When the
shift method (c) Result of extension of neutral-shift method faults occur, the DC-link voltages of the remaining modules in
the faulty phases are increased to keep the total voltage
The additional limitations of the traditional NS method are unchanged. For example, in the case of the fault as in Fig. 19
detailed in [78], which affects the output power factor (PF) of (a), the voltage stress on remaining semiconductor devices is
the converter. Therefore, in some types of faults, PF angles increased by 200% (shown in Fig. 19 (b)).
could be greater than 90°even if the load is not an active load. Va Va Va
a3 a3 a1
In this case, the inverter will absorb the power instead of
a2 a2
supplying the load, which may lead to its destruction. 3.61 5.19 5.19 5.19 5.19
a1
5.19
a1 a1
Reference [79] proposed a variant method combining the 120° 120° 120° 120° a1
merit of the neutral-shift and the 3rd zero-sequence injection. ×
c2
c1
120°
b1
b2
b1
3 120° b2 b V Vc c2 .3
140°80°
5 b1 b2
Vc ×
c3 b3 Vb Vc c2 3 b 1 b3 Vb
After the occurrence of a fault, the converter can be analyzed 3.61 5.19 5.19
as two separate systems. The first one can operate as a three- (a) (b) (c)
Fig. 19. Dc-bus voltage reconfiguration (a) Fault occurrence (b) Strategy 1 (c)
phase balanced system with 3rd harmonics injection to increase
Strategy 2
the modulation index by 1.15 times, and the second one can
operate with the NS approach to obtain balanced three-phase Unlike the previous method, the approach in [84]-[85]
voltages. Fig. 19 illustrates an example with a phase-b module introduces a neutral shift, sharing the increased voltage burden
failure. The resultant modulation index can reach 0.83pu. equally among all healthy modules of three phases. As shown

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in Fig. 19 (c), the DC-link voltage of the remaining modules is and phase-leg open-circuit. However, the power rating after
only increased by 35% with this method. faults is degraded. Parallel converters have been used to
Although the output voltage can be sustained at same level improve the reliability in active power filters [89],
as that in the pre-fault condition, the principle drawbacks of uninterruptible power supplies (UPSs) [90], and DFIGs [91].
the DC-bus voltage reconfiguration still exist as follows. As shown in Fig. 21 (b), one of inverters is operated in normal
1) The increased DC-bus voltage can expose a higher condition. When faults occur, the other inverter can replace
voltage stress on the devices, necessitating oversized design. the faulty one for continuous operation. However, when the
2) The combination of the DC-bus reconfiguration and dual converters are operated at same time during normal
neutral-shift can only be applied in three-phase 3-wire systems. situations, the reduction of circulating currents among
Moreover, another post-fault reconfiguration to maintain converters is an important objective to address. Several
output voltage is realized by regulating the output transformer control techniques have been developed to ensure equal load
turn ratio [86]. This reconfiguration method is based on a sharing [92]-[93]. As shown in Fig. 21(c), the current sharing
multi-coil transformer and a set of bidirectional valves for the is controlled via regulating the magnitude and the phase angle
system fault-tolerance. However, the added hardware of the output references. In addition, this concept is applied in
increases the system costs greatly. DC/DC converters, AC/DC converters, etc. Two common
connection structures are common DC-bus and high frequency
C. Redundant Modules Installation AC-bus.
Sa11 Sb11 Sc11 Sa11 Sb11 Sc11 #1 Group
For CMCs, redundant modules are added in series with the i1a Ta1
basic topology as shown in Fig. 20(a). Normally, the C C v1a Tb1
Tc1
redundant modules are inactive. When any module has a fault, Sa12 Sb12 Sc12 Sa12 Sb12 Sc12

it will be isolated by setting the bypass switch T in the “3-4” AC

Sa21 Sb21 Sc21 Motor Sa21 Sb21 Sc21 #2 Group
position. Subsequently, the redundant module starts to replace i2a
Ta Ta2
the faulty module and reestablish the normal operation. The Tb
Tc
v2a Tb2
Tc2
Sa22 Sb22 Sc22 Sa22 Sb22 Sc22
bypass switches can be simplified by applying the failure
(a)
characteristics of semiconductors. In contrast, in [83], the (b)

redundant modules are active in normal operations. Therefore, P1a

Normal
* =P2a
* =50%Poa
#1 group failure
* =100%Poa
P2a
#2 group failure
* =100%Poa
P1a
the output quality is improved compared to the previous * =50%Qoa Q2a
* =Q2a
Q1a * =100%Qoa * =100%Qoa
Q1a
v1a i1a V1a*
method. However, the conduction losses are relatively higher. P1a* P,Q ΔV1a Sine Generator
v1a_ref
v1a
Voltage i1a_ref
i1a
Current
ga11
Q1a* Δφ1a PWM
The fault-tolerant control is shown in Fig. 20(b). It can be seen Controller
φa*
V1asin(ωt+φ1a) Controller Controller ga12
PLL
that the output voltage amplitude of the each cell in faulty Phase A in #1 Group
v2a i2a V2a*
phase is increased after faults. A similar approach can be P2a*
P,Q ΔV2a Sine Generator
v2a_ref
v2a
Voltage i2a_ref
i2a
Current
ga21
Q2a* Δφ2a PWM
applied in MMC [87]-[88], shown in Fig. 20(c). The Controller
φa
* V2asin(ωt+φ2a) Controller Controller
ga22

redundant modules adopt the online mode, which can reduce PLL Phase A in #2 Group
CAN Synchronization
(c)
the transition time and the charge time of redundant modules. Bus Bus

Redundant Module Fig. 21. (a) Series converters for motor drive (b) Parallel converters for UPS
A +Vdc
A1 A2 …… AN AR Redundant
Modules
Redundant
Modules
Redundant
Modules system (b) Control strategy for parallel UPS system
B M_Ap 1 M_Bp 1 M_Cp 1
O B1 B2 …… BN BR N

C1 C2 CN CR C
M_Ap 2 M_Bp 2 M_Cp 2 VIII.CONCLUSIONS
……
……

……

……

Each Module T
1 2
S1 This paper presented a comprehensive review of fault-
S1 S3 M_Ap N M_Bp N M_Cp N
3 4 S2 tolerant techniques in power electronic converters that have
S2 S4

(a) A B C been introduced in past literatures. The fault-tolerant solutions

Voltage (N+1)×vosin(ωt-120º)
(N+1)×vosin(ωt+120º)
1/NC are always based on hardware redundancy plus associated
1/NB M_An N M_Bn N M_Cn N
Controller (N+1)×vosin(ωt)
1/NA control strategies. Therefore, the conventional fault-tolerant
……

……

……

Bypass PWM A1 PWM B1 PWM C1

techniques are classified into switch-level, leg-level, module-
Fault- Faulty Cells
M_An 2 M_Bn 2 M_Cn 2

Tolerant
Recalculate
level and system-level solutions based on the type of hardware
Controller M_An 1 M_Bn 1 M_Cn 1
NA, NB, NC
PWM AN PWM BN PWM CN
Redundant Redundant Redundant
redundancy. Various approaches are presented and their
NA, NB and NC are the numbers
PWM AR PWM BR PWM CR
of operative cells in each phase Modules Modules Modules
advantages and disadvantages are analyzed in detail. It is
(b) -Vdc (c)
shown that some fault-tolerant methods, such as redundant
Fig. 20. Series redundant module (a) Cascaded converters topology (b)
switching states and neutral-shift, are easily implemented and
Cascaded converters control (c) modular multilevel converters topology
cost-effective, but cannot maintain the full rated power after
faults. Therefore, in mission critical applications, the full
VII. HARDWARE RECONFIGURATIONS: SYSTEM-LEVEL
fault-tolerant design serves as a more suitable option.
In this section, two types of system-level hardware Therefore, multiple modified topologies with full fault-
solutions for fault reconfiguration are introduced, which are tolerant capability are summarized. Among them, the
cascaded converters and parallel converters. As shown in Fig. redundant parallel leg topology is recognized as the optimal
21(a), three switches are added in series with each output compromise between system cost, performance and reliability.
phase [6]. Therefore, the modified configuration is able to Additionally, the implementation of redundant parallel
handle single switch short-circuit, single switch open-circuit,

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20,2008, pp. 1683–1685. Science and Technology, Nanjing, China, in 2008.
[76] P. W. Hammond, “Multiphase power supply with series connected He is currently pursuing the PhD. degree in the
power cells with failed cell bypass,” U.S. Patent 6 222 284, Apr. 24, Department of Electrical Engineering, Zhejiang
2001. University, Hangzhou, China.
[77] P. Lezana and G. Ortiz, “Extended operation of cascade multicell From Sep. 2012 to Sep. 2013, he was a visiting
converters under fault condition,” IEEE Trans. Ind. Electron., vol. 56, no. student in electrical engineering at Texas A&M
7,pp. 2697–2703, Jul. 2009. University. His research interests include fuel cell
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2002. and Ph.D. degrees from the Department of
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Tolerant Operation of H-Bridge Multilevel Inverters," Industrial Hangzhou, China, in 1983, 1986, and 1989,
Electronics, 2006 IEEE International Symposium on , vol.2, no., respectively. Since 1996, He becomes a full
pp.1589,1594, 9-13 July 2006 professor in College of Electrical Engineering of
Zhejiang University. He was a visiting scholar in
[80] P. Hammond and M. F. Aielo, “Multiphase power supply with plural
University of Tokyo, Japan from Jun. 1995 to May
series connected cells and failed cell bypass,” U.S. Patent 5 986 909,
1996. From Jun. to Dec. of 2000, he was a visiting
Nov. 16, 1999.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2014.2304561, IEEE Transactions on Power Electronics

professor in CPES of Virginia Tech, United State. From Feb. 2006 to Apr. renewable energy conversion, etc.
2006, he was a visiting professor in ETH, Switzerland. He is interested in
power electronics topology and control, power conversion for energy saving
and renewable energy. He has authored five books and more than 350 papers.
He owns 3 US patent and 20 Chinese patents. He has received three IEEE
paper awards.
Presently he is a board member of Electrical Engineering Discipline of
China State Department Education Degree Committee. He is president of
China Power Supply Society. He was an at-large AdCom member of IEEE
power electronics society from 2006-2008. He is an associate editor of both
IEEE Transaction on Power Electronics and IEEE Transaction on Sustainable
Energy. He was technical program chair of IEEE International Symposium on
Power Electronics for Distributed Generation Systems (PEDG2010), general
chair of PEDG2013, and general chair of IEEE International Symposium on
Industrial Electronics (ISIE2012).
Prasad N. Enjeti (M’85–SM’88–F’00) received the
B.E. degree from Osmania University, Hyderabad,
India, in 1980, the M. Tech degree from the Indian
Institute of Technology, Kanpur, in 1982, and the
Ph.D. degree from Concordia University, Montreal,
QC, Canada, in 1988, all in electrical engineering. In
1988, he joined, as an Assistant Professor, the
Department of Electrical Engineering Department,
Texas A&M University, College Station. In 1994,
he was promoted to Associate Professor and in 1998
he became a Full Professor. He holds four U.S. patents and has licensed two
new technologies to the industry so far. He is the lead developer of the Power
Electronics/Power Quality and Fuel Cell Power Conditioning Laboratories,
Texas A&M University and is actively involved in many projects with
industries while engaged in teaching, research and consulting in the area of
power electronics, motor drives, power quality, and clean power utility
interface issues.
Dr. Enjeti received the inaugural R. David Middlebrook Technical
Achievement Award from the IEEE Power Electronics Society in 2012. He
received the IEEE-IAS Second and Third Best Paper Awards in 1993, 1998,
1999, 2001, and 1996, respectively; the Second Best IEEE-IA
TRANSACTIONS paper published in mid-year 1994 to mid-year 1995, the
IEEE-IAS Magazine Prize Article Award in 1996, the Class of 2001 Texas
A&M University Faculty Fellow Award for demonstrated achievement of
excellence in research, scholarship and leadership in the field, and he directed
a team of students to design and build a low cost fuel cell inverter for
residential applications, which won the 2001 future energy challenge award,
grand prize, from the Department of Energy (DOE).
Haijin Li (S’13) received the B.S. degree in electrical
engineering, from the Department of Electrical
Engineering, Zhejiang University, Hangzhou, China, in
2010. He is currently pursuing the Ph.D. degree in the
Department of Electrical Engineering, Zhejiang
University, Hangzhou, China.
His current research interests include fuel cell power
system, efficiency optimization for inverter.

Joshua T. Hawke (S’11) received the B.S. degree in

electrical engineering from Texas A&M University,
College Station, TX, USA in 2007. He is currently
working towards his Ph.D. degree in electrical
engineering at Texas A&M University.
From 2010-2011, he was an Application Engineer
for Maxwell Technologies in San Diego, CA, USA.
His current research interests include multiport
converters clean and renewable energy technologies, as
well as multiport power conversion.
Harish S. Krishnamoorthy (S’12) received his B.
Tech degree in Electrical & Electronics Engineering
from National Institute of Technology, Tiruchirappalli
in 2008. He is currently working towards his Ph.D.
degree in electrical engineering at Texas A&M
University.
From 2008 to 2010, he was an Engineer in General
Electric (GE) Energy, India. His current research
interests are in high power density converter design,

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