2019 IEEE 4th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC 2019)

Modeling and analysis of single event crosstalk in

multi-lines system
Baojun Liu1, Bo Wei2, Shuang Zhang1, Li Cai2, XiangYan Luo1, Yin Gu1
1. Aviation Maintenance NCO Academy, Air Force Engineering University, XinYang, HeNan 464000, China
2. Department of Basic Science, Air Force Engineering University, Xi’An, ShannXi 710051, China
[email protected], [email protected], [email protected], [email protected], [email protected],
[email protected]

Abstract—With device feature size scaling down, single event These models and analyses of SEC are based on the
crosstalk (SEC) effects should be considered carefully in the coupled two-line interconnects system, which is not justified
early design stages of circuits applied for space and ground in a practical scenario. However, the models of SEC in a
radiation environments. A model for predicting SEC in 3-lines 3-lines have not been reported. Focused on 3-lines system
system is proposed based on the point admittance and the with a step or ramp input signal, many models were presented.
distribution network of the lines. By using the presented model, Based on the effective interconnects model, a crosstalk model
1000 random generated circuits are modeled and tested. The was proposed [8], where CMOS device was simply
simulation results show that the model has average error 5.52%, approximated as a linear device, which is not applied to the
whose results match SPICE very well. The relevance between the analysis of nanometer CMOS SEC noise. T. Kim et al [9]
parameters of the lines and the prediction accuracy of the model developed an analytical compact-form crosstalk model of
is analyzed by using grey theory.
inductive-effect-prominent multiline, by using a symbolic
operation. The other methods have been also applied for
Keywords—single event crosstalk; model; multi-lines system; modeling and analyzing crosstalk, such as Fourier analysis,
point admittance; interconnect ABCD, finite difference time domain (FDTD) and so on
[10-12]. However, those models may be too time inefficient
I. INTRODUCTION or computation complicated and cannot be extended to the
As technology node scaled down, single event transient evaluation for SEC of 3-lines system.
(SET) becomes the most serious threat for the reliability of
The rest of the paper is organized as follows. Section II
integrated circuits (ICs) with advanced process in the future,
introduces the circuits of 3-lines and its equivalent circuits. In
which should be highly concerned [1-2]. With CMOS
Section III, an analytical model for evaluating SEC in 3-line
technology scaling continuing and operating frequencies
system is proposed. The verification an analysis of the
increasing, SET might bring noise into electronically
proposed SEC model is performed in Section IV. Lastly, the
unrelated multiple logic circuit paths due to increased
paper is concluded in Section V.
crosstalk effects between interconnects, which can intensify
the SET susceptibility of nanometer CMOS circuits[3-4]. II. SEC CIRCUIT OF MULTI-AGGRESSOR
Therefore, single event crosstalk (SEC) effects should be INTERCONNECT
considered in the early stages of modern high-performance
very large scale integration (VLSI) designs flow and signal In general, although the interconnect lines are modeled
integrity for application to space and ground radiation as distributed RLC transmission lines for nanometer CMOS
environments[5-6]. Modeling efficiently and accurately SEC technology, the inductive coupling noise can be neglected as a
waveform shape and noise peak voltage in a first-order approximation due to the driver resistance
driver-interconnect load system has been a very important moderate and a high impedance capacitive load for practical
design concern that should be considered [4-5,7]. Previously CMOS circuits [13]. In this paper, 3-lines are modeled as
many works have been studied on SEC evaluation and distributed RC configuration, shown in Fig.1 (a). Each line is
analysis. S. Sayil et al [4] proposed a method, which used an divided into n segments. rij, Cgij, and Ccij (i=1,2,3, j=1,2,…,n)
accurate 4-π RC model for interconnect, to correctly model are the ith line self-resistance, self-capacitance and
SEC noise with an average error for noise peak about 5.2%. B. coupled-capacitance between the ith and the i+1th line of the
Liu et al [5] presented a model to predict SEC, which used a jth segment, respectively.
6-node template circuit of interconnect, with the average error
of 3.07% in noise peak and 8.11% in pulse width, respectively.
A Balasubramanian et al [7] quantified the dependency of
SEC on the interconnect length and on the amount of
deposited charge at 90 nm technology for two different supply
voltages.

978-1-7281-1907-6/19/$31.00 ©2019 IEEE 1928

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 initially establishing the ion track.
An equivalent circuit of RC parallel network model can
be used to calculate circuit response to SET. The victim line
are replaced by RC parallel model. The outputs of the lines
are replaced by the load capacitances, respectively. The
equivalent circuit of SEC in multi-aggressor interconnect is
shown in Fig.2.

C1

aggressor 1 R1
CL1
Cs1
Rs1 Ip1

Hits1 C1 Cc1
Line 1
R1
victim 2 R2
CL2
Cs2 C2
Cc1 Rs2
Line 2
Cc2

R2
C2
aggressor 3 R3
C3 CL3
Hits2 Cs3 Ip3
Cc2 Rs3
Line 3
R3 C3 Fig. 2 equivalent circuit of SEC
（b）

Fig.1 RC network of lines: (a) distributed model; (b) effective lumped III. SEC EVALUATION OF 3-LINES SYSTEM
configuration.
The equivalent circuit is arranged as shown in Fig.3.
Based on the same Elmore time constant, the above Cc1
Cc2

mentioned distributed RC network for interconnect can be

2 3
considered as a lumped configuration with the effective 1
R1 R2
self-resistance, self-capacitance and coupled-capacitance [13], R3

shown in Fig.1 (b), where Cs1 C1 CL1 C2 CL2 Cs2 C3 CL3 Cs3
Ip1 Rs1 Rs2 Rs3 Ip3
n
Ri   rij / 2
, (i=1,2,3) （1a）
j 1

n , (i=1,2,3) （1b）
Ci   Cgij / 2 aggressor 1 victim 2 aggressor 3
j 1
n
Cci   Ccij , (i=1,2) （1c） Fig.3 equivalent circuit of SEC in 3-line system.
j 1
Based on the superposition theorem, the final crosstalk
For convenient calculation, we assume that SET occurs response voltage of the victim line is the sum of the output
at the first line and the third line input nodes, respectively, voltages for each aggressor line processing separately. Firstly,
shown in Fig.1 (b). The second line is the quiet victim. In we calculate the response voltage of victim 2 only under the
circuit analysis of SET, a transient current source is process of aggressor 1 when the current source of aggressor 3
introduced at the circuit node where the energetic particle hit is set to zero.
occurs [5,14]. The transient current source is always modeled
by a double exponential function as: For the Laplace transformation of the point admittance of
a general node Y(s), it can be expanded s3 Taylor series to
Qdep1 t /  1 (2) characterize the transient response accurately for many circuit
I p1 (t )  (e  t /   1  e )
1  1 applications [5-6].
where Qdep1 is the deposited charge, τα1 is the collection time By using the theory and rules of the point admittance [5],
constant of the junction and τβ1 is the time constant for Y(s) of all nodes are obtained:

Y3 (s)  p1 / Rs3  ( p12Cs3  CL3  C3 )s  p13 R3Cs23s 2  p14 R32Cs33s3 (3a)

Y2 ( s)  p2 / Rs2  (Cc2  p22Cs2  CL2  C2 ) s  (Cc 2 Rs3 / p1  p23 R2Cs22 ) s 2 

(3b)
Cc22 ( p12Cs3  CL3  C3  Cc2 )
[  p24 R22Cs32 ]s 3
( p1 / Rs3 ) 2

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 Cc12 2 Cc12 ( p22Cs2  CL2  C2  Cc2 ) 3 (3c)
Y1 ( s)  (Cc1  CL1  C1 ) s  s  s
p2 / Rs2 ( p2 / Rs2 )2
Cc12
Y0 ( s)  1/ Rs1  Ceff s  [  R1 (Ceff  Cs1 )]s 2 
p2 / Rs2 (3d)
Cc2 ( p 2C  CL2  C2  Cc2 ) Cc12
[ 1 2 s2  2 R1 ( Ceff  C s1 )  R12 (Ceff  Cs1 )3 ]s 3
( p2 / Rs2 ) 2 p2 / Rs2
where, where,
1 , p  1 , Ceff  Cc1  CL1  C1  Cs1
p1  C2 =Cc1+ p22 Cs2+CL2+C2
1  R3 / Rs3 2
1  R2 / Rs2

C3* =C1+CL1
By using Y0(s), the equivalent circuit can be simplified as
shown in Fig.4 (a). Based on nodal analysis method, the Ceff3  Cc2  CL3  C3  Cs3
voltage at node 0 can be achieved as:
Rs1 b1  R2* (C2  Cc2 )  R2* (Cc2  C3* )
V0 ( s)  I p1 ( s) (4)
1  sRs1Ceff
0 b2  R2* R2* (C3*C2  C3*Cc2  C2Cc2 )
V0 Cc1 2
1
R1
Ceff By using the superposition theorem, the final SEC
Rs1 Ip1 C1 CL1 C2*
R2 * response voltage of the victim line is obtained as

（a） V3SEC (s)  V21 (s)  V23 (s) (8)

（b）

Fig.4 simplified circuit: (a) output at node 0; (b) output at node 2 For τβ much smaller than τα, the inverse Laplace
transform of SEC voltage is
In order to evaluate the crosstalk voltage of victim line
(node 2), the circuit shown in Fig.3 is simplified as shown in V3-SEC (t )  k11et / 1  k12et /( Rs1Ceff )  k13e t / 1  k14e t / 2 
Fig.4 (b) by using Y2(s), where, R2* =Rs2/p2, k31et / 3  k32et /( Rs3Ceff3 )  k33et / 3  k34e t / 4
C =Cc2+ p Cs2+CL2+C2. Based on the voltage distribution law,
*
2
2
2

the output voltage at node 2 can be achieved as: (9)

sR2*Cc1 sR2*Cc1 Based on the use of Taylor series expansion theorem and
V21 ( s)  V ( s )  V0 (s ) (5)
1
1  sR2* (C2*  Cc1 ) 1  a1s  a2 s 2 derivative [5], the noise peak voltage and pulse width of SEC
where, can be analytically presented, respectively.
C* =C1+CL1, a1  R (C  Cc1 )  R1 (Cc1  C )
* * * ,
1 2 2 1 IV. VERIFICATION AND ANALYSIS
a2  R R (C C  C Cc1  Cc1C2* ) .
*
2 1
*
1
*
2
*
1
The SEC waveforms from SPICE and the proposed
Replace (4) into (5), we can obtain model are compared, shown in Fig.5. The following
*
sR Cc1 Rs1 (6) parameters are set. The type of the line is intermediate in
V21 ( s)  2
I p1 ( s)
1  a1s  a2 s 1  sRs1Ceff
2
32nm, and its length is 500 μm. Each line is divided into 30
segments. The load capacitances are set to 0.5fF. The
By the similar calculation way, the response voltage of
equivalent resistances and capacitances for the driving
victim 2 only under the process of aggressor 3 can be
inverters are 14.5kΩ and 8fF, 20kΩ and 1fF, 10kΩ and 5fF,
achieved as
respectively. The parameter of the transient current source is
sR2*Cc2 Rs3 (7)
V (s) 
2
3
I p 3 (s) set as τα=250ps, τβ=10ps. The deposited charges for the first
1+b1s  b2 s 2 1  sRs3Ceff3
and third aggressors are 14.4fC and 9.6fC, respectively. The

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simulation results show that the SEC waveform from the
proposed model is very good in agreement with SPICE circuit. 180

160
The noise peak voltage and the pulse width match the SPICE
140
results very well. 120

Number of cases
100
We have tested the presented model using over 1000
80
randomly generated cases having 3-lines system, where the 60

second line is victim and the others are aggressors. In those 40

test circuits, the parameter ranges are as follows. The 20

0
self-resistance of each line is varied from 10Ω up to 10kΩ. -30 -20 -10 0
Relative error (%)
10 20 30

The self-capacitance and coupled-capacitance of each line are

varied from 10fF up to 5000fF, from 10fF up to 3000fF, Fig.6 Histogram of noise peak error from the model

respectively. The number of the segments for each line is 30.

TABLE I MODEL ERRORS IN SEC NOISE PEAK ON 1000 RANDOM
The deposited charges are set in the range 24 fC-200 fC.
CASES
9 Error Range SEC peak voltage
model
8 SPICE
Within ±5% 55.8%
7

6
Within ±10% 85.4%
Within ±15% 94.6%
SEC voltage (mV)

4
Average error 5.52%
3

2
Max error 28.7%
1
In order to analyze the effect of the parameters of the
0

-1
lines on the accuracy of predicting SEC noise voltage by the
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Time (ns) proposed model, the relevance between those parameters and
Fig.5 SEC waveform from SPICE and model. the prediction error is studied through using grey theory [15].
For convenient calculation, the analyzed circuit is shown in
Fig.6 shows the histogram evaluation error of SEC peak Fig.3, where the first line is only aggressor and the second
voltage for 1000 random circuits. For most of the cases, the line is victim. The varying parameters include the
relative error stays less than 20%. The percentage of nets that self-resistance, self-capacitance and coupled-capacitance of
fall into the given error ranges is given in Table I. For SEC each line. The other parameters are fixed. The number of the
noise peak voltage, the error of 85.4% of cases is less than tested cases is 100. The relative error between the proposed
10%, and average error is 5.52%. On the other hand, around model and SPICE is tested. By using grey theory, the
95% of all tested cases have errors less than 15% in our correlation of each parameter about the relative error can be
proposed model. obtained, shown in Table II. It indicates that the accuracy for
predicting SEC peak voltage by the presented model is
remarkably influenced by the parameters C1(self-capacitance
of the first line), C3(self-capacitance of the third line), and
R1(self-resistance of the first line).
TABLE II CORRELATION OF PARAMETERS OF LINES TO ERROR

Parameters R1 R2 R3 C1 C2 C3 Cc1 Cc2

Correlation 0.8459 0.6255 0.5803 0.9996 0.7134 0.9772 0.7138 0.5942

Rank 3 6 8 1 5 2 4 7

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parameters of the lines and the prediction accuracy of the 2019.

model is performed. These results validate that the proposed

model is accurate and efficient.

ACKNOWLEDGMENTS

This work was supported by the National Natural

Science Foundation of China (Grant No. 11975311,
11405270)

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