Unit-II

TIMERS & PHASE LOCKED LOOPS

Topics: Introduction to 555 timer, functional diagram, Monostable and Astable operations and applications,
Schmitt Trigger; PLL - introduction, block schematic, principles and description of individual blocks, 565
PLL, VCO

Introduction:IC555 is called timer and IC565 is called PLL. IC 555 is a stable device that it has to provide
necessary time delay and oscillations. IC 555 is designed by Stigmatic Corporation named as SE/NE 555
and is available in two packages.
1. 8 pin circular (or) To-99 package
2. 8 pin MINDIP (or) 14 pin DIP

Pin configuration of IC 555:

Applications:

IC555 used as square and linear ramp generators. Astablemonostablemultivibrator, burglar alarms, voltage
monitoring systems, traffic light control, pulse width modulation, FSK modulator, missing pulse detector
etc.

*** for 555IC, power supply range Vcc is +5V to +18V and drives maximum output current of 200mA.

*** IC555 is compatible with both TTL and COMS logic.

*** IC555 provide time delay range from µsec to few hours.

***IC 556 internally contains two 555IC and it is available as a 14-PIN package.

***counter timer designated by Exar’s XR2240. It contains one 555IC plus a programmable binary counter,
XR2240 provides time delay ranges from µsec to few days.
Functional diagram of IC 555:

IC 555 uses a voltage divider biasing network with the help of three 5Kohm resistors and power supply
1 2
Vcc. Tis type of arrangement makes two threshold voltages 3 𝑉𝑐𝑐 , 3 𝑉𝑐𝑐 to (+,-) input terminals of lower and
1 2
upper comparators. Hence the two voltage levels 3 𝑉𝑐𝑐 and 𝑉 are determine the timing cycle of IC555.It is
3 𝑐𝑐
also possible to adjust timing cycle electronically by just applying a modulation input voltage to the control
terminal as shown in fig. if the control voltage is not required, the manufacturers of IC suggested to
connect 0.01µF capacitor in between control input terminal (5) and ground terminal(1), to reject ripples
from power supply and bypass noise.

Case i: in standby state Q’=0 , which makes output low .

Case ii: by applying –ve triggering pulses to the inverting terminals of LC, when triggering input crosses
1
below 3 𝑉𝑐𝑐 , LC is high which makes R=1, S=0,Q=0,Q’=1 output is high.

2
Case iii: when threshold voltage at pin 6 of +ve input terminal of UC crosses over 3 𝑉𝑐𝑐 , UC high, R=0,
S=1, Q=1, Q’=0, out put is low .A reset pin provides interruption to timing device when the reset pulse is
applied all the function inside 555IC are set to zero.

IC555 as a monostablemultivibrator:IC555 can be used as monostablemultivibrator the circuit diagram and

its functional diagram is as shown in bellow fig.

Pin diagram of a monostablemultivinrator

 Functional Diagram of amonostablemultivinrator Input and output wave forms of amonostablemultivinrator

Case i: in stability state R=1,S=0,Q’=1,Q=0 R=1, S=0

Output –LOW, Q1-ON Q=0 Q’=0

The voltage across capacitor, Vc=0V Output-LOW, Q1-ON

Case ii: when applying triggering pulse, when the When a reset pulse is applied, it makes
1 transistor Q1 to ON. Thus the voltage across
triggering input crosses bellow 3 𝑉𝐶𝐶
capacitor is 0V and output is LOW. Here the
LC-HIGH,S=1,R=0,Q=1,Q’=0 output of transistor Q2 is directly connected to
base of transistor Q1 there output of flip flop to
Output is HIGH avoid propagation delay of the flip flop.
Q1 is OFF From the above graph it is observed that
Now transistor Q1 acts as open circuit and S/C during timing cycle of M.M.V even an additional
across timing capacitor, C is released and the triggering pulse is to be applied, the output
capacitor starts charging from 0V through remains in its previous state until the timing cycle
resistor, R with a time constant RC towards +VCC is to be over.

case iii: when voltage across capacitor is slightly To change the output state to timing cycle of
2 M.M.V a reset pulse is to be applied as shown.
grater than or equal to 3 𝑉𝐶𝐶 UC-HIGH
After applying reset pulse, the output remains at
0v until the next triggering pulse is to be applied.
Modified monostablemultivibrator:

Some times a M.M.V miss triggers to the +ve edges of the triggering pulse. To prevent this resistor
R1=10Kohm and capacitor is to be used in M.M.V circuit along with a diode as shown in bellow fig.

The output of RC network comprises of both –ve and +ve spikes and the amp of +ve spikes is restricted to
0.7v with the help of diode. The graphical representation of timing cycle, T of monostablemultivibrtor for
different values of R and C as shown in the fig.

Expression for timing cycle T of M.M.V:

The voltage across capacitor, VC is given by

−𝑡
Vc = Vcc(1- 𝑒 𝑅𝐶 )….(1)
2
When t= T, VC = 3Vcc……(2)

From (1) and (2)

−𝑡
2
Vcc= Vcc(1- 𝑒 𝑅𝐶 )
3

−𝑡
1
𝑒 𝑅𝐶 = 3

−𝑡 1
= ln3
𝑅𝐶

𝑡
= ln 3
𝑅𝐶

T = RC ln 3, there fore

T= 1.1 RC

There fore the time constant of monostablemultivibrator is T= 1.1 RC

Astablemultivibrator:Astable multi vibrator does not require any triggering pulses.

Here the triggering resistor R in

monostablemultivibrator circuit is split into two
resistors Ra and Rb the functional diagram
representation of astablemultivibrator is

When Vcc power supply is connected, the timing capacitor C gets changes through resistors RA and RB towards VCC with time
constant (Ra+Rb)C .
2
Case i: when the voltage across capacitor is just greater or equal to 3 𝑉𝐶𝐶 , the UC –high, it makes R=1,S=0,Q=0,Q’=1. This
Q’=1 makes the output low and transistor Q1 on .the Q1 is replaced with short circuit. now the capacitor start discharging
through resistor Rbtowords ground potential with time constant RbC.
1
Case ii: however when voltage across capacitor is slightly less than or equal to 3 𝑉𝐶𝐶 , LC-HIGH makes S=1,R=0,Q=1,Q’=0.
This Q’=0 makes the output high and transistor Q1-off. Now transistor Q1 is replaced with open circuit and capacitor C starts
charging towards +Vcc through resistors Ra and Rb with time constant (Ra+Rb)C. thus the voltage across the capacitor in astable
1 2
operator always swings between 3 𝑉𝐶𝐶 and 3 𝑉𝐶𝐶 .

Expression for timming cycle of astablemultivibrtor:

Let ts be the time taken by the capacitor to charge from thigh=t1-t2 = 0.69RC
2
0 to 𝑉𝐶𝐶 ,ThenVc is given by thigh=t1-t2 = 0.69(Ra+Rb)C
3
−𝑡 let Tlow be the time taken by the capacitor to discharge from
Vc= VCC (1 - 𝑒 𝑅𝐶 )…..(1) 2/3 VCC to 1/3 VCC. Then voltage across capacitor is
−𝑡 −𝑡
2 2 1
At t=t1, Vc =3 𝑉𝐶𝐶 = Vcc( 1 - 𝑒 𝑅𝐶 ) Vc = 𝑉𝐶𝐶 𝑒 𝑅𝐶 at t = Tlow ,Vc = Vcc
−𝑡
3 3
2 −𝑡2
1
=1-𝑒 𝑅𝐶 At t=t2, Vc=3Vcc=Vcc (1- 𝑒 𝑅𝐶 )
3
−𝑡 −𝑇𝑙𝑜𝑤
1 1 2
𝑒 𝑅𝐶 =3 Vcc = 3 𝑉𝐶𝐶 𝑒 𝑅𝐶
3
−𝑡 1 −𝑇𝑙𝑜𝑤
= ln
𝑅𝐶 3 1= 2 𝑒 𝑅𝐶
𝑡 𝑇𝑙𝑜𝑤
𝑅𝐶
= ln 3 𝑒 =2
𝑅𝐶
T = RC ln 3, there fore 𝑇𝑙𝑜𝑤
= ln 2
T= 1.1 RC 𝑅𝐶
Let t2 be the time period taken by the capacitor Tlow = RC ln2 where R=Rb, ln 2=0.69
1 Tlow= 0.69 Rb C
to charge from 0v to 3Vcc
−𝑡2
Timing cycle , T= Thigh+Tlow
1 T= 0.69(Ra+Rb)C+0.69 RbC
3
= 1 - 𝑒 𝑅𝐶
T= 0.69 (Ra+2Rb)C
𝑡2 = RC ln (1.5) 1 1 1.45
𝑡2 =0.405 RC Frequency , f= 𝑇 = 0.69 (Ra+2Rb)C= (Ra+2Rb)C
R=Ra+Rb
555 Timer as Schmitt Trigger:
A comparator is a device that compares two voltages and the outcome is the indication of whether one
voltage is higher than the other or not.Schmitt trigger, also called as Regenerative Comparator, compares
the input voltage to two reference voltages and produces an equivalent output. The output of a Schmitt
trigger is always a square or rectangular wave irrespective of the shape of the input. It is often used when
we need to do the following:

 Convert sine wave to square wave

 To clean up the noisy signals
 To convert slow edges (like in a triangular wave) into fast edges (like a square wave)

Schmitt can be constructed from a 555 timer. Some of the other function of the 555 timer, apart from the
timer operation, is to use the two internal comparators as independent units to form a Schmitt Trigger. The
general operation of the Schmitt trigger built from a 555 timer is inverting but the discussion will be for
non-inverting.

The pin diagram of Schmitt trigger with IC 555as shown in bellow fig., Pins 4 and 8 are connected to the
supply (VCC). The pins 2 and 6 are tied together and the input is given to this common point through a
capacitor C. this common point is supplied with an external bias voltage of VCC / 2 with the help of the
voltage divider circuit formed by the resistors R1 and R2.The important characteristic of the Schmitt trigger
is Hysteresis.

Pin diagram of Schmitt trigger with IC555

The output of the Schmitt trigger is high if the input voltage is greater than the upper threshold value and
the output of the Schmitt trigger is low if the input voltage is lower than the lower threshold value.The
output retains its value when the input is between the two threshold values. The usage of two threshold
values is called Hysteresis and the Schmitt trigger acts as a memory element (a bistablemultivibrator or a
flip-flop).

The threshold values in this case are 2/3 VCC and 1/3 VCC i.e. the upper comparator trips at 2/3 VCC and
the lower comparator trips at 1/3 VCC. The input voltage is compared to these threshold values by the
individual comparators and the flip-flop is SET or RESET accordingly. Based on this the output becomes
high or low.When a sine wave of amplitude greater than VCC / 6 is applied at the input, the flip-flop is set
and reset alternately for the positive cycle and the negative cycle. The output is a square wave and the
waveforms for input sine wave and output square wave are shown below.

Input and output of Schmitt trigger with IC555

The normal operation of the 555 timer as a Schmitt trigger is inverting in nature. When the trigger input,
which is same as the external input, falls below the threshold value of 1/3 VCC, the output of the lower
comparator goes high and the flip-flop is SET and the output at pin 3 goes high.Similarly, when the
threshold input, which is same as the external input, rises above the threshold value of 2/3 VCC, the output
of the upper comparator goes high and the flip-flop is RESET and the output at pin 3 goes low.
PHASE LOCKED LOOP (PLL):
Introduction to PLL:PLL is a control system which generates output signal in phase with the input signal.
The concept of Phase Locked Loops (PLL) first emerged in the early 1930’s.But the technology was not
developed as it now, the cost factor for developing this technology was very high. Since the advancement in
the field of integrated circuits, PLL has become one of the main building blocks in the electronics
technology. In present, the PLL is available as a single IC in the SE/NE560 series (560, 561, 562, 564, 565
and 567) to further reduce the buying cost,the discrete IC’s are used to construct a PLL.

PLL Applications:

 Frequency Modulation (FM) stereo decoders, FM Demodulation networks for FM operation.

 Frequency synthesis that provides multiple of a reference signal frequency.
 Used in motor speed controls, tracking filters.
 Used in frequency shift keying (FSK) decodes for demodulation carrier frequencies.

PLL Block Diagram:

The block diagram of a basic PLL is shown in the figure below. It is basically a flip flop consisting of a
phase detector, a low pass filter (LPF),and a Voltage Controlled Oscillator (VCO).

The input signal Vi with an input frequency fi is passed through a phase detector. A phase detector basically
a comparator which compares the input frequency fi with the feedback frequency fo .The phase detector
provides an output error voltage Ver= (fi- fo), which is a DC voltage. This DC voltage is then passed on to
an LPF. The LPF removes the high frequency noise and produces a steady DC level, V f= (fi-fo). Vf also
represents the dynamic characteristics of the PLL.The DC level is then passed on to a VCO. The output
frequency of the VCO (fo) is directly proportional to the input signal. Both the input frequency and output
frequency are compared and adjusted through feedback loops until the output frequency equals the input
frequency. Thus the PLL works in these stages – free-running, capture and phase lock.

As the name suggests, the free running stage refer to the stage when there is no input voltage
applied. As soon as the input frequency is applied the VCO starts to change and begin producing an output
frequency for comparison this stage is called the capture stage. The frequency comparison stops as soon as
the output frequency is adjusted to become equal to the input frequency. This stage is called the phase
locked state.Now let us study in detail about the various parts of a PLL – The phase detector, Low Pass
Filter and Voltage Controlled Oscillator.
 1. Phase Detector: This comparator circuit compares the input frequency and the VCO output
frequency and produces a dc voltage that is proportional to the phase difference between the two
frequencies. The phase detector used in PLL may be of analog or digital type. Even though most of
the monolithic PLL integrated circuits use analog phase detectors, the majority of discrete phase
detectors are of the digital type. One of the most commonly used analog phase detector is the double
balanced mixer circuit. Some of the common digital type phase detectors are

1.1 Exclusive OR Phase Detector

An exclusive OR phase detector is shown in the figure below.

It is obtained as a CMOS IC of type 4070. Both the frequencies are provided as an input to the EX OR
phase detector. Obeying the EX-OR concept the output becomes HIGH only if either of the inputs fi or fo
becomes HIGH. All other conditions will produce a LOW output. Let us consider a waveform where the
input frequency leads the output frequency by θ degrees. That is, fi and fo has a phase difference of θ
degrees. The dc output voltage of the comparator will be a function of the phase difference between its two
inputs.The figure shows the graph of DC output voltage as a function of the phase difference between fi and
fo. The output DC voltage is maximum when the phase detector is 180°.This type of phase detector is used
when both fi and fo are square waves.

1.2 Edge Triggered Phase Detector:Edge triggered phase detector is used when fi and fo are pulse
waveforms with less than 50% duty cycles. Two NOR Gate (CD4001) are cross-coupled to form an R-S
Flip Flop. The output of the phase detector changes it’s logic state by triggering of the R-S Flip Flop. That
is, the output of the phase detector changes its logic state on the positive edge of the input fi and fo. The
advantage of such a detector can be understood from the graph below. It is clear that the DC output voltage
is linear over 360°.
1.3 Monolithic Phase Detectors:The monolithic type phase detector uses a CMOS type 4044 IC ,Which is
highly advantages as the harmonic sensitivity and duty cycle problems are neglected and the circuit will be
respond only to the transition in the input signals. This is the most preferred phase detector in the critical
applications as the phase error and the output error voltage are independent of variations in the amplitude
and duty cycles of the input waveforms.
2. Low Pass Filter (LPF):

A Low Pass Filter (LPF) is used in Phase Locked Loops (PLL) to get rid of the high frequency components
in the output of the phase detector. It also removes the high frequency noise. All these features make the
LPF a critical part in PLL and helps control the dynamic characteristics of the whole circuit. The dynamic
characteristics include capture and lock ranges, bandwidth, and transient response. The lock range is the
tracking range where the range of frequencies of the PLL system follows the changes in the input
frequency. The capture range is the range in which the Phase Locker Loops attains the Phase Lock.When
the filter bandwidth is reduced, the response time increases .But this reduces the capture range. But it also
helps in reducing noise and in maintaining the locked loop through momentary losses of signal. Two types
of passive filter are used for the LPF circuit in a PLL. An amplifier is used also with LPF to obtain gain.

3. Voltage Controlled Oscillator (VCO):

The main function of the VCO is to generate an output frequency that is directly proportional to the input
voltage. The maximum frequency of the VCO is 500 KHz.This VCO provides simultaneous square wave
and triangular wave outputs as a function of the input voltage. The frequency of oscillation is determined by
the resistor R and capacitor C along with the voltage Vc applied to the control terminal .

Monolithic Phase Locked Loop :

PLL is now readily available as IC’s which were developed in the SE/NE 560 series. Some of the
commonly used ones are the SE/NE 560,561,562,564,565 and 567.The difference between each one of
them is in the different parameters like operating frequency range, power supply requirements, and
frequency and bandwidth ranges. Out of all the series the SE/NE 565 is the most famous. It is available as a
14-pin DIP and also as a 10-pin metal can package. The 14-pin DIP and its characteristics are given below.

Monolithic PLL Characteristics

 Operating frequency range: 0.001 Hz to 500 kHz.
 Operating voltage range: ± 6 to ± 12 V.
 Input impedance: 10 k Q typically.
 Output sink current: 1mA typically.
 Output source current: 10 m A typically.
 Drift in VCO centre frequency with temperature: 300 ppm/ °C typically.
 Drift in VCO centre frequency with supply voltage: 1.5 %/V maximum.
 Input level required for tracking: 10 mVrms minimum to 3 V peak-to-peak maximum.
 Bandwidth adjustment range: < ± 1 to > ± 60 %.
IC 565 PLL:

Block Diagram of PLL internal connection of 565 PLL

Above Figures shows the block diagram and internal connection of IC 565 phase locked loop. It consists of
Phase detector
Low pass filter
Voltage controlled oscillator
• Phase Detector :
1) The phase detector compares the input frequency fin with the feedback frequency fout.
2) The output of phase detector is proportional to the phase difference between fin and fout. If the two signal
which are applied as input to PLL differs in frequency or phase , an error voltage Ve is generated.
3) The phase detector is basically a multiplier and produces the sum (fin+fout) and difference (fin−fout)
components at its output.
4) The output of phase detector is then applied to the low pass filter, which removes the high- frequency
noise and produces a dc level.
• Low Pass Filter :
1) The function of low pass filter is to remove the high frequency components in the output of the phase
detector and to remove high frequency noise.
2) The low pass filter controls dynamic characteristics such as capture and lock ranges, bandwidth and
transient response.
3) Lock range is defined as the range of frequencies over which the PLL system follows the changes in the
input frequency fin, Lock range is also called as tracking range.
4) Capture range is the frequency range in which the PLL acquires phase lock. Capture range is always
smaller than Lock range.
5) The filter bandwidth is reduced, its response time increases. However, reduced bandwidth reduces the
capture range of the PLL. Reduced bandwidth helps to keep the loop in lock through momentary losses of
signal and also minimizes noise.
• Voltage Controlled Oscillator :
1) Third section of the PLL is the voltage controlled oscillator. The VCO generates an output frequency that
is directly proportional of its input voltage.
2) The VCO frequency is compared with the input frequencies and adjusted until it is equal to the input
frequencies.
PLL applications:

**Frequency Multiplier: In this application, the loop is broken and a frequency divider network is inserted
between VCO and phase detector as shown in figure below.

Since the output of frequency divider is locked to input frequency fin, the VCO is actually running at a
multiple of the input frequency. The desired amount of multiplication can be obtained by selecting a proper
÷N network.
∴Input to phase detector, fin=fo/N, fo=Nfin
First adjust the fin range and then adjust the free running frequency fo of the VCO by means of R1 and C1.
Consider the following example shown below. Between pin no.4 and 5 the loop is broken i.e. ÷N network is
inserted. In this case we have connected IC 7490 as ÷5 network. The output of VCO at pin no. 4 is not
sufficient to drive IC so a transistor is used in-between to increase the drive. Transistor is in CE
configuration so there is current gain at collector to drive IC. After ÷5 network, the frequency is applied to
phase detector.

VCO frequency can be varied with the help of R1 (consists of 20kΩ pot and 2kΩ resistor) and C1.

f(Omin )=0.3/(R1max ) C1 )=0.3/(22kΩ×0.01μf )=1.3636kHz

f(Omax )=0.3/(R1min C1 )=0.3/(2kΩ×0.01μf )=15kHz

Thus the output frequency can be varied from 1.3636 kHz to 15 kHz with a single capacitor. The
input waveform can be square wave (pin no.3) or sine wave (pin no. 2). A small capacitor, typically 1000pf
is connected between pin no. 7 and 8 to eliminate possible oscillations. Also capacitor C2 should be large
enough to stabilize the VCO frequency.
**Frequency Translator (frequency Synthesizer):

In some applications we want to shift the input frequency (fin) by a small amount and not by
multiple numbers. This shift is called as frequency translation (fT). It is useful in communication
systems.While transmission, a carrier frequency is used which is highly stable. We can generate carrier
frequency from oscillator. For this purpose a quartz crystal oscillator is required.As crystal oscillators have
some temperature coefficient, we get some thermal drift in frequency. To avoidthis frequency change due
to temperature, we have to keep temperature constant. This method is very costly.If we want to use many
carrier frequencies then it is impossible to use separate crystal for each carrier frequency. So by using PLL
we can generate different carrier frequencies shifted by small amount from reference frequency.A stable
frequency generated by crystal is called reference frequency and numbers of other frequencies are
generated from PLL. Since the PLL IC is available in low cost, the system is not costly. The following
figure shows the block diagram of frequency translator.

Externally multiplier (or mixer) and LPF are added. Multiplier is basically a non-linear circuit. Input for
multipliers are fref and VCO frequency fo.Let fref is 1 MHz and we want to shift it to a value 1.2 MHz So
there is a frequency translation of 0.2 MHz.At the output of multiplier, we have number of frequency
components including addition and difference frequencies i.e. (fo ± fref). This frequency is passed through
LPF. The output of LPF is the difference signal i.e. (fo-fref).The external frequency (translation frequency) is
selected such that it is equal to translation required. In the above example fT = 0.2 MHz.

Thus to achieve the locked condition, the two input frequencies for phase detector must be equal.
∴fo-fref=fT
∴fo=fT+fref
∴fo=(0.2+1)MHz
∴fo=1.2 MHz

Thus the reference frequency is shifted from 1 MHz to 1.2 MHz and when the locked condition is
achieved, this output frequency is highly stable i.e. translated frequency is also stable. Thus by using PLL,
from a single reference frequency we can generate number of stable frequencies by this method of
translation.The instrumentation which generates number of frequencies from single reference frequency is
called frequency synthesizer.

** FM Detector:

There is shift in carrier frequency about the mean value according to modulating signal at FM
transmitter. The deviation or shift in carrier frequency from centre value is converted to low voltage or high
voltage, is demodulation.Assume the loop is in locked condition, so VCO frequency and input frequency is
same. FM signal is applied as input to phase detector. Phase detector produce error voltage proportional to
frequency shift. This signal is passed through LPF and amplifier to give controlled voltage. Thus controlled
voltage is proportional to change in frequency. As input frequency is shifted up or down, VCO voltage also
varies accordingly. FM input is applied to pin no. 2 which is input to phase detector internally. Pin no. 4 and
5 are shorted externally to complete the loop. Initially loop is locked onto carrier frequency. As carrier
frequency changes we get demodulated output at pin no.7. R1 and C1 connected externally, determine the
oscillator frequency. An external capacitor of 1000pf is connected for stability of internal circuit.Range of
R1 is from 2kΩ to 20kΩ (typically=4kΩ). Direct coupling can be used at input if the dc resistance as seen
from pin no. 2 and pin no. 3 are equal and if there is no dc voltage difference these two pins. If resistance is
connected between pin no.6 and pin no.7, the gain of output stage can be reduced. The lock range is thus
decreased with little change in VCO free running frequency

**FSK Demodulator:
Two frequencies are used instead of two voltage levels while transmitting signal called FSK
modulation. At receiver from these two frequencies we can detect the two voltage levels called FSK
demodulation. In computer peripherals and radio communication binary data or code is transmitted by
means of a carrier frequency which is shifted between two predetermined frequencies. The frequencies
corresponding to logic 1 and logic 0 states are commonly called as mark and space frequencies. Several
standards are used to set the mark and space frequencies. For e.g.when transmitting teletypewriter
information using a modem system 1070/1270 Hz pair represents the original signal and the other pair
2025/2225Hz is used as answering unit.The difference between FSK signals of 1070 and 1270 Hz is 200 Hz
and between 2025 and 2225 Hz is also 200 Hz. This is called as frequency shift. Generally binary data is
transmitted at the rate of 150 Hz. At receiver end we have to generate two different voltage levels (high &
low). The following figure shows the PLL IC 565 as FSK demodulator.
Pin no.4 and pin no.5 shorted externally to get VCO output to phase detector. At pin no.7 the demodulated
output is available. This demodulated output is further passed through a 3 identical sections of ladder RC
LPF. At the output of 3 LPF sections we get almost a dc voltage. The following figure shows the PLL IC
565 as FSK demodulator.

This dc voltage is applied to inverting terminal of open loop comparator. At pin no.6 reference dc voltage is
present, this is second input to comparator i.e. this is the triggering point for comparator. At pin no.6 we
may use RC LPF to get pure dc output.Corresponding to 1070 Hz frequency, we get one signal VC1 at
output of 3 RC LPF sections which is connected to comparator. When input frequency is shifted to 1270
Hz, we have another voltage Vc2. The triggering voltage of the comparator is adjusted such that it lies
between Vc1 and Vc2. When Vc1 is received at output which is less than VT, then output of comparator is
+Vsat. When Vc2 is received at output is more than VT, output of comparator changes to –Vsat.Thus the
corresponding two frequencies are converted into two voltage levels +Vsatand –Vsat (high & low) at
output; which is nothing but FSK demodulation.

**AM Detector:The PLL can be used as an AM detector for demodulating the amplitude modulated
signals.The following figure shows AM detection using PLL.
The equation of AM signal is, E[1+m cosωmt]cosωct
where m→Modulation index (0 to 1)
ωm=2πfm→Modulating frequency
ωc=2πfc→Carrier frequency
Amplitude of VCO is constant =Ecosωct
These are the two inputs to the multiplier block. The output is the product of the two inputs as calculated
below.
=E[1+m cosωmt]cosωct [E cosωct]
=E^2 [1+m cosωmt] cos^2 ωct
=E^2 [1+m cosωmt][(1+cos 2ωct)/2]
Where cos2ωct →Second harmonics of carrier frequency
When this output signal is passed through LPF, second harmonic is removed.