Computer Architecture and Design CSE 211

SET A
CA3
UID_____________ Roll Number_____________ Section_________________

1.The number of micro-operations required to fetch an 1.The operand is inside the instruction
instruction from memory is __________ 2.The address of the operand is inside the instruction
3.The register containing the address of the operand is specified
2. Consider a 5 stage pipeline with IF, ID, EX, MEM and WB inside the instruction
latencies 8, 6, 4, 6 and 4 respectively (in ns). If IF stage is made 4.The location of the operand is implicit
50% faster, the percentage it will improve the performance CPU a) 1 b) 2 c)3 d) 4
is __________. 11. Which of the following addressing modes permits relocation
a)12.2 b)13.2 c)14.3 d)15.3 without any change whatsoever in the code?
3. A certain architecture supports indirect, direct and register a) Indirect addressing b) Indexed addressing c) Base register
addressing modes for use in identifying operands for arithmetic addressing d) PC relative addressing
instructions. Which of the following cannot be achieved with a
single instruction? 12. Which one is correct
(a) specifying a register number in the instruction such that the 1.The aim of pipelined architecture is to execute one complete
register contains the value of an operand that will be used by the instruction in one clock cycle.
operation. 2.In other words, the aim of pipelining is to maintain CPI ≅ 1.
(b) specifying a register number in the instruction such that the 3.Practically, it is not possible to achieve CPI ≅ 1 due to delays that
register will serve as the destination for the operation’s output. get introduced due to registers.
(c) specifying an operand value in the instruction such that the a) 1,2 b)2,3 c)3,1
value will be used by the operation. 13. Which one is correct
(d) specifying a memory location in the instruction such that the 1.The maximum speed up that can be achieved is always equal to
memory location contains the value of an operand that will be the number of stages.
used by the operation. 2.Practically, efficiency is always less than 100%.
4. Consider the following statements. 3.Therefore speed up is always greater than number of stages in
pipelined architecture
S1: The RISC processor has CPI always 1. a) 1,2 b)2,3 c)3,1
S2: In horizontal instruction control signals are always in encoded 14. In case only one instruction has to be executed, then-
form.
S3: In vertical instruction control signals are always in encoded
1: Non-pipelined execution gives better performance than
form.
S4: In terms of speed vertical instruction is slower than horizontal pipelined execution.
instruction. 2: This is because delays are introduced due to registers in
Which of the above statements are true? pipelined architecture
a) S1,S2,S3 b)S1,S3,S4 c)S2,S3,S4 d)none 1 is true and 2 is the correct explanation
5. Match List-I with List-II and select the correct answer using the 1 is false but 2 is the correct explanation
codes given below the lists: 1 is false and 2 is also false.
List-I List-II 15. High efficiency of pipelined processor is achieved when-
A. Pointer 1. Indirect addressing mode
B. Position independent code 2. Immediate addressing mode 1.All the stages are of different duration.
C. Constant operand 3. Relative addressing mode 2.There are no conditional branch instructions.
a) 3,2,1 b)1,3 ,2 c) 2,3,1 3.There are no interrupts.
6. In which of the following addressing mode, the content of the 4.There are no register and memory conflicts
program counter is added to the address part of the instruction a) 1,2,3 b)2,3,4 c)3,4,1
to get the effective address? 16.Consider the 5 stage pipeline {IF,ID,EX,MA,WB} with clock
a) Implied mode b) Relative mode c) Register mode cycles of Intruction1 as {2,3,4,2,1} at which clock does MA stage
7. A pipelined CPU has a speed up of 4.5 over non-pipelined CPU completes execution._________
and has an efficiency of 90%. How many stages are there? 17. A pipelined CPU has a speed up of 4.5 over non-pipelined CPU
a) 4 b) 5 c) 6 d)7 and has an efficiency of 90%. How many stages are there?
8.Which of the following keeps track of instruction execution (a) 5 (b) 4 (c) 6
sequence? (d) 3
a) Accumulator b Program Counter c) Stack Pointer d) all 18. A 2 way set associative cache is 256 Kbytes in size. What is the
of the mentioned number of sets if block size is 16 Bytes?
9. A 5 stage pipeline has the stages IF, ID, OF, PO, WB (Assume (a) 4096 (b) 8192 (c) 1024 (d) 16,384
that there are no separate data and instruction caches). For the 19. A cache is having 60% hit ratio for read operation. Cache
program below, what is/are the hazard(s) possible? access time is 30 ns and main memory access time is 100 ns, 50%
MOV R1,A; R1←μ[A] operations are read operation.
MOV R2,A; R2←μ[B] What will be the average access time for read operation?
ADD R1,R2; R1←R1+R2 (a) 50 ns (b) 58 ns (c) 100 ns (d) 70 ns
MOV X,R1; μ[x]←R1 20.A CPU has 30 bit memory address and 512Kbyte cache
a) Data Hazard b) Control hazard c) Structural hazard organized into 8-way set associative cache and block size is 32
10. In the absolute addressing mode, which one is correct Bytes.
What is the number of bits required in TAG for comparator (a) Direct (b) Indirect (c) Relative (d) Indexed Mode
matching?
(a) 16 (b) 11 (c) 17 (d) 14 27. Which set of instruction transfers the memory word specified
21. More than one word is put in one cache block to by the effective address to AC or Load to AC?
(a) Exploit temporal locality references in a program (a) DR←M[AR]AC←AC+DR,E←COUT,SC←O
(b) Exploit spatial locality references in a program (b) DR←M[AR]AC←DR,SC←O
(c) Reduce miss penalty (c) M[AR]←AC,SC←O
(d) All of these (d) DR←M[AR]AC←AC∧DR,SC←O
22. An instruction pipeline consists of 4 stages fetch(F), 28. A program consists of four major types of instructions. The
decode(D), execute(E) and write(W). Different instruction spent instruction mix and the CPI for each instruction type are given in
different number of clock cycles. the following table.

If the clock frequency of the processor is 400 MHz, what is the

The value in the box represents clock cycles taken by instructions average CPI of the processor?
in different states. (a) 3.75 (b) 2.87
At what clock cycle, instruction I3, will complete its decoding? (c) 1.87 (d) 1.54
(a) 6th clock cycle (b) 7th clock cycle 29. Consider a 16-bit processor in which the following one
(c) 12th clock cycle (d) 13th clock cycle address instruction is loaded in main memory.

23. How many cycles are required for a 100 MHz processor to
execute a program which requires 5 seconds of CPU time?
(a) 109 cycles (b) 50 × 107 cycles
(c) 108 cycles (d) 50 cycles

24. Main difference between CISC and RISC is

(a) RISC has few instructions (b) RISC has few addressing modes
(c) CISC is having fewer registers (d) Both (a) & (b)
The effective address using PC relative addressing mode when
25. Which of following may not definitely occur in an instruction processor is executing an instruction at location 300 is ______.
cycle?
(i) Fetch cycle 30.Consider a 5 stage pipeline with IF, ID, EX, MEM and WB
(ii) Execution cycle latencies 8, 6, 4, 6 and 4 respectively (in ns). If IF stage is made
(iii) Indirect cycle 50% faster, the percentage it will improve the performance CPU is
(a) (i) only (b) (i) and (ii) (c) (iii) only (d) (ii) and (iii) __________.

26. Most relevant addressing mode to write position independent a)14.3 b)15.3 c) 16.3 d)17.3
code is

Note: Fill your responses here. Over Written option will be discarded.
1) 4 2) c 3)c 4) 5)
6) 7) 8) 9) 10)
11) 12) 13) 14) 15)
16) 17) 18) 19)d 20)d
21)b 22) 23)b 24)d 25)c
26)c 27)b 28)c 29)802 30)a
 Computer Architecture and Design CSE211
SET B
CA3
UID________ Roll Number_____________ Section_________
Find number of clock cycles needed to execute the above 4
1). High efficiency of pipelined processor is achieved when. instructions.
1.All the stages are of different duration. (a) 12 (b) 13 (c) 14 (d) 15
2.There are no conditional branch instructions. 13. Consider the following statements:
3.There are no interrupts. 1. Time taken for a single instruction on a pipelined CPU is less
4.There are no register and memory conflicts than or equal to time taken on a
a) 1,2,3 b)2,3,4 c)3,4,1 non-pipelined (identical) CPU.
2. Which one is correct 2. In a uniform delay pipeline execution time for a single
1.The maximum speed up that can be achieved is always equal to instruction is equal to the execution
the number of stages. time in non-pipelined processor. (Assume no buffer delay)
2.Practically, efficiency is always less than 100%. Which of the above statement(s) is correct?
3.Therefore speed up is always greater than number of stages in (a) Only 1 (b) Only 2 (c) Both 1 and 2 (d)
pipelined architecture Neither 1 nor 2
a) 1,2 b)2,3 c)3,1 14. Compared to RISC processors, CISC processors contain
3.Which of the following addressing modes permits relocation _________.
without any change whatsoever in the code? (a) More registers and smaller instruction set
a)Indirect addressing b) Indexed addressing (b) Larger instruction set and less registers
c) Base register addressing d) PC relative addressing (c) Less registers and smaller instruction set
4.Which of the following keeps track of instruction execution (d) More transistor elements
sequence? 15.An instruction pipeline consist of 4 stages IF, ID, EX and
a) Accumulator b Program Counter c) Stack WB. Four instructions need these stages for different number
Pointer d) all of the mentioned of cycles as shown by the table below
5. A 5 stage pipeline has the stages IF, ID, OF, PO, WB
(Assume that there are no separate data and instruction
caches). For the program below, what is/are the hazard(s)
possible?
MOV R1,A; R1←μ[A]
MOV R2,A; R2←μ[B]
ADD R1,R2; R1←R1+R2
MOV X,R1; μ[x]←R1
a) Data Hazard b) Control hazard c) Structural hazard
6.Consider a 5 stage pipeline with IF, ID, EX, MEM and WB
latencies 8, 6, 4, 6 and 4 respectively (in ns). If IF stage is made
50% faster, the percentage it will improve the performance Find number of clock cycles needed to execute the above 4
CPU is __________. instructions.
a)12.2 b)13.2 c)14.3 d)15.3 (a) 12 (b) 13 (c) 14 (d) 15
7.Consider the following statements.
S1: The RISC processor has CPI always 1. 16. Which set of instruction transfers the memory word
S2: In horizontal instruction control signals are always in encoded specified by the effective address to AC or Load to AC?
form. (a) DR←M[AR]AC←AC+DR,E←COUT,SC←O
S3: In vertical instruction control signals are always in encoded (b) DR←M[AR]AC←DR,SC←O
form. (c) M[AR]←AC,SC←O
S4: In terms of speed vertical instruction is slower than horizontal (d) DR←M[AR]AC←AC∧DR,SC←O
instruction. 17. Main difference between CISC and RISC is
Which of the above statements are true? (a) RISC has few instructions (b) RISC has few addressing modes
S1, S2, S3 b) S1, S3, S4 c) S2, S3, S4 d) none (c) CISC is having fewer registers (d) Both (a) & (b)
8).Consider a pipeline having 4 phases with duration 60, 50, 90 18. A program consists of four major types of instructions. The
and 80 ns. Given latch delay is 10 ns. Calculate pipeline/cycle instruction mix and the CPI for each instruction type are given in
time is ____. the following table.
A) 200 b)300 c)100 d)50
9.For the same question number 8, Non pipeline Execution
time is_________
10.For the same question 8, Speed up is _______
11. Consider a 5 stage instruction pipeline having latencies (in
ns) 1, 2, 3, 4 and 5 respectively. Find average CPI of non-
pipeline CPU when speed up achieved with respect to pipeline
is 4 (assume ideal case for pipelining)? If the clock frequency of the processor is 400 MHz, what is the
(a) 1.23 (b) 1.33 (c) 1.66 (d) 1.73 average CPI of the processor?
12. An instruction pipeline consist of 4 stages IF, ID, EX and (a) 3.75 (b) 2.87
WB. Four instructions need these stages for different number (c) 1.87 (d) 1.54
of cycles as shown below 19. How many cycles are required for a 100 MHz processor to
i1(1,2,1,1),i2(1,2,2,1),I3(2,1,3,2),I4(1,,3,2,1) execute a program which requires 5 seconds of CPU time?
(a) 109 cycles (b) 50 × 107 cycles
(c) 108 cycles (d) 50 cycles
20. In MESI protocol of Cache Coherence,I stands for
a) Increment b) Invalid c) Incidence d) None
20) Cache Miss and Cache hit are two opposite terms in Cache.If
cache hit rate is 80 %, then what will be cache miss rate______
21).Compulsory miss is_____
a) First Miss of cache b) Last miss of cache c) Second Miss of
cache d) None
22) S1: In temporal Locality of reference recently accessed data is
likely to be accessed again
S2: In spatial locality f reference nearby data is likely to be accessed.
a)Both are true b)S1 is ttrue S2 is false c)S2 is true S1 is False
d) Both are False.
23) S1. FIFO replacement replace oldest block first.
S2: LRU replace Recently used memory block.
Which one is correct.
a)S1, S2 b) S1 c) S2 d) None
24) S1:Update both main memory and cache is called write
through
S2:Update cache and later update main memory is write back.
A)S1 B) S2 c) S1,S2
25). Choose the correct option.
Higher associativity reduces conflict misses
But increases hardware complexity and access time
Common associativities are : 2-way, 4-way
a) S1,S2 b) S2,S3 c) S3,S1 d)S1,S2,S3
26) Which of the following is true?
(a) In write through protocol, cache location and main memory
location are updated
simultaneously.
(b) In write back protocol, cache location and main memory location
are updated simultaneously.
(c) Modified or dirty bits are used by write through protocol.
(d) None of these
27). To increase the speed of memory access in pipelining, we
make use of _______
a) Special memory locations b) Special purpose registers
c) Cache d) Buffers
28). The periods of time when the unit is idle is called as _____
a) Stalls b) Bubbles c) Hazards d) Both Stalls and Bubbles
29). The contention for the usage of a hardware device is called
______
a) Structural hazard b) Stalk c) Deadlock d) None
30). The situation wherein the data of operands are not available is
called ______
a) Data hazard b) Stock c) Deadlock d) Structural hazard

Note: Fill your responses here. Over Written

option will be discarded.
1) 4 2) c 3)c 4) 5) c
6) 7) 8) 9) 10)
11) 12) 13) 14) 15)
16) 17) 18) 19)d 20)
21)a 22)a 23)a 24)b 25)c
26)a 27)c 28) d 29)d 30) a
 Computer Architecture and Design CSE211
SET C
CA3
c) Reference bit
d) Flag bit
1). To increase the speed of memory access in pipelining, we
9) The approach where the memory contents are transferred
make use of _______
directly to the processor from the memory is called ______
a) Special memory locations b) Special purpose registers
c) Cache d) Buffers a) Read-later
b) Read-through
c) Early-start
2).Which one is correct
d) None of the mentioned
1.The aim of pipelined architecture is to execute one complete
10). The throughput of a super scalar processor is _______
instruction in one clock cycle.
a) less than 1
2.In other words, the aim of pipelining is to maintain CPI ≅ 1.
b) 1
3.Practically, it is not possible to achieve CPI ≅ 1 due to delays
c) More than 1
that get introduced due to registers.
d) Not Known
a) 1,2 b)2,3 c)3,1
10). In super-scalar mode, all the similar instructions are grouped
and executed together.
3).Which of the following is true?
a) True b) False
(a) In write through protocol, cache location and main memory
location are updated
11). Choose the correct option.
simultaneously.
Higher associativity reduces conflict misses
(b) In write back protocol, cache location and main memory location
But increases hardware complexity and access time
are updated simultaneously.
Common associativities are : 2-way, 4-way
(c) Modified or dirty bits are used by write through protocol.
a) S1,S2 b) S2,S3 c) S3,S1 d)S1,S2,S3
(d) None of these
12). A program consists of four major types of instructions. The
4).Cache Miss and Cache hit are two opposite terms in Cache.If
cache hit rate is 80 %, then what will be cache miss rate______ instruction mix and the CPI for each instruction type are given in
the following table.
5).The effectiveness of the cache memory is based on the property
of ________
a) Locality of reference b) Memory localisation
c) Memory size d) None of the mentioned

6).The temporal aspect of the locality of reference means ________

a) That the recently executed instruction won’t be executed soon
b) That the recently executed instruction is temporarily not If the clock frequency of the processor is 400 MHz, what is the
referenced average CPI of the processor?
c) That the recently executed instruction will be executed soon (a) 3.75 (b) 2.87 (c) 1.87 (d) 1.54
again
d) None of the mentioned 13).Main difference between CISC and RISC is
6). The spatial aspect of the locality of reference means ________ (a) RISC has few instructions (b) RISC has few addressing modes
a) That the recently executed instruction is executed again next (c) CISC is having fewer registers (d) Both (a) & (b)
b) That the recently executed won’t be executed again
c) That the instruction executed will be executed at a later time 14). Consider a pipeline having 4 phases with duration 60, 50,
d) That the instruction in close proximity of the instruction 90 and 80 ns. Given latch delay is 10 ns. Calculate
executed will be executed in future pipeline/cycle time is ____.
A) 200 b)300 c)100 d)50
7).The algorithm to remove and place new contents into the cache
is called _______ 15) An instruction pipeline consist of 4 stages IF, ID, EX and
a) Replacement algorithm WB. Four instructions need these stages for different number
b) Renewal algorithm of cycles as shown below
c) Updation I1(1,2,1,1),I2(1,2,2,1),I3(2,1,3,2),I4(1,,3,2,1)
8).The write-through procedure is used ________ Find number of clock cycles needed to execute the above 4
a) To write onto the memory directly instructions.
b) To write and read from memory simultaneously (a) 12 (b) 13 (c) 14 (d) 15
c) To write directly on the memory and the cache
simultaneously 16).Consider a pipeline having 4 phases with duration 60, 50,
90 and 80 ns. Given latch delay is 10 ns. Calculate
pipeline/cycle time is ____.
8. The bit used to signify that the cache location is updated is
A) 200 b)300 c)100 d)50
________
17).For the same question number 16, Non pipeline Execution
a) Dirty bit
time is_________
b) Update bit
18).For the same question 16, Speed up is _______ 29). In which of the following addressing mode, the content of the
19). Consider a 5 stage instruction pipeline having latencies (in program counter is added to the address part of the instruction
ns) 1, 2, 3, 4 and 5 respectively. Find average CPI of non- to get the effective address?
pipeline CPU when speed up achieved with respect to pipeline a) Implied mode b) Relative mode c) Register mode
is 4 (assume ideal case for pipelining)?
(a) 1.23 (b) 1.33 (c) 1.66 (d) 1.73 30). 30.Consider a 5 stage pipeline with IF, ID, EX, MEM and WB
latencies 8, 6, 4, 6 and 4 respectively (in ns). If IF stage is made
20).How many cycles are required for a 100 MHz processor to
50% faster, the percentage it will improve the performance CPU is
execute a program which requires 5 seconds of CPU time?
__________.
(a) 109 cycles (b) 50 × 107 cycles
(c) 108 cycles (d) 50 cycles. a) 14.3 b)15.3 c) 16.3 d)17.5

21)Which of following may not definitely occur in an instruction

cycle?
(i) Fetch cycle
(ii) Execution cycle
(iii) Indirect cycle
(a) (i) only (b) (i) and (ii) (c) (iii) only (d) (ii) and (iii)

22). An instruction pipeline consist of 4 stages IF, ID, EX and

WB. Four instructions need these stages for different number
of cycles as shown by the table below

Find number of clock cycles needed to execute the above 4

instructions.
(a) 12 (b) 13 (c) 14 (d) 15

23).More than one word is put in one cache block to

(a) Exploit temporal locality references in a program
(b) Exploit spatial locality references in a program
(c) Reduce miss penalty
(d) All of these

24). Which of the following addressing modes permits relocation

without any change whatsoever in the code?
a) Indirect addressing b) Indexed addressing c) Base register
addressing d) PC relative addressing
25). The CISC stands for ___________
a) Computer Instruction Set Compliment
b) Complete Instruction Set Compliment
c) Computer Indexed Set Components
d) Complex Instruction set computer.

26). The last on the hierarchy scale of memory devices is ______

a) Main memory
b) Secondary memory
c) TLB
d) Flash drives.

27). Cache Miss and Cache hit are two opposite terms in Cache.If
cache hit rate is 80 %, then what will be cache miss rate______

28). Which set of instruction transfers the memory word

specified by the effective address to AC or Load to AC?
(a) DR←M[AR]AC←AC+DR,E←COUT,SC←O
(b) DR←M[AR]AC←DR,SC←O
(c) M[AR]←AC,SC←O
(d) DR←M[AR]AC←AC∧DR,SC←O