Computer Organization & Architecture

Functional Components of a Computer

Computer: A computer is a combination of hardware and software resources which integrate together and provides
various functionalities to the user. Hardware are the physical components of a computer like the processor, memory
devices, monitor, keyboard etc. while software is the set of programs or instructions that are required by the hardware
resources to function properly.

There are a few basic components that aids the working-cycle of a computer i.e. the Input- Process- Output Cycle and
these are called as the functional components of a computer. It needs certain input, processes that input and produces
the desired output. The input unit takes the input, the central processing unit does the processing of data and the
output unit produces the output. The memory unit holds the data and instructions during the processing.

Digital Computer: A digital computer can be defined as a programmable machine which reads the binary data passed as
instructions, processes this binary data, and displays a calculated digital output. Therefore, Digital computers are those
that work on the digital data.

Details of Functional Components of a Digital Computer Computer:

Input Unit :The input unit consists of input devices that are attached to the computer. These devices take input and
convert it into binary language that the computer understands. Some of the common input devices are keyboard,
mouse, joystick, scanner etc.

Central Processing Unit (CPU) : Once the information is entered into the computer by the input device, the processor
processes it. The CPU is called the brain of the computer because it is the control center of the computer. It first fetches
instructions from memory and then interprets them so as to know what is to be done. If required, data is fetched from
memory or input device. Thereafter CPU executes or performs the required computation and then either stores the
output or displays on the output device. The CPU has three main components which are responsible for different
functions – Arithmetic Logic Unit (ALU), Control Unit (CU) and Memory registers.

Arithmetic and Logic Unit (ALU) : The ALU, as its name suggests performs mathematical calculations and takes logical
decisions. Arithmetic calculations include addition, subtraction, multiplication and division. Logical decisions involve
comparison of two data items to see which one is larger or smaller or equal.
 Control Unit : The Control unit coordinates and controls the data flow in and out of CPU and also controls all the
operations of ALU, memory registers and also input/output units. It is also responsible for carrying out all the
instructions stored in the program. It decodes the fetched instruction, interprets it and sends control signals to
input/output devices until the required operation is done properly by ALU and memory.

Memory Registers : A register is a temporary unit of memory in the CPU. These are used to store the data which is
directly used by the processor. Registers can be of different sizes(16 bit, 32 bit, 64 bit and so on) and each register inside
the CPU has a specific function like storing data, storing an instruction, storing address of a location in memory etc. The
user registers can be used by an assembly language programmer for storing operands, intermediate results etc.
Accumulator (ACC) is the main register in the ALU and contains one of the operands of an operation to be performed in
the ALU.

Memory : Memory attached to the CPU is used for storage of data and instructions and is called internal memory The
internal memory is divided into many storage locations, each of which can store data or instructions. Each memory
location is of the same size and has an address. With the help of the address, the computer can read any memory
location easily without having to search the entire memory. when a program is executed, it’s data is copied to the
internal memory and is stored in the memory till the end of the execution. The internal memory is also called the
Primary memory or Main memory. This memory is also called as RAM, i.e. Random Access Memory. The time of access
of data is independent of its location in memory, therefore this memory is also called Random Access memory (RAM).

Output Unit : The output unit consists of output devices that are attached with the computer. It converts the binary
data coming from CPU to human understandable form. The common output devices are monitor, printer, plotter etc.

Interconnection between Functional Components

A computer consists of input unit that takes input, a CPU that processes the input and an output unit that produces
output. All these devices communicate with each other through a common bus. A bus is a transmission path, made of a
set of conducting wires over which data or information in the form of electric signals, is passed from one component to
another in a computer. The bus can be of three types – Address bus, Data bus and Control Bus.

Following figure shows the connection of various functional components:

The address bus carries the address location of the data or instruction. The data bus carries data from one component to
another and the control bus carries the control signals. The system bus is the common communication path that carries
signals to/from CPU, main memory and input/output devices. The input/output devices communicate with the system
bus through the controller circuit which helps in managing various input/output devices attached to the computer.

BUS

 A bus is a set of electrical wires (lines) that connects the various hardware components of a computer system.
 It works as a communication pathway through which information flows from one hardware component to the
other hardware component.
 A bus that connects major components (CPU, memory and I/O devices) of a computer system is called as a
System Bus.

Why Do We Need Bus?

A computer system is made of different components such as memory, ALU, registers etc. Each component should be
able to communicate with other for proper execution of instructions and information flow. If we try to implement a
mesh topology among different components, it would be really expensive. So, we use a common component to connect
each necessary component i.e. BUS.

Components Of A System Bus

The system bus consists of three major components

1. Data Bus
2. Address Bus
3. Control Bus
 1) Data Bus

 As the name suggests, data bus is used for transmitting the data / instruction from CPU to memory/IO and vice-
versa.
 It is bi-directional.

2) Control Bus

 As the name suggests, control bus is used to transfer the control and timing signals from one component to the
other component.
 The CPU uses control bus to communicate with the devices that are connected to the computer system.
 The CPU transmits different types of control signals to the system components.
 It is bi-directional

What Are Control & Timing Signals?

 Control signals are generated in the control unit of CPU.

 Timing signals are used to synchronize the memory and I/O operations with a CPU clock.
 Typical control signals hold by control bus
 Memory read – Data from memory address location to be placed on data bus.
 Memory write – Data from data bus to be placed on memory address location. I/O Read – Data from I/O address
location to be placed on data bus.
 I/O Write – Data from data bus to be placed on I/O address location.
 Other control signals hold by control bus are interrupt, interrupt acknowledge, bus request, bus grant and several
others.

The type of action taking place on the system bus is indicated by these control signals.

Example

When CPU wants to read or write data, it sends the memory read or memory write control signal on the control bus to
perform the memory read or write operation from the main memory. Similarly, when the processor wants to read from an
I/O device, it generates the I/O read signal.

3) Address Bus

 As the name suggests, address bus is used to carry address from CPU to memory/IO devices.
 It is used to identify the particular location in memory.
 It carries the source or destination address of data i.e. where to store or from where to retrieve the data.
 It is uni-directional.
Example

When CPU wants to read or write data, it sends the memory read or memory write control signal on the control bus to
perform the memory read or write operation from the main memory and the address of the memory location is sent on the
address bus. If CPU wants to read data stored at the memory location (address) 4, the CPU send the value 4 in binary on
the address bus.

Bus Arbitration in Computer Organization

Introduction : In a computer system, multiple devices, such as the CPU, memory, and I/O controllers, are connected to a
common communication pathway, known as a bus. In order to transfer data between these devices, they need to have
access to the bus. Bus arbitration is the process of resolving conflicts that arise when multiple devices attempt to access
the bus at the same time. When multiple devices try to use the bus simultaneously, it can lead to data corruption and
system instability. To prevent this, a bus arbitration mechanism is used to ensure that only one device has access to the
bus at any given tim

What is Bus Arbitration?

Bus Arbitration is the procedure by which the active bus master accesses the bus, relinquishes control of it,
and then transfers it to a different bus-seeking processor unit. A bus master is a controller that can access the
bus for a given instance.

A conflict could occur if multiple DMA controllers, other controllers, or processors attempt to access the
common bus simultaneously, yet only one is permitted to access. Bus master status can only be held by one
processor or controller at once. By coordinating the actions of all devices seeking memory transfers, the Bus
Arbitration method is used to resolve these disputes.

The Bus Arbiter decides who would become the current bus master.

Two approaches are followed for the bus Arbitration:

1. Centralized Bus Arbitration : A single bus arbiter performs the required arbitration.
2. Distributive Bus Arbitration : All devices participating in the selection of the next bus master.

Centralized Bus Arbitration Methodologies

There are three methods of Centralized Bus Arbitration, which are listed below:

1. Daily Chaining Method - All bus masters work on the same line to make bus requests in this
straightforward and less expensive approach. Up until it comes across the first master who is making a request
for access to the bus, the bus grant signal travels serially through each master. Any other seeking module will
not receive the grant signal and hence be unable to access the bus since this master prevents the bus grant
signal from propagating.
Any device linked to the bus, such as the processor or any DMA controller unit, may act as the bus master
throughout any bus cycle.

Its Advantages:

o It is scalable and provides simplicity

o The user is free to add multiple devices to a predefined number of maximum devices wherever he
wants along the chain.
Its Disadvantages:

o A device's priority value is determined by the location of the master bus.

o Using this strategy results in propagation delay.
o The entire system will cease to function if one gadget malfunctions.
3. Rotating or Polling Priority Method - The address lines needed depend on how many connected
masters are in the system. The controller is utilized to produce the unique priority for the master (or
address). A series of master addresses are generated by the controller. The bus is used once the
asking master knows its address and activates the busy line.

Its Advantages:

o This approach is neutral in terms of processor and device preferences.

o The process is also straightforward.
Its Disadvantages:

o It is challenging to add bus masters since it increases the circuit's address line count.
o The system will continue to function even if one device malfunctions.
3. Independent Request or Fixed Priority Method - A unique pair of bus requests and bus grant lines are
provided to each master, and each pair is given a priority. The controller's built-in priority decoder chooses the
utmost priority request and then asserts the matching bus grant signal.

Its Advantage:

o This technique produces a quick response.

Its Disadvantage:

o A significant number of control lines are needed, which raises the cost of the hardware.

Register, Bus and Memory Transfer

A basic computer has 8 registers, memory unit and a control unit.

The diagram of the common bus system is as shown below.

Connections: The outputs of all the registers except the OUTR (output register) are connected to the common bus. The
output selected depends upon the binary value of variables S2, S1 and S0. The lines from common bus are connected to
the inputs of the registers and memory. A register receives the information from the bus when its LD (load) input is
activated while in case of memory the Write input must be enabled to receive the information. The contents of memory
are placed onto the bus when its Read input is activated.

Various Registers: 4 registers DR, AC, IR and TR have 16 bits and 2 registers AR and PC have 12 bits. The INPR and
OUTR have 8 bits each. The INPR receives character from input device and delivers it to the AC while the OUTR
receives character from AC and transfers it to the output device. 5 registers have 3 control inputs LD (load), INR
(increment) and CLR (clear).

Abbreviation Register Name

OUTR Output Register

TR Temporary Register

IR Instruction Register
INPR Input Register

AC Accumulator
DR Data Register
PC Program Counter
AR Address Register
 Adder and logic circuit: The adder and logic circuit provides the 16 inputs of AC. This circuit has 3 sets of inputs. One
set comes from the outputs of AC which implements register micro operations. The other set comes from the DR (data
register) which are used to perform arithmetic and logic micro operations. The result of these operations is sent to AC
while the end around carry is stored in E as shown in diagram. The third set of inputs is from INPR.

Accumulator Register: The Accumulator Register can be abbreviated as AC and it is mainly used to store the
result of logical and arithmetic operations. This is also used as a temporary storage location for the data during
the calculations. This is most commonly used by every computer as they provide dedicated memory locations
for storing the data and results of the logical and arithmetic calculations and operation

Address Register: The Address Register or AR is a type of register that is mainly used to hold the memory
address of the data that the CPU wants to read or write to. The CPU uses AR to specify the memory location
that it wants to access. The Memory Data Register (MDR) is used in conjunction with the AR to transfer the
data between the CPU and memory.

Data Registers (DR): As the name suggests the Data Register or DR is the register that stores the data that
is written to memory or read from memory. Mainly DR is used to transfer the data between CPU and memory.
It will work in conjunction with Memory Address Register as it specifies the memory location that the CPU
wants to access.

Program Counter (PC): Program Counter (PC) is used to keep the track of the execution of the program. It
contains the memory address of the next instruction to be fetched. PC points to the address of the next
instruction to be fetched from the main memory when the previous instruction has been successfully
completed. Program Counter (PC) also functions to count the number of instructions. The incrementation of
PCs depends on the type of architecture being used.

Instruction Register (IR): The IR holds the instruction which is just about to be executed. The instruction
from the PC is fetched and stored in IR. As soon as the instruction is placed in IR, the CPU starts executing
the instruction, and the PC points to the next instruction to be executed.

Input Register (INPR): As the name suggests the input register is used to store the input that is given to the
CPU from an external device or source like a mouse or keyboard. This is mainly used in conjunction with
I/O(Input/ Output) instructions that transfer the data between external devices and the CPU.

Temporary Register: The intermediate result of the calculations is stored in these registers. There is not any
specific purpose for temporary registers so they can be used for any purpose by the CPU and because of this
they also sometimes refer to as the general-purpose register. It can also be used to store the intermediate data
between many calculations or complex calculations.

Output Register: This will store the result or the output from the CPU to an external device, such as a printer
or monitor. It is used in conjunction with the input/ Output instructions to transfer the data between external
devices and the CPU. It is also used to store the data temporarily that is to be shown as output so the CPU can
continue to execute further.

Processor Organization: In the context of computer systems, a processor organization refers to the way in
which the central processing unit (CPU) is designed and organized to carry out operations and execute
instructions. This includes the physical layout and architecture of the processor, as well as its functional
components, such as registers, cache, and pipelines. The processor organization can have a significant impact
on the performance and efficiency of a computer system.

Introduction of General Register based CPU Organization


When we are using multiple general-purpose registers, instead of a single accumulator register, in the CPU
Organization then this type of organization is known as General register-based CPU Organization. In this
type of organization, the computer uses two or three address fields in their instruction format. Each address
field may specify a general register or a memory word. If many CPU registers are available for heavily used
variables and intermediate results, we can avoid memory references much of the time, thus vastly increasing
program execution speed, and reducing program size.
For example:
MULT R1, R2, R3
This is an instruction of an arithmetic multiplication written in assembly language. It uses three address fi elds
R1, R2, and R3. The meaning of this instruction is:
R1 <-- R2 * R3
This instruction also can be written using only two address fields as:
MULT R1, R2
In this instruction, the destination register is the same as one of the source registers. This mea ns the
operation
R1 <-- R1 * R2
The use of a large number of registers results in a short program with limited instructions.
Some examples of General register-based CPU Organizations are IBM 360 and PDP- 11.

Features of a General Register based CPU organization:

Registers: In this organization, the CPU contains a set of registers, which are small, high-speed memory
locations used to store data that is being processed by the CPU. The general-purpose registers can be used
to store any type of data, including integers, floating-point numbers, addresses, and control information.
Operand access: The CPU accesses operands directly from the registers, rather than having to load them
from memory each time they are needed. This can significantly improve performance, as register access is
much faster than memory access.
Data processing: The CPU can perform arithmetic and logical operations directly on the data stored in the
registers. This eliminates the need to transfer data between the registers and memory, which can further
improve performance.
Instruction format: The instruction format used in a General Register based CPU typically includes fields
for specifying the operands and operation to be performed. The operands are identified by register numbers,
rather than memory addresses.
Context switching: Context switching in a General Register based CPU involves saving the contents of the
registers to memory, and then restoring them when the process resumes. This is necessary to allow multiple
processes to share the CPU.
The advantages of General register-based CPU organization –
 The efficiency of the CPU increases as large number of registers are used in this organization.
 Less memory space is used to store the program since the instructions are written in a compact way.
The disadvantages of General register based CPU organization –
 Care should be taken to avoid unnecessary usage of registers. Thus, compilers need to be more
intelligent in this aspect.
 Since a large number of registers are used, thus extra cost is required in this organization.
General register CPU organization of two types:
1. Register-memory reference architecture (CPU with less register) –
In this organization Source 1 is always required in the register, source 2 can be present either in the
register or in memory. Here two address instruction formats are compatible instruction formats.
2. Register-register reference architecture (CPU with more register) –
In this organization, ALU operations are performed only on registered data. So operands are required in
 the register. After manipulation, the result is also placed in a register. Here three address instruction
formats are the compatible instruction format.

Introduction of Stack based CPU Organization

The computers which use Stack-based CPU Organization are based on a data structure called a stack. The
stack is a list of data words. It uses the Last In First Out (LIFO) access method which is the most popular
access method in most of the CPU. A register is used to store the address of the topm ost element of the
stack which is known as Stack pointer (SP). In this organization, ALU operations are performed on stack
data. It means both the operands are always required on the stack. After manipulation, the result is placed in
the stack.
The main two operations that are performed on the operators of the stack are Push and Pop. These two
operations are performed from one end only.
1.Push –
This operation results in inserting one operand at the top of the stack and it increases the stack pointer
register. The format of the PUSH instruction is:
PUSH
It inserts the data word at a specified address to the top of the stack. It can be implemented as:
// Increment SP by 1
SP <-- SP + 1
//store the content of specified memory address
//into SP; i.e, at top of stack
SP <-- (memory address)
2. Pop –
This operation results in deleting one operand from the top of the stack and decreasing the stack pointer
register. The format of the POP instruction is:
POP
It deletes the data word at the top of the stack to the specified address. It can be implemented as:
//transfer the content of SP (i.e, at top most data)
//into specified memory location
(memory address) <-- SP
//Decrement SP by 1
SP <-- SP - 1
PDP-11, Intel’s 8085, and HP 3000 are some examples of stack-organized computers.
The advantages of Stack-based CPU organization –
 Efficient computation of complex arithmetic expressions.
 Execution of instructions is fast because operand data are stored in consecutive memory locations.
 The length of instruction is short as they do not have an address field.
The disadvantages of Stack-based CPU organization –
 The size of the program increases.
Note: Stack-based CPU organization uses zero address instruction.