Design and Implementation of Selective Active

EMI Filter with Digital Resonant Controller

*
Hongwu Peng, Balaji Narayanasamy, Asif Imran Emon, Zhao Yuan, Mustafeez Ul Hassan, and Fang Luo
University of Arkansas, Fayetteville, AR, USA
*
[email protected]

Abstract—In the power electronics equipment, passive EMI is stability. The stability is mainly influenced by the phase
filters occupy up to 30% of system’s volume and weight. In order shift introduced by the noise-sensing stage [27] and the noise-
to reduce the size of passive EMI filter in the power electronics processing stage. Particularly, in converters with ac voltage,
system, active EMI filters (AEF) is introduced. With the AEF
approaches, the size of the passive component within the EMI a second-order high-pass filter is required to separate the
filter can be reduced by more than 50%. The higher attenuation sensed noise from the fundamental voltage or current signal.
achieved by AEFs, the more size reduction can be obtained This results in reduced attenuation of the AEF and additional
through AEFs methodology. However, the performance of AEF compensation network. Some compensation networks require
with feedback control is limited to around 24 dB attenuation in high-voltage capacitors, thus reducing the volumetric benefits
the reported work. New methodology needs to be found to push
forward the performance. In this study, a novel digital active of using an active EMI filter. This limitation is applicable
EMI filter (DAEF) with the resonant controller, which provides to both analog and digital AEF. In [35] showed how the
ultra high-gain at frequencies of interest, is demonstrated for processing delay in digital AEF affects the attenuation. In [34],
DM noise attenuation. The experimental test results show that it was shown that the previous switching cycle noise could be
the proposed EMI filter has 45 dB more attenuation at 150 kHz used to compensate for noise in the next switching cycle to
than the conventional passive EMI filter, which is also the highest
attenuation reported in the AEF literature. avoid the delay. However, attenuation of only 24 dB could
Index Terms—Conducted emission, digital active EMI filter, be achieved in the process. This paper proposes an improved
resonant controller, Field Programmable Gate Array (FPGA) digital active EMI filter that uses the resonant controller, which
achieves improved attenuation without increasing the volume
I. I NTRODUCTION overhead from additional high-voltage components.
In order to comply with certain conducted emission stan- Proportional resonant (PR) controller [36], [37] has been
dard, the passive EMI filter is needed for the power elec- widely used in grid-connected inverters, which provides supe-
tronics equipment [1]–[6]. In most of the power converter rior performance than conventional proportional-integral (PI)
with semiconductor switches [7]–[11], the passive EMI filter controller in tracking fixed frequency signals. Ideally, the
occupies up to 30% of system’s size [12]–[17]. Thus, AEF resonant part of the PR controller provides infinite gain on
could be utilized to reduce the size of passives [18]–[25]. the frequency of interest, while provides no gain and phase
There are different approaches for the classification of AEFs: at other frequencies. Thus, the resonant controller will be
noise sensing methodology, noise cancellation circuits, and perfectly suitable for the VSCC DAEF application. However,
active circuits. AEFs with feedback [26]–[28] and feedforward CISPR 22 [38] class B conducted noise limits, which is
[29], [30] have been evaluated in past works, which provides widely used in the residential environment, define EMI test
an attenuation of 20 to 30 dB. By combining feedback and frequency range from 150 kHz to 30 MHz. If the resonant
feedforward implementation together [28], two-stage AEFs controller is to be implemented in the DAEF system, the
have pushed the attenuation of AEFs to more than 40 dB. resonant frequency should be set to be a few 100s of kHz,
However, two-stage AEFs adds to system complexity as well while digital controller discretization frequency should be at
as volume of passive component. Owning to the growth least a few 10s of MHz for fulfilling the speed requirement.
of controller’s computing speed, DAEFs [31]–[34] that use Thus, FPGA instead of DSP is to be used for the ultra-high
DSP/FPGAs have been demonstrated. This paper proposes frequency control. The structure of the resonant controller is
a new implementation of single -stage AEF, which provides shown in Fig. 1b, multiple resonant controllers are used in
higher attenuation than any previous works. parallel at different frequencies for canceling EMI noise on
The voltage-sensing current-cancellation (VSCC) feedback different frequencies.
AEF with digital resonant controller is shown in Fig. 1aa. The The contributions of this work are as follows. A novel digital
system comprises of the noise sensing circuit, the Analog- AEF that utilizes both VSCC topology and the resonant con-
to-Digital Converter (ADC), the DSP/FPGA, the Digital-to- troller is proposed, the stability design of the implementation is
Analog Converter (DAC), the active circuit, the main passives, demonstrated. The discretization and modeling of the resonant
and the compensation circuitry. The DSP/FPGA will not be controller based VSCC AEF are demonstrated, and the design
present in an analog-only implementation. The main limitation methodology for proposed implementation is included. By
to the performance of any AEF with feedback compensation utilizing the resonant controller in the FPGA control system,

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 (a) Digital active EMI filter based on VSCC topology
(b) Resonant controller built in FPGA

Fig. 1: Proposed digital active EMI filter with the resonant controller

the proposed AEF achieves an attenuation of 46 dB at around

150 kHz which is 25 dB higher than conventional single-stage
active EMI filter. This is the highest reported attenuation in
the literature using single-stage digital or analog AEF.
The organization of the work is as follows. Section II
describes the topology which is used in the implementation.
Section III involves the theoretical modeling of proposed
VSCC with the resonant controller. Section IV describes the
design case for the proposed concept and frequency domain
measurements using the VNA to verify the modeling. Section
V describes the experimental test setup and discusses the (a) Simplified VSCC AEF topology
small-signal and converter test results. Section VI presents the
conclusion.
II. ACTIVE EMI FILTER T OPOLOGY
Different AEF topologies use either current or voltage sens-
ing and compensation. While for AEF topologies that utilize
current-sensing or voltage compensation, current transformers
(CTs) or voltage-injection transformers are needed. For DM
noise, CTs and voltage-injection transformers can be bulky
when the line current is high. Therefore, AEF topologies that
do not have transformers are preferred. The voltage-sense
current-cancellation topology requires high voltage capacitors (b) Equivalent circuit of VSCC AEF topology
and other low voltage circuitry for noise sensing and can-
Fig. 2: VSCC AEF topology
cellation. In summary, VSCC topology will maximize the
volume reduction for AEFs, which will be used in this pa- is the noise source current and IS0 represent equivalent noise
per. Previously, feedback control based voltage-sense current- source current considering the current sharing between the
cancellation topology was demonstrated in [27]. However, the differential-mode noise source impedance (ZS ) and impedance
attenuation of only 12 dB at around 150 kHz is obtained. of DM inductor. The new equivalent noise source (IS0 ) and
This paper utilizes the resonant controller built in FPGA for noise source impedance (ZS0 ) is given by (1) and (2), respec-
the feedback loop of VSCC AEF, which achieves 46 dB tively. The AEF cancellation current and noise current on the
attenuation at around 150 kHz and is the highest attenuation LISN are represented by ISC and ISL , respectively. The noise
in reported literature. voltage on the LISN is represented by VL .
The VSCC AEF topology is shown in Fig. 1. And the
simplified version of VSCC topology is shown in Fig. 2a, ZS
IS0 = IS (1)
where the feedback loop is collapsed into a transfer function ZS + ZDM
Rjt . Through Norton and Thevenin equivalent circuit transfor-
mation, the equivalent circuit can be obtained as Fig. 2b. IS ZS0 = ZS + ZDM (2)

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 III. D ESIGN AND MODELING OF THE ACTIVE EMI F ILTER
ISL GF W
WITH D IGITAL R ESONANT C ONTROLLER GCL = = (5)
IS0 1 + GF W · GF B
According to Fig. 1 and Fig. 2b, the block diagram of VSCC
AEF system is shown in Fig. 3a. The equivalent feedforward GF W 1
GIS = = (6)
and feedback loop equivalent block diagram is shown in Fig. GCL 1 + GF W · GF B
3b, where GF W (s) and GF B (s) donate transfer function of
forward and backward loop. Sensing and FPGA processing are TLG = GF W · GF B (7)
collapsed into Rjt . The open-loop current gain GF W without
The sensing and FPGA processing transfer function Rjt
the DAEF (Rjs is disconnected) is given by (3). And the
is shown In Fig. 3c. THP F denotes the transfer function of
feedback loop transfer function is give by (4). Close-loop
the high pass filter, Tiso denotes the RF transformer transfer
current gain GCL with active EMI filter is give by (5). The
function, GADC and GDAC denotes the transfer function of
insertion gain GIS , which is defined as the ratio of current
ADC sampling stage, Rwi,T p (z) denotes the transfer function
flowing through ZLISN with and without active EMI filter,
of digitized resonant controller, GZOH denotes the transfer
can be derived as (6). The open loop gain is given by (7),
function of transformation between continuous and discrete
which will be used for defining stability margin.
domain. Within FPGA, resonant controllers are built in parallel
with each other, the transfer function of Rjs is given by
(8). The resonant controller provides high gain at frequencies
which match with noise source spectrum, and provide high
attenuation to the EMI noise at those frequencies. However, the
delay introduced by ADC/DAC and the phase introduced by
resonant controller will give rise the stability issue in feedback
loop.

wX
i =wn
2
Rjs = THP F · Tiso · GADC · GDAC · Rwi,T P (z) (8)
wi =w1

(a) System block diagram (Sensing and FPGA processing stage are Discretization methods of resonant controller and detailed
collapsed into Rjt ) modeling of each component within VSCC DAEF system will
be discussed in the next few sections, which will provide a
guideline of the detailed resonant controller modeling strategy.
A. Gain Selection for Resonant Controller
The selection of gain at different resonant frequencies is
dependant on the clock accuracy for pulse width modulation
(PWM), the accuracy of resonant controller itself within
(b) Equivalent system block diagram
FPGA, and the fundamental frequency of output current if the
noise source is an inverter. Assuming resonant frequency of
resonant controller is wi , and the frequency variation caused
by the PWM clock accuracy or calculation accuracy is ∆wi
(either positive or negative). The amplitude of the resonant
controller at w = wi + ∆wi frequency is given by (9). The
lower limit of gain value selection is given by (10), where
dBrsd denotes the desired amplitude residue of the resonant
controller at w = wi + ∆wi frequency. The higher limit of
gain value is given by (11), which limits the bandwith of
resonant within wi − 0.05wi to wi + 0.05wi to make sure that
the resonant controller will not create stability issues when
(c) Sensing and FPGA processing stage block diagram
multiple resonant controllers are used in parallel.

Fig. 3: Block diagram of VSCC DAEF system Kr,i

|Rs (wi + ∆wi )| = | ∆wi2
| (9)
−2∆wi + wi +∆wi
ISL ZS0 · ZIN J dBrsd
GF W = 0 = 0 (3) |Rs (wi + ∆wi )| > 10 20 (10)
IS ZIN J · (ZS + ZLISN ) + ZLISN · Zs0
ISC ZLISN 10Kr,i
GF B = = Rjs (4) |Rs (wi ± 0.05wi )| ≈ <2 (11)
ISL ZIN J wi

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 B. modeling of The High Pass Filter of ADC and DAC are given in (17) and (18), where m and
The converter that uses this filter could be fed from an n denote the bit width of ADC and DAC, VADC and VDAC
ac or dc supply. Either way, the noise-sensing stage has to denote the range of ADC and DAC, nADC and nDAC donate
sufficiently attenuate any 60 Hz ac voltage and its harmonics, the clock latency of ADC/DACs.
and the high-frequency currents due to rectifier operation or 2m
any other converters connected to the same node. Otherwise, GADC = · z −nADC (17)
VADC
any low frequency harmonic can easily saturate the output of
the active circuits. Ideally, the output of the high pass filter VDAC −nDAC
should only include the switching frequency and its harmonics GDAC = ·z (18)
2n
in the desired EMI frequency range (150 kHz to 30 MHz). The
IV. S YSTEM L EVEL MODELING OF THE C ONFIGURATION
design of the sensing network requires careful consideration
AND S TABILITY A NALYSIS
to ensure that it:
1. has the desired performance throughout the entire frequency In this section, the parameter of the AEF system will be
range and given or derived based on previous sections, and then the open
2. it does not add too much to the volume of the filter loop gain and close loop gain modeling and measurement will
It is not possible to get around high attenuation at 60 Hz be conducted.
with a 1st order high pass filter. Therefore a 2nd order high The noise source is a DC-DC converter, the output filter
pass filter is used as the sensing network. The capacitor Cs1 components’ parameters are: L = 70µH and C = 5µF .
needs to be rated for the input voltage and needs to be safety The switch frequency of DC-DC converter is 50 kHz, and
rated (X1Y1 rated). The other components Cs2 , Rs1 and Rs2 it’s realizing 12 to 5 V conversion. The inductance value of
are low voltage and low power components. The capacitor Cs2 the DM inductor is LDM = 131µH, and capacitance value of
is a 50 V rated X7R surface mount capacitor. The transfer the DM capacitor is CIN J = 470nF .
function of the filter is given by (12) ∼ (14). The output of The gain for resonant controller (Kr,i ) is selected based
the high pass filter is buffered (op-amp configured as voltage on (9) ∼ (11). For example, for an DC-DC converter which
follower) and fed to ADC. The selected op-amp is unity-gain switching frequency is 50kHz, and resonant controller at 150
stable with a gain-bandwidth of about 500 MHz. Therefore, kHz is to be designed for DAEF. Assuming the 150 kHz noise
the output of the buffer could be assumed to be the same as will have ±300Hz variation. 30 dB amplitude residue (dBrsd )
that of the high pass filter. at 150kHz ± 300Hz is to be ensured. According to (10), the
lower limit of gain Ki can be calculated as 1.9 · 104 . And
s2 according to (11), the higher limit of Ki can be calculated as
THP F = (12)
s2 + k1 s + k2 3 · 104 . So the value of resonant controller gain Ki should
1 1 1 satisfy 1.9 · 104 < Ki < 3 · 104 .
k1 = ( + + ) (13) For the second order high pass filter, the components’ values
Cs1 Rs1 Cs1 Rs2 Cs2 Rs2
are: Cs1 = 4.7 nF , Cs2 = 10 nF , Rs1 = 3.3 kΩ and Rs2 =
1 3.3 kΩ. According to (12) ∼ (14), two corner frequencies of
k2 = (14)
Cs1 Cs2 Rs1 Rs2 the high pass filter can be calculated as 700Hz and 7kHz.
C. modeling of the ADC and DAC Sampling System The attenuation of 60Hz signal is around 35dB, which will
make sure that the line frequency voltage variation will not
According to [39], the RF transformer which is used in sam-
saturate the ADC sampling.
pling system for matching the impedance on termination, the
The proposed concept is implemented using Intel Cyclone
transfer function can be modelled as (15). The characteristic
IV FPGA in a Terasic DE2-115 demo board, and the operating
of the RF transformer is simply a band pass filter, which has
frequency is set to 100 MHz, so the discretization time step
the first corner frequency w1 as around 20 kHz and the second
is Ts = 10ns. In the configuration, the ADC AD9254 [41]
corner w2 as around 200 MHz.
has around 4 ns of propagation delay and 12 cycles of clock
1 latency. Since the ADC is using FPGA’s clock output as ADC
Tiso = (15) clock in the design, the propagation delay can be ignored and
(1 + w1 /s) · (1 + s/w2 )
totally 13 cycles of clock latency exists in ADC sampling. The
[40] presented the model of discrete sampling system,
same concept can be applied to DAC DAC5672 [42] model.
transfer function of transformation between continuous and
In equation (17) and (18), the nADC and nDAC values can be
discrete domain is given in (16), where Ts represents the
acquired as (19).
digitization step.

1 − e−sTs nADC = 14, nDAC = 5 (19)

GZOH = (16)
sTs Based on (3) ∼ (8), the loop gain of the proposed config-
For most of the off-shore ADC/DACs, there are clock uration of AEF without resonant controller can be expressed
latency which is around 5 to 15 clock cycles. Thus, the model as (20). The first round of loop gain and phase measurement

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 should be done by replacing resonant controller with unity
gain transfer function, which is described as (7). The loop
gain measured from the circuit under test as well as loop
gain calculated from modeling is shown in Fig. 4. From
70 kHz to 20 MHz, the model matches pretty well with
the measurement, the discrepancy of low frequency and high
frequency gain/phase might be caused by the inaccuracy model
of the RF transformer.

ZLISN 2
TLG,w/o res = GF W · · THP F · Tiso · GADC · GDAC
ZIN J
(20)

Fig. 5: Loop gain with the resonant controller

Fig. 4: Loop gain without resonant controller

Fig. 6: Insertion loss measurement of DAEF implementation
Gain and phase of the loop gain without PR controller is of
great significance in determining where digital PR controller
can be implemented. The resonant controller will introduce kHz is enhanced by about 45 dB using the resonant controller.
90◦ lead/lag. In order to make sure that the entire loop gain The insertion loss is high at harmonics of 50 kHz (n = 3, 4,
with the resonant controller implemented is stable, original ..., 19).
phase of the loop gain without PR controller should be within
±90◦ , otherwise phase compensation should be implement
together with the resonant controller. Remaining 25◦ phase V. E XPERIMENTAL R ESULTS
margin, 65 kHz to 950 kHz frequency range is available for
implementing resonant without any phase compensation. The filter discussed in above is implemented in the experi-
Assuming the noise source is a converter/inverter operating ment. The proposed resonant controller is implemented in the
at 50 kHz switching frequency, then the noise source will FPGA (Intel Cyclone IV FPGA in a Terasic DE2-115 demo
contain ki · 50kHz noise and its harmonics. CISPR 22 defined board along with Terasic AD/DA daughter card with sample
the conducted emission limit from 150 kHz to 30 MHz, so rate of 100 MHz). Apart from the filter, the noise is measured
the resonant controller’s frequencies are selected as i · 50kHz at the LISN using an EMI receiver.
where i ranges from 3 to 19. Gain selection for resonant In the small signal measurement, a function generator along
controller is done by using (10) and (11). After carefully with a buffer is used as the noise source, and D = 0.5 and D
designing the resonant frequencies and gains, the loop gain = 0.3 of noise source are implemented and test. The EMI
incorporating resonant controller is obtained in Fig. 5. As it receiver measurement is shown in Fig. 8a and the attenuation
can be seen from the loop gain measurement, the phase margin at 150 kHz with the active EMI filter is about 45 dB which
at highest frequency is exactly 25◦ , which matches very well is the highest attenuation reported in any active EMI filter
with previous analysis. literature, both analog and digital active EMI filters. As for
The insertion loss measurement result is shown in Fig. 6. D = 0.3 condition, harmonics of 50 kHz (n = 3, 4, ..., 19) is
From the figure it can be seen that the insertion loss at 150 attenuated down to noise floor as well.

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 resonant controller along with the digital active EMI filter
to improve the attenuation by another 20 dB. Design and
modeling of the proposed DAEF are discussed, small-signal
experimental results as well as converter experimental results
have confirmed the validity of the proposed method.

(a) Equivalent circuit for experiment setup ACKNOWLEDGMENT

The authors would like to acknowledge the National Science
Foundation (NSF Award No. 1846917) for lending financial
support for this work.

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