VLSI Physical Design Automation

Prof. G.K.Sharma

ABV-IIITM, Gwalior

August 4, 2015

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Standard Cell Layout

I A standard cell (or a polycell) is a logic block that performs a

standard function.
Example: Two-input NAND gate, two-input XOR gate,
D flip-flop, two-input multiplexer etc.
I Cell Library is a collection of information pertaining to
standard-cells.
I Relevant information about a cell consists of its name,
functionality, pin structure, and a layout for the cell in a
particular CMOS technology such as 90nm, 45nm, 32nm etc.
I Cells in the same library have standardized layouts, i.e., all
cells are constrained to have the same height.

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Layout-Inverter Standard Cell

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Cell-Based Design

I Cell-based design is similar to designing a circuit using SSI

and MSI components, except the implementation details.
I Selection is from a cell-library, and components are placed in
silicon instead of PCB.
I Advantage: More flexibility and rapid design completion.
I Disadvantage: All the fabrication steps are necessary to
manufacture.
I Layout program will only be concerned with:
1. Location of each cell, and
2. Interconnection of the cells.
I Placement and routing is again simplified using a standard
floorplan.

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Floorplan: Standard-Cell Layout

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Macro-Cell Layout

I Both gate-array and standard-cell designs impose restrictions

on the cells that are used to design the circuit.
Example: The cells in a standard-cell layout must have the
same height.
I Macro-cell layout or Building-Block Layout (BBL) have no
restrictions and permits cells to vary in both dimensions.
I Cells can no longer be placed in a row-based floorplan.

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Macro-cell Layout (Contd...)

Cells of varying heights and widths placed in a row-based floorplan.

A more compact floorplan for the same circuit is preferred.

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Macro-cell Layout (Contd...)

I Advantages:
1. Cells of significant complexity are permitted in the library
(registers, ALUs, etc).
2. Building-block layout (BBL) comes closest to full-custom
layout.
3. Like standard-cell layout style, all the processing steps are
required to manufacture a BBL chip.
I Disadvantages:
1. It is much more difficult to write layout programs for the BBL
design style.
2. There is no standard floorplan to adhere to. As a result, the
routing channels are not predefined either.
3. Floorplanning and channel definition are additional steps
required in a BBL layout system.

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FPGA Layout

I FPGAs were first introduced in 1985 by Xilinx Company.

I An FPGA (Field Programmable Gate Array) also consists of a
two-dimensional array of logic blocks.
I Each Configurable Logic Block (CLB) can be programmed to
implement any logic function of its inputs.
I The channels or switchboxes between logic blocks contain
interconnection resources.
I These interconnects contain programmable switches that
serve to connect the logic blocks to the wire segments, or one
wire segment to another.
I I/O pads are also programmable to be either input or output
pads.

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Typical FPGA Diagram

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FPGA Layout: Design Steps

Main design steps to implement digital circuits:

1. Technology Mapping: Mapping of the initial logic description

of the circuit into a netlist of CLBs.
2. Placement: Assign each CLB in the netlist, a corresponding
CLB in the array.
3. Routing: Interconnecting the CLBs of the array.
4. Generating Bit Patterns: To ensure that the CLBs perform
the assigned function and interconnected as decided by the
routing step.
Note: In FPGAs, both the logic blocks and the interconnects are
field programmable.

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FPGA Layout (Contd...)

I Design issues include trade-offs in the granularity (fine/coarse

grain) and flexibility of both logic blocks and the
interconnection resources.
I Advantages: Lower prototyping cost and shorter production
times.
I Disadvantages: Lower speed of operations and lower gate
density.
I FPGAs are most ideally suited for prototyping applications,
and implementation of random logic using Programmable
Array Logic (PALs).
They have also been successfully used in the implementation
of Application-Specific Integrated Circuits (ASICs).

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Physical Design Problem
I Physical design is a complex optimization problem, involving
several conflicting objectives.
I It is customary to adopt a stepwise approach and subdivide
the problem into subproblems (Circuit Partitioning,
Floorplanning, etc.).
I All these subproblems are constrained optimization problems.
Unfortunately these layout subproblems (even simplified
versions) are NP-Hard.
I Instead, optimal enumerative techniques heuristics based are
used.
I Solution quality of heuristics is determined using artificial
inputs whose optimal solutions are known or using test inputs
comprising of real circuits, called benchmarks, (MCNC,
ISCAS).
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Terminology and Definitions

I Cell: Logic block (AND, OR, NAND, NOR, XOR etc.) is

useful in building larger circuits.
I Macro-cell: Logic circuit composed of basic gates and possibly
flip-flops.
I Logic Module: Macro-cell or standard-cell based.
I Pin: Wire (metal or polysilicon) for connection. A module
interfaces to other modules through pins.
I Net: Collection of pins which must be electrically connected.
e.g., clock pins of all the flip-flops must be connected.
I Graph: Abstract representation that is more convenient to
work with than the original netlist.

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Connectivity Information

I Input to a layout program is a circuit description. Basically,

one must specify the modules used in the circuit and how they
are interconnected.
I Module information consists of the name of the module, its
shape and size information, and the pin structure of the
module.
I In particular layout styles, some of this information may be
omitted.
I A netlist description is, as the name suggests, a list of all the
nets in the circuit.
I Connectivity information can be represented in the form of an
n × n matrix.

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Example: Full Adder Carry

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NETLIST: Example (Contd...)

(A, AND[1].IN1)
(B, AND[1].IN2)
(C, AND[2].IN1)
(B, AND[2].IN2)
(A, AND[3].IN1)
(C, AND[3].IN2)

(AND[1].OUT, OR3[1].IN1)
(AND[2].OUT, OR3[1].IN2)
(AND[1].OUT, OR3[1].IN3)
(OR3[1].OUT, Z)

(AND[1].Vdd, AND[2].Vdd, AND[3].Vdd, OR3[1].Vdd)

(AND[1].Gnd, AND[2].Gnd, AND[3].Gnd, OR3[1].Gnd)

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Connectivity Graph: Example (Contd...)

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Connectivity Matrix

I If there are n modules in the circuit, the connectivity ci of

module i is defined as follow,
X
n
ci = cij
j=i

Element cij is the connectivity between modules i and j.

I The connectivity matrix is symmetric, i.e.,

cij = cji i, j = 1, 2, 3, ....n

I Also, It is never required to externally connect two pins of the

same module, i.e.,

cii = 0 i = 1, 2, 3, ....n

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Connectivity Matrix: Example (Contd...)

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Tree: Example (Contd...)

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Tree

I The style of routing, where wires can only make 90-degree

turns is known as Manhattan routing.
I The length of the wiring required to implement a two-pin net
is measured by taking the Manhattan distance between the
two pins.
I If the two pins are located at coordinates (x1 , y1 ) and (x2 , y2 ),
the Manhattan distance between them is given by

d12 = |x1 − x2 | + |y1 − y2 |

Note: d12 is the shortest possible length of wire required to

connect the two pins using the Manhattan style of routing.
It may or may not be possible to route the net along the
shortest path.

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Remarks

I In this session we introduced the basic concepts of VLSI

physical design and Design Automation.
I Physical design is the final step in the VLSI design process,
and involves mainly the placement of circuit modules and
routing of the nets.
I In order to automate the layout procedure, it is common to
impose restrictions on the layout architecture.
I Automatic layout methodologies rely on the extensive use of
computer programs during all design phases.
I In order to reduce the complexity the layout process is broken
into a sequence of physical design phases.
I Each of design phases amounts to solving a combinatorial
optimization problem.

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Comparision

Table below assesses and compares several aspects of the various

layout styles. The number in parentheses indicates a rank to grade
the layout style in comparison to others in the same category.

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