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Answer Final - Exam Microprocessor - ECE341 2022-2023

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Answer Final - Exam Microprocessor - ECE341 2022-2023

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mam644564
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© © All Rights Reserved
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Higher Institute of Engineering and Technology in Zagazig

Answer-Final - Exam 2022-2023


Microprocessor and its applications
Course: ECE341
Date: 15/1/2023 Time: 180 minutes
Examiner: DR Ehab Rushdy No of pages: 2

Answer all questions (70 points)


Q1 (20 points) Complete the missing words, one point for each part:
No Statement
1 The …Flowchart……..always begins with start terminal symbol.
2 ……Micro-Computer………. contains microprocessor and other circuits like memory
3 ……MPU………. is a logic circuit that can be used to perform arithmetic operations.
4 …Program.. is group of instructions that stored in memory that allows the computer to perform a special task.
5 ……Word……… is fundamental unit of memory.
6 ……PC………….. stores or holds address of next instruction to be fetched.
7 In…Forward…………. branching, the offset or relative address is positive.
8 …Bus…………. is a communication pathway connecting two or more components.
9 Instructions got from memory are loaded finally into ……IR….. in MPU during fetch phase.
10 ……DR…… stores the data to be written into memory or receives from memory.
11 ……AC…… is used to store the output of arithmetic and logic operations.
12 ……ALU……. is the component in MPU that used to perform arithmetic and logic operations.
13 Each instruction stored in memory , consist of …Opcode….. and operand.
14 In …Immediate…….mode, the operand is immediately following opcode.
15 The time needed for fetching and executing the instruction is given by ……MPU cycle Time………..
16 The BEQ instruction causes a branch to occur only if …Z…… Register is set.
17 …Code or Condition……….. registers act as extension to AC.
18 If the size of PC register is 8 bits, the number of accessible memory locations is …… 256...
19 True or False: “BCS “instruction tests Z register to see if it set or not. False
20 True or False: “BMI “instruction tests C register to see if it set or not. False
21 PC in 6800 processor has …16……bits.
22 True or False : each Accumulator in 6800 MPU has its own Carry. False
23 True or False : C, I and V code registers can be individually cleared or set. True
24 ……WAI…………. instruction in 6800 MPU is corresponding to Halt Operation.
25 ……ABA…………. instruction in 6800 MPU, means A+B → A A, B are Accumulator A , B
26 ……TAP…………. instruction in 6800 MPU, means A→B
27 …CLC……………. instruction in 6800 MPU, means 0→C C is a Carry Register
28 ……TAP…………. instruction in 6800 MPU, means A → CCR CCR is Code Condition Registers
29 Index Addressing requires …………2…………. bytes for each instruction.
30 Extended Addressing can address ……65536……………bytes of memory

Page 1 of 4
Q2 (15 points) 2.5 points for each part:
A. Illustrate how 6800 processor differs from basic microprocessor.
 Two Accumulators A, B
 PC is 16 Bit Register
 7 Code registers
 16-bit Index Register for Extended Addressing

B. Illustrate the function of basic registers in MPU?


 DR: It stores the data going or coming from Memory.
 MAR: It holds the address of memory location or I/O used in the present operation
being performed.
 PC: It contains the address of memory has to be fetched next.
 IR: It decodes the code of instruction and decides which operation to be performed.
 AC: it has been used in performing arithmetic operations and results also are stored in.
 Controller Sequencer: it produces a variety of control signals to carry out different
instructions
C. Illustrate the types of addressing modes.
 Inherent mode: the instruction has no operand , it is one byte instruction as HLT.
 Immediate mode: in which the operand is stored in the next sequential memory
location following the instruction opcode as ADD X.
 Direct addressing: the next sequential memory location contains the address of the
operand.
D. In 6800, illustrate how to set all code registers?
 SEI set for I register
 SEV set for V register
 SEC set for C register
--------------
 CLRA
 COMA
 TAP
E. Illustrate the difference between extended and indexed addressing.
 Extended Addressing: The instruction will have three bytes, one for Opcode the other
two bytes for addressing ( forming 16-bit address).
 Indexed addressing: Index-addressing X is used, The address is the sum of the relative
address that followed the opcode plus X.
F. Illustrate the difference between ANDA M , BITA M instructions?
ANDA M: perform and operation between AC A and M , the result will be saved in A.
BITA M ,Compare only between AC, M , no changes in both AC nor M, only code registers are changed
according to comparison.

Page 2 of 4
Q3 (10 points) 5 Points for each Part:
A. Draw flow chart and Write a program starts from (00)16 location, to perform the following task:
-If the number at address 1016 is negative, then store the product of two numbers stored at
addresses 1116, 1216 at address 1316.
- If the number at address 1016 is not negative, then get quotient of dividing the data on
address 1116.over the data stored at 1216, and stores it on address 1316

CLRA
STA
11
LDA
12
BEQ
09
DECA
STA
22
LDA
13
ADD
11
BRA
F1
HLT

B. For the 10 numbers located in location 4016 till 4916, Draw flowchart and Write a program to
count the positive numbers and stores it in address 6116.
10 CLR A
11 STAB
12 61
13 LDAB
14 #10
15 LDX
16 #49
17 LDA X
18 49
19 BPL
1A 05
1B INX
1B DECB
1C BNE
1D 06
1E INC 61
1F BRA
20 F6

Page 3 of 4
Q4 (15 points) 1 point for each part:
In 6800 MPU: Accumulator A has a value of 00001111 Accumulator B has a value of 01010101, Index
Register X has a value of 00110011 01010101
Stack pointer SP has a value of 00100010 10101010
C register has a value of 0
Memory location (0021)16 has a value 01101101. Memory location (0022)16 has a value 00110111
Illustrate the change in registers and memory locations after the execution of each instruction:

No Part result
1. ROLA A=00011111
2. LDAB 0021 B=01101101
3. RORB B= 10101010
4. ASL 0021 (0021)= 00110110
5. LSRB B= 10110110
6. TBA B=A
7. STS 0021 (0021)
(0022)
8. ANDA 0021 (0021)
9. LDX 21 X=
10. EORA 0021 A=
11. BITA 0021 C=0, N=0
12. CMPB 0021 C=0 N=1
13. CBA C=1 N=1
14. TST 0021 C=0 N=1
15. TSTB C=0 , N=0

Page 4 of 4

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