Emulation: Interpretation

Contents
ƒ Emulation, Basic Interpretation

ƒ Threaded Interpretation

ƒ Emulation of a Complex Instruction Set

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 Emulation
ƒ “Implementing the interface/functionality of one system on
a system with different interface/functionality“
ƒ In VM, it means instruction set emulation
• Implementing one ISA (the target) reproduces the behavior of
software compiled to another ISA (the source)

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 Emulation Methods
ƒ Two methods of emulation: interpretation & binary translation
ƒ Interpretation
• Repeats a cycle of fetch a source instruction, analyze, perform
ƒ Binary translation
• Translates a block of source instr. to a block of target instr.
• Save the translated code for repeated use
• Bigger initial translation cost with smaller execution cost
• More advantageous if translated code is executed frequently
ƒ Some in-between techniques
• Threaded interpretation
• Predecoding

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 Basic Interpreter
• Emulates the whole Source Context
source machine state Source Memory State Block
Program Counter
• Guest memory and Condition Codes
context block is kept in Code
Reg 0
interpreter’s memory (heap) Reg 1

• code and data Data ……

Reg n-1
• general-purpose registers,
PC, CC, control registers

Stack Interpreter Code

Interpreter Overview
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 Decode-and-dispatch interpreter
Interpretation repeats
ƒ Decodes an instruction
ƒ Dispatches it to an interpretation routine based on the type of
instruction
ƒ Code for interpreting PPC ISA
While (!halt && interrupt){
inst=code[PC];
opcode=extract(inst,31,6);
switch(opcode){
case LoadWordAndZero: LoadWordAndZero(inst);
case ALU: ALU(inst);
case Branch: Branch(inst);
· · · · ·
}

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Instruction Functions

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Instruction Functions

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 Decode-and-dispatch interpreter
ƒ Advantage
• Low memory requirements
• Zero star-up time
ƒ Disadvantage:
• Steady-state performance is slow
- A source instruction must be parsed each time it is emulated
- Lots of branches would degrade performance

ƒ How many branches are there in our interpreter code?

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 Branches in Decode-&-Dispatch
While (!halt&&interrupt){
switch(opcode){
case ALU:ALU(inst); Switch(opcode)
·····
} 1.Switch statement->case Indirect
2.ALU(inst) case direct
3.Return from the routine Indirect
4.Loop back-edge direct
return

We can remove all of these branches with threading

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 Threaded Interpretation: Idea
„ Put the dispatch code to the end of each interpretation routine.
Instruction function list
Add:
RT=extract(inst,25,5);
RA=extract(inst,20,5);
RB=extract(inst,15,5);
source1=regs[RA];
source2=regs[RB];
sum=source1+source2;
regs[RT]=sum;
PC=PC+4;
If (halt || interrupt) goto exit;
inst=code[PC];
opcode=extract(inst,31,6);
extended_opcode=extract(inst,10,10);
routine=dispatch[opcode,extended_opcode];
goto *routine;
}

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Threaded Interpretation (2)

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Threaded Interpretation (3)

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 Threaded Interpretation
ƒ One key point is that dispatch occurs indirectly thru a
dispatch table

routine = dispatch[opcode,extended_opcode];
goto *routine;

ƒ Also called indirect threaded interpretation

ƒ Then, what would be directed threaded interpretation?
ƒ Can we remove the overhead of accessing the table?
ƒ Solution: predecoding and direct threading

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 Predecoding
ƒ Extracting various fields of an instruction is complicated
• Fields are not aligned, requiring complex bit extraction
• Some related fields needed for decoding is not adjacent
ƒ If it is in a loop, this extraction job should be repeated

ƒ How can we reduce this overhead? Predecoding

• Pre-parsing instructions in a form that is easier to interpreter
• Done before interpretation starts
• Predecoding allows direct threaded interpretation

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 Predecoding for PPC
ƒ In PPC, opcode & extended opcode field are separated and register
specifiers are not byte-aligned
ƒ Define instruction format and define an predecode instruction array
based on the format
Struct instruction {
unsigned long op; // 32 bit
unsigned char dest; // 8 bit
unsigned char src1; // 8 bit
unsigned int src2; // 16 bit
} code [CODE_SIZE];

ƒ Pre-decode each instruction based on this format

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Predecoding Example

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Previous Interpreter Code

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New Interpreter Code

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 Directed Threaded Interpretation
ƒ Even with predecoding, indirect threading includes a centralized
dispatch table, which requires
• Memory access and indirect jump
ƒ To remove this overhead, replace the instruction opcode in predecoded
format by address of interpreter routine

07 001048d0
1 2 08 1 2 08

If (halt || interrupt) goto exit; If (halt || interrupt) goto exit;

opcode= code[TPC].op; routine= code[TPC].op;
routine=dispatch [opcode]; goto *routine;
goto *routine;
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 Comparison
Dispatch-&-Decode Indirect Threaded
source code source code interpreter routines source code interpreter routines

dispatch loop

Indirection Table
(a) (b ) ( c)

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 Comparison
Predecoded Indirect Threaded Direct Threaded

Indirection Table
Predecoder

(d) (e)

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 Comparison
Decode-and- Indirect Threaded Direct Threaded
Dispatch Interpreter Interpreter

Memory Low Low High

requirements

Start-up Fast Fast Slow

performance

Steady-state Slow Slow Medium

performance (better than the first one)

Code portability Good Good Medium

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 DSVM
ƒ Dynamic Samsung Virtual Machine
ƒ Splitted interpreter
• Inner, Outer loop
• Instruction cache
ƒ Indirect threaded interpretation

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 Interpreting CISC ISA
ƒ RISC ISA (Power PC) 32 bit register. 32bit length.
31 25 20 15 10 0

Register-register Op Rd Rs1 Rs2 Opx

31 25 20 15 0
Register-immediate Op Rd Rs1 Const

Jump/call Op Const opx

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 Interpreting a Complex Instruction Set
CISC instruction set has a wide variety of formats, variable instruction
lengths, and variable field lengths (x86 instruction lengths: 1 ~ 16 bytes)

IA-32 Instruction Format

Prefixes Opcode ModR/M SIB Displacement Immediate

Up to four 1-,2-,or 3-byte 1byte 1byte Address Immediate

Prefixes of opcode (if required) (if required) Displacement data
1 byte each Of 1,2,or 4 Of 1,2,or 4
(optional) Bytes or none Bytes or none

7 6 5 3 2 0 7 6 5 3 2 0
Mod Reg/ R/M Scale Index Base
Opcode

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Interpreting a Complex Instruction Set
ƒ Decode and dispatch
• Decode fields and fill in a
general template General
• Jump to routines Decode
(fill-in instruction
ƒ Slow due to generality
Structure)
ƒ Solution
• Make common case faster

Dispatch

Inst.1 Inst.1 Inst.1

Specialized Specialized Specialized
routine routine routine

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 Some optimizations
Dispatch
On
first byte

Simple Simple Complex Complex

Inst.1 Inst.m Inst.m+1 Inst.m+1 Prefix
Specialized Specialized Specialized Specialized Set flags
routine routine routine routine

Shared
routines

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 Threaded Interpretation

Complex
Decode/
Dispatch

Simple Simple Simple Simple

Instruction Instruction Instruction Instruction
Specialized Specialized Specialized Specialized
routine routine routine routine
Simple Simple Simple Simple
Decode/ Decode/ Decode/ Decode/
Dispatch Dispatch Dispatch Dispatch

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