2024-10-10

Digital Design
Chapter 2: Introduction to Verilog HDL
Structural Model
Duong Ngoc Phap, Ph.D
Faculty of Computer Engineering and Electronics
Use some slides from ITI-VNU and Dr. Pham Quoc Cuong [email protected])
October 10,
2024

Boolean Algebra Review

• Developed by George Boole
– in his book (a treatise): “An Investigation of the Laws of Thought”
– no application was made of Boolean Algebra until the late 1930s
– Nakashima in Japan (1937) and Shannon at MIT (1938), each independently applied the
algebra of Boole to the analysis of networks of relays (in telephone systems).

October 10, 2024 Introduction to Verilog - Structural Model 2/97

1
 2024-10-10

The Huntington postulates

• In 1904, Huntington found that
– all of the results and implications of the algebra described by Boole could be derived from
only six basic postulates.

• Huntington postulates: The set {B, +, ·, ¯ }

– B is the set of elements or constants of the algebra
– the symbols + and · are two binary operators(*)
– the overbar ¯is a unary operator(*)

is a Boolean algebra if the following hold true:

(*) The terms binary operator and unary operator refer to the number of arguments involved
in the operation: two or one, respectively.

October 10, 2024 Introduction to Verilog - Structural Model 3/97

The Huntington postulates

1. Closure (khép kín)
For all elements a and b in the set B,
• a+bB
• a·bB
2. Existing 0 and 1 elements
– There exists a 0 element in B such that
for every element a in B, 0 + a = a + 0 = a
– There exists a 1 element in B such that
for every element a in B, a = a · 1 = a

October 10, 2024 Introduction to Verilog - Structural Model 4/97

2
 2024-10-10

The Huntington postulates

3. Commutativity (giao hoán)
– a+b=b+a
– a·b=b·a

4. Distributivity (phân phối)

– a · (b + c) = a · b + a · c
– a + (b · c) = (a + b) · (a + c)

October 10, 2024 Introduction to Verilog - Structural Model 5/97

The Huntington postulates

5. a  B, there exists an element a-bar in the set B such
that
a  a 1
aa  0

6. There exists at least two distinct elements in B

Switching algebra is a Boolean algebra in which the number

of elements in the set B is precisely 2.

October 10, 2024 Introduction to Verilog - Structural Model 6/97

3
 2024-10-10

Switching Algebra

• is a Boolean algebra in which the number of elements in the set B is precisely 2

• The two binary operators, represented by the signs + and ·, are called the OR and
the AND, respectively.
• The unary operator, represented by the overbar ¯, is called the NOT or the
complement operator.

October 10, 2024 Introduction to Verilog - Structural Model 7/97

Algebra Implications
• Theorem 1 – idempotence (i) aa a
(Địnhlý hấp thụ)
(ii) aa  a
Proof
a 𝑎  a  a 1 P-2(ii) aa  aa  0 P-2(i)

 a  a  a  a  P-5(i)  aa  aa P-5(ii)

 a  aa P-4(ii)  a  a  a  P-4(i)

a0 P-5(ii)  a 1 P-5(i)

a P-2(i) a P-2(ii)

October 10, 2024 Introduction to Verilog - Structural Model 8/97

4
 2024-10-10

Algebra Implications
• Theorem 2 (i) a0  0a  0
(ii) a 1  1 a  1
Proof

a 0  0  a  0 P-2(i) a 1 P-2(ii)

 a  a  a.0 P-5(ii)
Principle
P-5(i)

of duality
 a  (a+0) P-4(i) P-4(ii)

 a.a P-2(i) P-2(ii)

 P-5(ii) P-5(i)

 Exercise for students

October 10, 2024 Introduction to Verilog - Structural Model 9/97

Algebra Implications
• Theorem 3
Let a be an element of B. Then a-bar is unique.
Proof

Assume that a has 2 distinct complements

(not equal), a-bar and b. Then by P-5, we
a  a 1 b  b 1 P-2(ii)

must have that:  a  (a  b)  b(a  a )

a b 1  a  a  a b  ba  ba P-4(i)
and a  a 1
and  0  a b  0  ba
 a b  a b P-2(i)
a b  0 and aa  0

a b
October 10, 2024 Introduction to Verilog - Structural Model 10/97

5
 2024-10-10

Algebra Implications – Basic logic

operations
• From this point, we will restrict our attention to switching algebras only.
– Switching algebra is basically a two-element Boolean algebra which, obviously, has
the two elements 0 and 1.

• AND operation
Symbols
x y z=x·y
x
0 0 0 Theorem 1(ii) z
y
0 1 0 Theorem 2(i)
1 0 0 Postulate 3(ii) x
z
1 1 1 Theorem 1(ii) y 

October 10, 2024 Introduction to Verilog - Structural Model 11/97

Algebra Implications – Basic logic

operations
• OR operation Symbols

x
x y z=x+y z
Derived from which y
0 0 0
theorem, postulate?
0 1 1
x z
1 0 1 Exercise for Students 1
y
1 1 1

• NOT operation Symbols

Derived from which x z

x z = x-bar
0 1 theorem, postulate?

1 0 Exercise for Students x z

1

October 10, 2024 Introduction to Verilog - Structural Model 12/97

6
 2024-10-10

Algebra Implications – Basic logic

operations
• NAND operation
x y z=x·y
0 0 1 Symbols

0 1 1 x
z
y
1 0 1
1 1 0
x
z
y 
• NOR operation
Symbols
x y z=x+y x
z
0 0 1 y
0 1 0
x z
1 0 0 y 1
1 1 0

October 10, 2024 Introduction to Verilog - Structural Model 13/97

Algebra Implications – Basic logic

operations
• XOR operation
Symbols
x y z=xy
x
0 0 0 z
y
0 1 1
1 0 1 x
z
y =1
1 1 0

z  x y 

- Construct XOR gate from NOT, AND, and OR ?

October 10, 2024 Introduction to Verilog - Structural Model 14/97

7
 2024-10-10

Algebra Implications – Basic logic

operations
• NXOR operation
Symbols
x y z=xy
x
0 0 1 z
y
0 1 0
1 0 0 x
z
y =1
1 1 1

z  x  y  x.y  x.y
- Construct NXOR gate from NOT, AND, and OR ?

October 10, 2024 Introduction to Verilog - Structural Model 15/97

Algebra Implications
• Theorem 4 – Involution
Định lý phủ định của phủ định
x   x
Let x be a switching variable. Then
Proof

Since the left column is identical to the right

column and we have listed all possibilities,

we have proved the result.

October 10, 2024 Introduction to Verilog - Structural Model 16/97

8
 2024-10-10

Algebra Implications
• Theorem 5
Let x and y be two switching variables.
Then (i) x  x  y  x

Proof
(ii) x  x  y   x

x y x y x + x y
0 0 0 0 + 0 0
0 1 0 0 + 0 0
1 0 0 1 + 0 1
1 1 1 1 + 1 1

October 10, 2024 Introduction to Verilog - Structural Model 17/97

Algebra Implications

October 10, 2024 Introduction to Verilog - Structural Model 18/97

9
 2024-10-10

Algebra Implications – De Morgan’s

Theorem

October 10, 2024 Introduction to Verilog - Structural Model 19/97

Algebra Implications – De Morgan’s

Theorem
• Used for the evaluation of complements of switching
expressions.

– For example,
x  y  z  w   x  y  z  w 

 x  y  z  w  
 x  y  z  w 
 x  y  z  w 
 x y  xzw
October 10, 2024 Introduction to Verilog - Structural Model 20/97

10
 2024-10-10

Algebra Implications – De Morgan’s

Theorem

October 10, 2024 Introduction to Verilog - Structural Model 21/97

Truth tables
• Truth table
– a simple way of representing a switching function is to make a list of the possible variable
assignments and note the value the function takes on for each assignment. This list is
called Truth Table.

• How to create the Truth Table of a switching function?

– For example, F ( x, y, z)  x  yz

October 10, 2024 Introduction to Verilog - Structural Model 22/97

11
 2024-10-10

Truth tables
F ( x, y, z)  x  yz
x y z F (x, y, z)
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
2n assignment 1 0 0 0
possibilities 1 0 1 0
1 1 0 1
1 1 1 0

- Write the Truth Table for the following switching function: F (x, y, z) = x yz  x y

October 10, 2024 Introduction to Verilog - Structural Model 23/97

Truth tables
• Find a switching function from a truth table

x y F (x, y)

0 0 0 F (x, y) ???
0 1 0

1 0 0
1 1 1

October 10, 2024 Introduction to Verilog - Structural Model 24/97

12
 2024-10-10

Canonical forms: Minterm - Maxterm

• Alternatives to the tabular representation
– To list only the assignments for which a function is 1 or,
– To list those for which the function is 0

 Canonical representation

x y F (x, y)
– F = 1 whenever x = 1 and y = 1 0 0 0

F ( x, y )  xy 0 1 0
1 0 0
1 1 1

October 10, 2024 Introduction to Verilog - Structural Model 25/97

Canonical forms: Minterm - Maxterm

• Sum of Products (SOP) expression
x y z F (x, y, z) If a product term involves all the
0 0 0 0 variables of a function, it is
0 0 1 1 referred to as a Minterm
0 1 0 1
0 1 1 0 A SOP is made of minterms only is
1 0 0 0 called a canonical minterm
1 0 1 1 expression or expansion of the
1 1 0 0
function F(x, y, z)
1 1 1 0

F ( x, y , z )  x y z  x yz  xy z

October 10, 2024 Introduction to Verilog - Structural Model 26/97

13
 2024-10-10

Canonical forms: Minterm - Maxterm

• Sum of Products (SOP) expression
x y z F (x, y, z) Write the SOP expression and simplify the
0 0 0 1 function !
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0

October 10, 2024 Introduction to Verilog - Structural Model 27/97

Canonical forms: Minterm - Maxterm

• Product of Sums (POS) expression
x y z F (x, y, z)
0 0 0 1
F ( x, y, z)  xyz  xyz  xyz
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
F ( x, y, z)  F ( x, y, z) 
1 0 1 0
1 1 0 1  xyz  xyz  xyz
1 1 1 0  xyz  xyz  xyz
 ( x  y  z)( x  y  z )( x  y  z )
 x  yz
October 10, 2024 Introduction to Verilog - Structural Model 28/97

14
 2024-10-10

Canonical forms: Minterm - Maxterm

• Product of Sums (POS) expression
x y z F (x, y, z)
0 0 0 0
F ( x, y, z)  F ( x, y, z)
0 0 1 1
0 1 0 0  xyz  xyz  xyz  xyz  xyz
0 1 1 0  ( x  y  z)( x  y  z)( x  y  z )
1 0 0 0
( x  y  z)( x  y  z )
1 0 1 1
1 1 0 1
Each sum term involves all the
1 1 1 0
variables of a function is called a
Maxterm

October 10, 2024 Introduction to Verilog - Structural Model 29/97

Conversion of SOP and POS

expressions to canonical forms

October 10, 2024 Introduction to Verilog - Structural Model 30/97

15
 2024-10-10

Conversion of SOP and POS

expressions to canonical forms

October 10, 2024 Introduction to Verilog - Structural Model 31/97

Conversion of SOP and POS

expressions to canonical forms
F ( A, B, C )  A B  AC
 A B 1  A 1 C
 A B(C  C )  A(B  B )C
  m(3, 2, 7, 5)
 ABC  ABC  ABC  ABC   M (0, 1, 4, 6)

F ( A, B, C )  ( A  B  C )( A  B  C )( A  B  C )( A  B  C )

October 10, 2024 Introduction to Verilog - Structural Model 32/97

16
 2024-10-10

Example
• Construct a XOR gate from NOR and NOT gates ?
z  x  y  xy  xy
• Construct a XOR gate from NAND and NOT gates ?

October 10, 2024 Introduction to Verilog - Structural Model 33/97

Simplification of Switching Functions

• Hardware cost of an equation

– Related to the number of terms and the number of literals in each term of the
expression.
• The complexity of an equation should be reduced.

• Three fundamental approaches can be used to simplify switching

expressions
– Use postulates and other results to reduce the form of an expression algebraically.
(require a good deal of experience)
– Use Karnaugh map (group of minterms are easily identified, limited variables)
– Quine-McCluskey algorithm
October 10, 2024 Introduction to Verilog - Structural Model 34/97

17
 2024-10-10

Simplification of Switching Functions

• Algebraic Manipulation
– Simplified expression: contains a minimal number of literals
and terms
• Minimal SOP, Minimal POS
– All theorems and postulates are used to find the minimal form
• Depend on your experience !!!
– 3 basic results are usually used for minimizing SOP
expressions:
Result 1: xy  xy  y (Verified using Distributivity)

Result 2 : x  xy  x  y Theorem 6, part 2(i)

Result 3 : xz  xy  yz  xz  xy Theorem 6, part 3(i) (consensus)

October 10, 2024 Introduction to Verilog - Structural Model 35/97

Simplification of Switching Functions

• Algebraic Manipulation (cont’d)

October 10, 2024 Introduction to Verilog - Structural Model 36/97

18
 2024-10-10

Simplification of Switching Functions

October 10, 2024 Introduction to Verilog - Structural Model 37/97

Simplification of Switching Functions

• Algebraic Manipulation (cont’d)
– Example:

x  y  z  y (w  z)  xz  ( x  xz )  [ y  y (w  z)]  z
Result 1 : xy  xy  y
 xz yw zz
Result 2 : x  xy  x  y
Result 3 : xz  xy  yz  xz  xy

None of the listed results can be applied for the above expression.
It’s OK or NOT yet ?

Attention: z  z 1
 The above expression should equal 1

October 10, 2024 Introduction to Verilog - Structural Model 38/97

19
 2024-10-10

Simplification of Switching Functions

• Prime implicants
– An implicant is a "covering" (sum term or product term) of one or more minterms in a
sum of products (or maxterms in a product of sums) of a boolean function.

– In an SOP expression, each of the product terms  an implicant of the function if it

implies the function (e.g., if the product term is 1 then the function is also 1).

October 10, 2024 Introduction to Verilog - Structural Model 39/97

Simplification of Switching Functions

• Prime implicants
h(w, x, y, z)  wxyz  wxyz  wxyz  wxyz
 Each of the minterm is an implicant.

 w(xyz  xyz)  w(xyz  xyz) Smaller in

 xyz  xyz  Each of these products is term of the

also an implicant. number of
literals
 yz  is also an implicant.

A prime implicant of a function is an implicant that cannot be covered by a more

general (more reduced - meaning with fewer literals) implicant.

October 10, 2024 Introduction to Verilog - Structural Model 40/97

20
 2024-10-10

Simplification of Switching Functions

• Minimal expression
– Any other expression having fewer terms and literals will not represent the original
function.

• Minimal SOP = minimal expression in SOP form

• Minimal POS = minimal expression in POS form

October 10, 2024 Introduction to Verilog - Structural Model 41/97

Simplification of Switching Functions

• Karnaugh map
– M. Karnaugh published an article describing a geometrical method for
finding a minimal closed cover (1953)  Karnaugh map method
– Based on mapping minterms onto a surface in such a way that minterms
that differ in one literal are adjacent to each other on the surface.
• Reason: when 2 minterms differ in one literal, they can be combined to form a product
term which has this literal missing.
– For example, ĀBC and ABC differ in only one literal (Ā and A)  the sum
reduces to

A BC  ABC  BC

October 10, 2024 Introduction to Verilog - Structural Model 42/97

21
 2024-10-10

Simplification of Switching Functions

• Karnaugh map
B
– All minterms in the column labeled B contain the literal B, all A AB
those in the other column contain B-bar. Similar for the rows
1 0

– 1 in each square corresponds to a minterm of the function f

A 1 1
– Prime implicants can be found by grouping the 1 cells into as
AB A
large a block of adjacent cells as possible.
f ( A, B)
– For example, the pair of cells AB and A group together to
give B  AB  A B
 B (A  A)
B

October 10, 2024 Introduction to Verilog - Structural Model 43/97

Simplification of Switching Functions

• Karnaugh map
B
– 1-cube: a single square B
– 2-cube: two adjacent squares are taken together
1 0
– 4-cube: two adjacent 2-cubes or two 2-cubes have a long edge in
common.
– The largest cube of 1s represent the prime implicants. A 1 1
– In the figure, the prime implicants are A and B therefore: A
f ( A, B)  A  B f ( A, B)

How do we achieve the minimal SOP from minterm SOP expression?

October 10, 2024 Introduction to Verilog - Structural Model 44/97

22
 2024-10-10

Simplification of Switching Functions

• Karnaugh map for 3 variables
– Two 2-variable Karnaugh map are placed side by side after reflecting one of
the two 2-variable maps  get a 3-variable map

xyz xyz y
xyz
xyz
0 1 1 1

x 1 1 1 1
xyz

xyz z xyz
xyz

October 10, 2024 Introduction to Verilog - Structural Model 45/97

Simplification of Switching Functions

y w
• Karnaugh map for 4 variables
– Two 3-variable Karnaugh map are
placed side by side after reflecting
one of the two 3-variable maps 
get a 4-variable map
w

– How to find prime implicants for the x

dash boxes ? z
w

y
z

October 10, 2024 Introduction to Verilog - Structural Model 46/97

23
 2024-10-10

Simplification of Switching Functions

• Karnaugh map examples
– Simples examples for Karnaugh map
– Timing Hazards
– Karnaugh map examples with timing hazards

October 10, 2024 Introduction to Verilog - Structural Model 47/97

Delay in gate networks (cont’d)

• Generation of a “glitch” in a combinational circuit.

October 10, 2024 Introduction to Verilog - Structural Model 48/97

24
 2024-10-10

Delay in gate networks (cont’d)

October 10, 2024 Introduction to Verilog - Structural Model 49/97

October 10, 2024 Introduction to Verilog - Structural Model 50/97

25
 2024-10-10

October 10, 2024 Introduction to Verilog - Structural Model 51/97

AB A
CD

1 1
D
z
1 1
C
1 1

October 10, 2024 Introduction to Verilog - Structural Model 52/97

26
 2024-10-10

2-bit parallel comparator ADC

𝑉ref = 4V

10k

3V
A3

Mã nhị phân lối ra

10k
D1 Hãy thiết kế
𝑉 Bộ lập
A2
mạch điện cho
2V
mã bộ lặp mã ưu
D0
10k A1 ưu tiên tiên?

1V
10k

GND

October 10, 2024 Introduction to Verilog - Structural Model 53/97

Overview of HDLs
• Hardware description languages (HDLs)
– Are computer-based hardware description languages
– Allow modeling and simulating the functional behavior and timing of digital
hardware
– Synthesis tools take an HDL description and generate a technology-specific
netlist
• Two main HDLs used by industry
– Verilog HDL (C-based, industry-driven)
– VHSIC HDL or VHDL (Ada-based,
defense/industry/university-driven).

October 10, 2024 Introduction to Verilog - Structural Model 54/97

27
 2024-10-10

Synthesis of HDLs
• Takes a description of what a circuit DOES
• Creates the hardware to DO it
• HDLs may LOOK like software, but they’re not!
– NOT a program
– Doesn’t “run” on anything
• Though we do simulate them on computers
– Don’t confuse them!

• Also use HDLs to test the hardware you create

– This is more like software
October 10, 2024 Introduction to Verilog - Structural Model 55/97

Describing Hardware!
• All hardware created during
synthesis if (a) f = c & d;
else if (b) f = d;
– Even if a is true, still else f = d & e;
computing d&e

• Learn to understand how

descriptions translated to
c
hardware f
d
e

b a
October 10, 2024 Introduction to Verilog - Structural Model 56/97

28
 2024-10-10

Why Use an HDL?

• More and more transistors can fit on a chip
– Allows larger designs!
– Work at transistor/gate level for large designs: hard
– Many designs need to go to production quickly
• Abstract large hardware designs!
– Describe what you need the hardware to do
– Tools then design the hardware for you

October 10, 2024 Introduction to Verilog - Structural Model 57/97

Why Use an HDL?

• Simplified & faster design process
• Explore larger solution space
– Smaller, faster, lower power
– Throughput vs. latency
– Examine more design tradeoffs
• Lessen the time spent debugging the design
– Design errors still possible, but in fewer places
– Generally easier to find and fix
• Can reuse design to target different technologies
– Don’t manually change all transistors for rule change

October 10, 2024 Introduction to Verilog - Structural Model 58/97

29
 2024-10-10

Other Important HDL Features

• Are highly portable (text)
• Are self-documenting (when commented well)
• Describe multiple levels of abstraction
• Represent parallelism
• Provides many descriptive styles
– Structural
– Register Transfer Level (RTL)
– Behavioral
• Serve as input for synthesis tools

October 10, 2024 Introduction to Verilog - Structural Model 59/97

Verilog
• In this class, we will use the Verilog HDL
– Used in academia and industry
• VHDL is another common HDL
– Also used by both academia and industry

• Many principles we will discuss apply to any HDL

• Once you can “think hardware”, you should be able
to use any HDL fairly quickly

October 10, 2024 Introduction to Verilog - Structural Model 60/97

30
 2024-10-10

Verilog Module
• In Verilog, a circuit is a module. A[1:0]
2

module decoder_2_to_4 (A, D) ; Decoder

2-to-4
input [1:0] A ;
output [3:0] D ; 4

assign D = (A == 2'b00) ? 4'b0001 : D[3:0]

(A == 2'b01) ? 4'b0010 :
(A == 2'b10) ? 4'b0100 :
(A == 2'b11) ? 4'b1000 ;
endmodule

October 10, 2024 Introduction to Verilog - Structural Model 61/97

Verilog Module
A[1:0]
module name ports names of
module 2

module decoder_2_to_4 (A, D) ; Decoder

2-to-4
port input [1:0] A ; port
types sizes
output [3:0] D ; 4

assign D = (A == 2'b00) ? 4'b0001 : D[3:0]

(A == 2'b01) ? 4'b0010 :
(A == 2'b10) ? 4'b0100 :
module
(A == 2'b11) ? 4'b1000 ; contents
endmodule
keywords underlined
October 10, 2024 Introduction to Verilog - Structural Model 62/97

31
 2024-10-10

Declaring A Module
• Can’t use keywords as module/port/signal names
– Choose a descriptive module name

• Indicate the ports (connectivity)

• Declare the signals connected to the ports

– Choose descriptive signal names

• Declare any internal signals

• Write the internals of the module (functionality)

October 10, 2024 Introduction to Verilog - Structural Model 63/97

Declaring Ports
• A signal is attached to every port

• Declare type of port

– input
– output
– inout (bidirectional)

• Scalar (single bit) - don’t specify a size

– input cin;

• Vector (multiple bits) - specify size using range

– Range is MSB to LSB (left to right)
– Don’t have to include zero if you don’t want to… (D[2:1])
– output [7:0 ] OUT;
– input [1:0] IN;

October 10, 2024 Introduction to Verilog - Structural Model 64/97

32
 2024-10-10

Module Styles
• Modules can be specified different ways
– Structural – connect primitives and modules (Gate-level model)
– RTL – use continuous assignments (Dataflow model)
– Behavioral – use initial and always blocks (Behavioral model)
• A single module can use more than one method!

• What are the differences?

October 10, 2024 Introduction to Verilog - Structural Model 65/97

Structural
• A schematic in text form
• Build up a circuit from gates/flip-flops
– Gates are primitives (part of the language)
– Flip-flops themselves described behaviorally
• Structural design
– Create module interface
– Instantiate the gates in the circuit
– Declare the internal wires needed to connect gates
– Put the names of the wires in the correct port locations of
the gates
• For primitives, outputs always come first

October 10, 2024 Introduction to Verilog - Structural Model 66/97

33
 2024-10-10

Structural Example

module majority (major, V1, V2, V3) ;

output major ;
input V1, V2, V3 ; V1 N1
A0
V2
wire N1, N2, N3;

and A0 (N1, V1, V2), V2 N2

A1 Or0 major
A1 (N2, V2, V3), V3
A2 (N3, V3, V1);
V3 N3
or Or0 (major, N1, N2, N3); A2
V1
endmodule majority

October 10, 2024 Introduction to Verilog - Structural Model 67/97

RTL Example

module majority (major, V1, V2, V3) ;

output major ;
input V1, V2, V3 ;
V1
assign major = V1 & V2
| V2 & V3 V2 Majority major
| V1 & V3;
endmodule V3

October 10, 2024 Introduction to Verilog - Structural Model 68/97

34
 2024-10-10

Behavioral Example

module majority (major, V1, V2, V3) ;

output reg major ;

input V1, V2, V3 ;

always @(V1, V2, V3) begin V1

if (V1 & V2 | V2 & V3
| V1 & V3) major = 1; V2 Majority major
else major = 0;
end V3

endmodule

October 10, 2024 Introduction to Verilog - Structural Model 69/97

Adder Example

October 10, 2024 Introduction to Verilog - Structural Model 70/97

35
 2024-10-10

Full Adder: Structural

module half_add (X, Y, S, C); module full_add (A, B, CI, S, CO) ;

input X, Y ; input A, B, CI ;
output S, C ; output S, CO ;

xor SUM (S, X, Y); wire S1, C1, C2;

and CARRY (C, X, Y);
// build full adder from 2 half-adders
endmodule half_add PARTSUM (A, B, S1, C1);
hafl_add SUM (S1, CI, S, C2);

// … and an OR gate for the carry

or CARRY (CO, C2, C1);

endmodule
October 10, 2024 Introduction to Verilog - Structural Model 71/97

Full Adder: RTL/Dataflow

module fa_rtl (A, B, CI, S, CO) ;

input A, B, CI ;
output S, CO ;

// use continuous assignments

assign S = A ^ B ^ CI;
assign C0 = (A & B) | (A & CI) | (B & CI);

endmodule

October 10, 2024 Introduction to Verilog - Structural Model 72/97

36
 2024-10-10

Full Adder: Behavioral

• Circuit “reacts” to given events (for simulation)
– Actually list of signal changes that affect output
module fa_bhv (A, B, CI, S, CO) ;

input A, B, CI;
output S, CO;
reg S, CO; // explained in later lecture – “holds” values

// use procedural assignments

always@(A or B or CI)
begin
S = A ^ B ^ CI;
CO = (A & B) | (A & CI) | (B & CI);
end
endmodule
October 10, 2024 Introduction to Verilog - Structural Model 73/97

Full Adder: Behavioral

• IN SIMULATION
– When A, B, or C change, S and CO are recalculated
• IN REALITY
– Combinational logic – no “waiting” for the trigger
– Constantly computing - think transistors and gates!
– Same hardware created for this and RTL example
A
always@(A or B or CI) S
B
begin
S = A ^ B ^ CI; CI
majority CO
CO = (A & B) | (A & CI) | (B & CI);
end
fa_bhv
October 10, 2024 Introduction to Verilog - Structural Model 74/97

37
 2024-10-10

Structural Basics: Primitives

• Build design up from the gate/flip-flop/latch level
– Flip-flops actually constructed using Behavioral
• Verilog provides a set of gate primitives
– and, nand, or, nor, xor, xnor, not, buf, bufif1, etc.
– Combinational building blocks for structural design
– Known “behavior”
– Cannot access “inside” description
• Can also model at the transistor level
– Most people don’t, we won’t

October 10, 2024 Introduction to Verilog - Structural Model 75/97

Primitives
• No declarations - can only be instantiated
• Output port appears before input ports
• Optionally specify: instance name and/or delay
(discuss delay later)

and N25 (Z, A, B, C); // name specified

and #10 (Z, A, B, X),
(X, C, D, E); // delay specified, 2 gates
and #10 N30 (Z, A, B); // name and delay specified

October 10, 2024 Introduction to Verilog - Structural Model 76/97

38
 2024-10-10

Verilog Primitives
• 26 pre-defined primitives
• Output is the first port
n-output
n-input output ending mark
3-states
and buf nand (y, a, b, c);
nand not input
keyword name
or bufif0
nor bufif1
xor notif0 nand N1(y, a, b, c);
xnor notif1
instance name (optional)

October 10, 2024 Introduction to Verilog - Structural Model 77/97

Syntax For Structural Verilog

• First declare the interface to the module
– Module keyword, module name
– Port names/types/sizes
• Next, declare any internal wires using “wire”
– wire [3:0] partialsum;
• Then instantiate the primitives/submodules
– Indicate which signal is on which port

October 10, 2024 Introduction to Verilog - Structural Model 78/97

39
 2024-10-10

Again: Structural Example

module majority (major, V1, V2, V3) ;

output major ;
input V1, V2, V3 ; V1 N1
A0
V2
wire N1, N2, N3;

and A0 (N1, V1, V2), V2 N2

A1 Or0 major
A1 (N2, V2, V3), V3
A2 (N3, V3, V1);
V3 N3
or Or0 (major, N1, N2, N3); A2
V1
endmodule majority

October 10, 2024 Introduction to Verilog - Structural Model 79/97

Example
• Using the Verilog structural style, describe the
following circuit

October 10, 2024 Introduction to Verilog - Structural Model 80/97

40
 2024-10-10

Example: Combinational Gray code

S2’ = Rst S2 S0 + Rst S1 S0

S1’ = Rst S2 S0 + Rst S1 S0

S0’ = Rst S2 S1 + Rst S2 S1

October 10, 2024 Introduction to Verilog - Structural Model 81/97

Datatypes
• Two categories
– Nets
– “Registers”
• Only dealing with nets in structural Verilog
• “Register” datatype doesn’t actually imply an actual
register…
– Will discuss this when we discuss Behavioral Verilog

October 10, 2024 Introduction to Verilog - Structural Model 82/97

41
 2024-10-10

Net Types
• wire: most common, establishes connections
– Default value for all signals
• tri: indicates will be output of a tri-state
– Basically same as “wire”
• supply0, supply1: ground & power connections
– Can imply this by saying “0” or “1” instead
– xor xorgate(out, a, 1’b1);
• wand, wor, triand, trior, tri0, tri1, trireg
– Perform some signal resolution or logical operation
– Not used in this course

October 10, 2024 Introduction to Verilog - Structural Model 83/97

Structural Verilog: Connections

• “Positional” or “Implicit” port connections
– Used for primitives (first port is output, others inputs)
– Can be okay in some situations
• Designs with very few ports
• Interchangeable input ports (and/or/xor gate inputs)
– Gets confusing for large #s of ports
• Can specify the connecting ports by name
– Helps avoid “misconnections”
– Don’t have to remember port order
– Can be easier to read
– .<port name>(<signal name>)

October 10, 2024 Introduction to Verilog - Structural Model 84/97

42
 2024-10-10

Connections Examples
• Variables – defined in upper level module
– wire [3:2] X; wire W_n; wire [3:0] word;
• By position
– module dec_2_4_en (A, E_n, D);
– dec_2_4_en DX (X[3:2], W_n, word);
• By name
– module dec_2_4_en (A, E_n, D);
– dec_2_4_en DX (.E_n(W_n), .A(X[3:2]), .D(word));
• In both cases,
A = X[3:2], E_n = W_n, D = word

October 10, 2024 Introduction to Verilog - Structural Model 85/97

Empty Port Connections

• Example: module dec_2_4_en(A, E_n, D);
– dec_2_4_en DX (X[3:2], , word); // E_n is high impedence (z)
– dec_2_4_en DX (X[3:2], W_n , ); // Outputs D[3:0] unused.

• General rules
– Empty input ports => high impedance state (z)
– Empty output ports => output not used
• Specify all input ports anyway!
– Usually don’t want z as input
– Clearer to understand & find problems
• Helps if no connection to name port, but leave empty:
– dec_2_4_en DX(.A(X[3:2]), .E_n(W_n), .D());

October 10, 2024 Introduction to Verilog - Structural Model 86/97

43
 2024-10-10

Hierarchy
• Any Verilog design you do will be a module
• This includes testbenches!

• Interface (“black box” representation)

– Module name, ports
• Definition
– Describe functionality of the block
– Includes interface
• Instantiation
– Use the module inside another module

October 10, 2024 Introduction to Verilog - Structural Model 87/97

Hierarchy
• Build up a module from smaller pieces
– Primitives
– Other modules (which may contain other modules)
• Design: typically top-down
• Verification: typically bottom-up
Full Adder Hierarchy Add_full

Add_half Add_half or

xor and xor and

October 10, 2024 Introduction to Verilog - Structural Model 88/97

44
 2024-10-10

Add_half Module
Add_half

xor and

module Add_half(c_out, sum, a, b);

output sum, c_out;
input a, b;

xor sum_bit(sum, a, b);

and carry_bit(c_out, a, b);
endmodule

October 10, 2024 Introduction to Verilog - Structural Model 89/97

Add_full Module
Add_full

Add_half Add_half or

module Add_full(c_out, sum, a, b, c_in) ;

output sum, c_out;
input a, b, c_in;
wire w1, w2, w3;

Add_half AH1(.sum(w1), .c_out(w2), .a(a), .b(b));

Add_half AH2(.sum(sum), .c_out(w3), .a(c_in), .b(w1));
or carry_bit(c_out, w2, w3);
endmodule

October 10, 2024 Introduction to Verilog - Structural Model 90/97

45
 2024-10-10

Can Mix Styles In Hierarchy!

module Add_half_bhv(c_out, sum, a, b);
output reg sum, c_out;
input a, b; module Add_full_mix(c_out, sum, a, b, c_in) ;
always @(a, b) begin output sum, c_out;
input a, b, c_in;
sum = a ^ b; c_out = a & b; wire w1, w2, w3;
Add_half_bhv AH1(.sum(w1), .c_out(w2),
end .a(a), .b(b));
Add_half_bhv AH2(.sum(sum), .c_out(w3),
endmodule .a(c_in), .b(w1));
assign c_out = w2 | w3;
endmodule

October 10, 2024 Introduction to Verilog - Structural Model 91/97

Hierarchy And Scope

• Parent cannot access “internal” signals of child
• If you need a signal, must make a port!

Example: module add8bit(cout, sum, a, b);

Detecting overflow output [7:0] sum;
output cout;
Overflow = input [7:0] a, b;
cout XOR cout6 wire cout0, cout1,… cout6;
FA A0(cout0, sum[0], a[0], b[0], 1’b0);
Must output FA A1(cout1, sum[1], a[1], b[1], cout0);
overflow or cout6! …
FA A7(cout, sum[7], a[7], b[7], cout6);
endmodule

October 10, 2024 Introduction to Verilog - Structural Model 92/97

46
 2024-10-10

Example: Gray code counter

Implement: module gray_counter(out, clk, rst); //3 bit

Use: module dff(clk, d, q, rst);

module comb_gray_code(ns, rst, out);
primitives

clk ns out

Counter Gray
07 code
rst

October 10, 2024 Introduction to Verilog - Structural Model 93/97

Implement the Counter module

• Assume that the schematic of the counter module is
as following

October 10, 2024 Introduction to Verilog - Structural Model 94/97

47
 2024-10-10

Interface: Gray code counter

module gray_counter(out, clk, rst);

output [2:0] out;
input clk, rst;
wire [2:0] ns;

endmodule

October 10, 2024 Introduction to Verilog - Structural Model 95/97

Hierarchy And Source Code

• Can have all modules in a single file
– Module order doesn’t matter!
– Good for small designs
– Not so good for bigger ones
– Not so good for module reuse (cut & paste)
• Can break up modules into multiple files
– Helps with organization
– Lets you find a specific module easily
– Great for module reuse (add file to project)

October 10, 2024 Introduction to Verilog - Structural Model 96/97

48
 2024-10-10

Q&A

October 10,
2024

49