Chapter2_Verilog_HDL
Chapter2_Verilog_HDL
Digital Design
Chapter 2: Introduction to Verilog HDL
Structural Model
Duong Ngoc Phap, Ph.D
Faculty of Computer Engineering and Electronics
Use some slides from ITI-VNU and Dr. Pham Quoc Cuong [email protected])
October 10,
2024
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(*) The terms binary operator and unary operator refer to the number of arguments involved
in the operation: two or one, respectively.
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Switching Algebra
Algebra Implications
• Theorem 1 – idempotence (i) aa a
(Địnhlý hấp thụ)
(ii) aa a
Proof
a 𝑎 a a 1 P-2(ii) aa aa 0 P-2(i)
a P-2(i) a P-2(ii)
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Algebra Implications
• Theorem 2 (i) a0 0a 0
(ii) a 1 1 a 1
Proof
a 0 0 a 0 P-2(i) a 1 P-2(ii)
a a a.0 P-5(ii)
Principle
P-5(i)
of duality
a (a+0) P-4(i) P-4(ii)
Algebra Implications
• Theorem 3
Let a be an element of B. Then a-bar is unique.
Proof
a b
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• AND operation
Symbols
x y z=x·y
x
0 0 0 Theorem 1(ii) z
y
0 1 0 Theorem 2(i)
1 0 0 Postulate 3(ii) x
z
1 1 1 Theorem 1(ii) y
x
x y z=x+y z
Derived from which y
0 0 0
theorem, postulate?
0 1 1
x z
1 0 1 Exercise for Students 1
y
1 1 1
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0 1 1 x
z
y
1 0 1
1 1 0
x
z
y
• NOR operation
Symbols
x y z=x+y x
z
0 0 1 y
0 1 0
x z
1 0 0 y 1
1 1 0
z x y
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z x y x.y x.y
- Construct NXOR gate from NOT, AND, and OR ?
Algebra Implications
• Theorem 4 – Involution
Định lý phủ định của phủ định
x x
Let x be a switching variable. Then
Proof
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Algebra Implications
• Theorem 5
Let x and y be two switching variables.
Then (i) x x y x
Proof
(ii) x x y x
x y x y x + x y
0 0 0 0 + 0 0
0 1 0 0 + 0 0
1 0 0 1 + 0 1
1 1 1 1 + 1 1
Algebra Implications
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– For example,
x y z w x y z w
x y z w
x y z w
x y z w
x y xzw
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Truth tables
• Truth table
– a simple way of representing a switching function is to make a list of the possible variable
assignments and note the value the function takes on for each assignment. This list is
called Truth Table.
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Truth tables
F ( x, y, z) x yz
x y z F (x, y, z)
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
2n assignment 1 0 0 0
possibilities 1 0 1 0
1 1 0 1
1 1 1 0
- Write the Truth Table for the following switching function: F (x, y, z) = x yz x y
Truth tables
• Find a switching function from a truth table
x y F (x, y)
0 0 0 F (x, y) ???
0 1 0
1 0 0
1 1 1
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Canonical representation
x y F (x, y)
– F = 1 whenever x = 1 and y = 1 0 0 0
F ( x, y ) xy 0 1 0
1 0 0
1 1 1
F ( x, y , z ) x y z x yz xy z
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F ( A, B, C ) ( A B C )( A B C )( A B C )( A B C )
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Example
• Construct a XOR gate from NOR and NOT gates ?
z x y xy xy
• Construct a XOR gate from NAND and NOT gates ?
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x y z y (w z) xz ( x xz ) [ y y (w z)] z
Result 1 : xy xy y
xz yw zz
Result 2 : x xy x y
Result 3 : xz xy yz xz xy
None of the listed results can be applied for the above expression.
It’s OK or NOT yet ?
Attention: z z 1
The above expression should equal 1
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A BC ABC BC
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xyz xyz y
xyz
xyz
0 1 1 1
x 1 1 1 1
xyz
xyz z xyz
xyz
y
z
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AB A
CD
1 1
D
z
1 1
C
1 1
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10k
3V
A3
1V
10k
GND
Overview of HDLs
• Hardware description languages (HDLs)
– Are computer-based hardware description languages
– Allow modeling and simulating the functional behavior and timing of digital
hardware
– Synthesis tools take an HDL description and generate a technology-specific
netlist
• Two main HDLs used by industry
– Verilog HDL (C-based, industry-driven)
– VHSIC HDL or VHDL (Ada-based,
defense/industry/university-driven).
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Synthesis of HDLs
• Takes a description of what a circuit DOES
• Creates the hardware to DO it
• HDLs may LOOK like software, but they’re not!
– NOT a program
– Doesn’t “run” on anything
• Though we do simulate them on computers
– Don’t confuse them!
Describing Hardware!
• All hardware created during
synthesis if (a) f = c & d;
else if (b) f = d;
– Even if a is true, still else f = d & e;
computing d&e
b a
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Verilog
• In this class, we will use the Verilog HDL
– Used in academia and industry
• VHDL is another common HDL
– Also used by both academia and industry
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Verilog Module
• In Verilog, a circuit is a module. A[1:0]
2
Verilog Module
A[1:0]
module name ports names of
module 2
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Declaring A Module
• Can’t use keywords as module/port/signal names
– Choose a descriptive module name
Declaring Ports
• A signal is attached to every port
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Module Styles
• Modules can be specified different ways
– Structural – connect primitives and modules (Gate-level model)
– RTL – use continuous assignments (Dataflow model)
– Behavioral – use initial and always blocks (Behavioral model)
• A single module can use more than one method!
Structural
• A schematic in text form
• Build up a circuit from gates/flip-flops
– Gates are primitives (part of the language)
– Flip-flops themselves described behaviorally
• Structural design
– Create module interface
– Instantiate the gates in the circuit
– Declare the internal wires needed to connect gates
– Put the names of the wires in the correct port locations of
the gates
• For primitives, outputs always come first
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Structural Example
output major ;
input V1, V2, V3 ; V1 N1
A0
V2
wire N1, N2, N3;
RTL Example
output major ;
input V1, V2, V3 ;
V1
assign major = V1 & V2
| V2 & V3 V2 Majority major
| V1 & V3;
endmodule V3
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Behavioral Example
endmodule
Adder Example
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input X, Y ; input A, B, CI ;
output S, C ; output S, CO ;
endmodule
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input A, B, CI ;
output S, CO ;
endmodule
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input A, B, CI;
output S, CO;
reg S, CO; // explained in later lecture – “holds” values
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Primitives
• No declarations - can only be instantiated
• Output port appears before input ports
• Optionally specify: instance name and/or delay
(discuss delay later)
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Verilog Primitives
• 26 pre-defined primitives
• Output is the first port
n-output
n-input output ending mark
3-states
and buf nand (y, a, b, c);
nand not input
keyword name
or bufif0
nor bufif1
xor notif0 nand N1(y, a, b, c);
xnor notif1
instance name (optional)
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output major ;
input V1, V2, V3 ; V1 N1
A0
V2
wire N1, N2, N3;
Example
• Using the Verilog structural style, describe the
following circuit
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Datatypes
• Two categories
– Nets
– “Registers”
• Only dealing with nets in structural Verilog
• “Register” datatype doesn’t actually imply an actual
register…
– Will discuss this when we discuss Behavioral Verilog
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Net Types
• wire: most common, establishes connections
– Default value for all signals
• tri: indicates will be output of a tri-state
– Basically same as “wire”
• supply0, supply1: ground & power connections
– Can imply this by saying “0” or “1” instead
– xor xorgate(out, a, 1’b1);
• wand, wor, triand, trior, tri0, tri1, trireg
– Perform some signal resolution or logical operation
– Not used in this course
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Connections Examples
• Variables – defined in upper level module
– wire [3:2] X; wire W_n; wire [3:0] word;
• By position
– module dec_2_4_en (A, E_n, D);
– dec_2_4_en DX (X[3:2], W_n, word);
• By name
– module dec_2_4_en (A, E_n, D);
– dec_2_4_en DX (.E_n(W_n), .A(X[3:2]), .D(word));
• In both cases,
A = X[3:2], E_n = W_n, D = word
• General rules
– Empty input ports => high impedance state (z)
– Empty output ports => output not used
• Specify all input ports anyway!
– Usually don’t want z as input
– Clearer to understand & find problems
• Helps if no connection to name port, but leave empty:
– dec_2_4_en DX(.A(X[3:2]), .E_n(W_n), .D());
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Hierarchy
• Any Verilog design you do will be a module
• This includes testbenches!
Hierarchy
• Build up a module from smaller pieces
– Primitives
– Other modules (which may contain other modules)
• Design: typically top-down
• Verification: typically bottom-up
Full Adder Hierarchy Add_full
Add_half Add_half or
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Add_half Module
Add_half
xor and
Add_full Module
Add_full
Add_half Add_half or
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clk ns out
Counter Gray
07 code
rst
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endmodule
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Q&A
October 10,
2024
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