Semiconductor Memories and

Programmable Logic Devices

• The Basic memory element is binary cell which
can store only one bit of information
• Group of binary cells are called register which can
store n bits of information
• Memories made up of registers. Each register in
the memory is one storage location. Each location
identified by its address
• The total number of bits that a memory can store
is called capacity, the capacity specified in terms
of Bytes( group of eight bits)
• The data stored in a memory by a process
called writing and retrieved from the memory
by the process called reading
Classification of semiconductor memories
 Programmable Logic Devices
• A programmable Logic Devices(PLDs) is general name
for digital integrated circuit capable of being
programmed to provide a variety of different logic
functions.
• Programmable logic devices are broadly classified as
• Read Only Memory or ROM,
• Programmable Logic Array or PLA,
• Programmable Array Logic or PAL
• Complex Programmable Logic Devices or CPLD
• Field Programmable Gate Array or FPGA
 Structure of PLDs

PLD Notation
 Read Only Memory(ROM)
A read only memory is a device that includes
both the Decoder and OR gates within a single
IC package
A ROM consist of an array of semiconductor
devices that are interconnected to store an
array of binary data. Once binary data stored in
ROM, it can be read out whenever desired, but
the data is stored can not be changed normal
operating conditions.
 Types of ROM
(I) Mask programmed ROMs: In the mask programmed ROMs, switch is realized at
the time the ROM is manufactured. Either a connection is made by putting in a wire,
or the connection is left open by not putting in a wire.

(II) Field programmable ROMs (PROMs): In the field programmable ROMs,

switch is realized by a fuse. When the ROM is manufactured all switches are closed
since all the fuses are intact. To open a switch the fuse is blown by sending a larger than
usual current through it. Once a fuse is blown, it cannot be reinstalled.

(III) Erasable ROMs (EPROMs): In the erasable ROMs switch is realized by a

special kind of fuse that can be restored to its usual closed state, usually by the insertion
of extra energy (e.g., shining ultraviolet light on the fuse). All fuses are reset when this
is done.

(IV) Electrically Programmable ROMs (EPROMs): In the electrically

programmable ROMs fuses are reset by the application of larger than usual currents.
Sometimes subsections of the ROM can be reset without resetting all fuses.
Programmable Read Only Memory(PROM)
As shown in the fig, the ROM consists of n input lines and
m output line.
 Each bit combination of the input variables is called an address.
 Each combination that comes out of the output lines is called
word.
The address specified in binary number denotes one of the min
term of n variables
The number of distinct address possible with n input variables is
2n
The input lines serve as an address to select one of the 2n words
when the input combination is applied to the ROM.
The pattern of 0’s and 1’s which stored in the corresponding
word in the memory appears at the output lines.
Consider 64 x 4 ROM. The ROM consists 6 inputs, because 26 =64

With 6 Variables we can specify 64 addresses, for each address

there is unique selected 4 bit word
Combinational logic Implementation Using ROM

• Looking at the logic diagram of the ROM, we can realize that

the output of the decoder is connected to OR gate, hence by
using Rom we can implement any Boolean function which is in
the form Sum of Products(SOP)
Example:
Implement the following Boolean function using ROM
F1(a,b,c) = Σm(0,1,3,5,7 ), F2(a,b,c) = Σm(1,2,5,6).

Sol: The given function have three inputs, they generate 23 = 8

minterms, since there are two functions there are two
outputs
Example 2: Design a combinational circuit using a ROM. The circuit accepts
3 bit binary number and generate its equivalent Excess- 3 code
 Programmable Logic Array(PLA)

 In PROM address will be generated by Decoder, hence it will have 2n

addresses, but in combinational circuit do not use all the minterms
every time, occasionally they have don’t care conditions. Don’t care
conditions when implemented with a PROM becomes an address input
that will never occur. Which may consider waste of available
equipment.

 By using PLA we can avoid this problem. In PLA the decoder circuit is
replaced with group of AND gates, each of which can be programmed
to generate a product term of the input variable

 In PLA both AND gate and OR gate have fuses at inputs, therefore in
PLA both AND gates and OR gates are programmable
 Combinational logic Implementation Using PLA
• We can implement any logic function using PLA which is in the
form of SoP by using PLA program table.
Example: Implement the programming table following
function using PLA
F1 = Σm(3,5,7) F2 = Σm(4,5,7)
The simplified functions in sum of products are obtained from the maps are:
F1= AC + BC
F2=AB’ + AC
Therefore, there are three distinct product terms: AC, BC, and A B’ , and two sum
terms. The PLA program table shown in Table, consists of three columns
specifying product terms, inputs and outputs. The first column gives the lists of
product terms numerically. The second column specifies the required paths
between inputs and AND gates. The third column specifies the required paths
between the AND gates and the OR gates
• Example 2: Implement the following Function using PLA
F1 = Σm(0,1,3,4) F2 = Σm(1,2,3,4,5)
 Programmable Array Logic(PAL)
• We have seen that PLA is a device with programmable AND array
and Programmable OR array. However, PAL is programmable logic
device with a fixed OR array and Programmable AND array. Because
only AND gates are programmable, the PAL is easier to design, but
not as flexible as the PLA
• Implementation of combinational logic circuit is same as PLA
Example: Implement the following Boolean function using PAL
W = Σm(0,2,6,7,8,9,12,13)
X = Σm(0,2,6,7,8,9,12,13,14)
Y = Σm(2,3,8,9,10,12,13)
Z= Σm(1,3,4,6,9,12,14)
K Map Simplification

X = w + BCD’
PAL Programming Table
 Sequential PLDs
• In Combinational PLDs, it will have AND array followed by OR
Array.(Ex: PROM, PLA, PAL)
• In Sequential PLDs it will have logic gates(AND array, OR Array)
followed by Flipflops(D Flipflop)
 Complex Programmable Logic Devices (CPLD)
 The simple programmable logic devices
(SPLDs) has a limitations of number of
inputs, product terms and outputs.
 For applications which requires more number
of inputs or product terms or output we have
to expand the capacity of PLDs by cascading
them.
 The complex programmable logic devices
(CPLDs) are introduced to solve the above
mentioned difficulty of SPLDs.
 A typical CPLD is merely a collection of
multiple PLDs and an interconnection
structure, all on the same chip, as shown in the
Fig.
 In CPLDs, in addition to the individual PLDs
the on-chip interconnection structure is also
programmable.
 Therefore, unlike PLDs, the CPLDs can be
scaled to larger sizes by increasing the number
of individual PLDs.
 General architecture of CPLD

 The Fig. shows the block diagram of a

complex programmable logic device
(CPLD). It consists of collection of PAL like
blocks, I/O blocks and a set of
interconnection wires, called programmable
interconnection structure.
 The PAL like blocks are connected to the
programmable interconnect structure and to
the I/O blocks.
 The chip input-output pins are attached to
the I/O blocks.
 A PAL like block in the CPLD usually
consists of about 16 macrocells.
 The macrocell in CPLD consists of AND-
OR configuration, an EX-OR gate, a flip-
flop, a multiplexer, and a tri-state buffer.
Functional block(FB) is a combination of PLD along with
the Macro cell
Macro Cell
Field Programmable Gate Array
Logical Element

Look Up Table
is a memory
place, where it
will store output
of something is
to implement
Difference Between CPLD and FPGA
 Random Access Memory(RAM)
 Random access memory is a volatile memory i.e the
information stored in a memory is lost when electrical power is
switched off.

 There are two different types of (Random Access Memory)

i. Static RAM
ii. Dynamic RAM
 Static RAM(SRAM)
 Static RAM is able to retain all information into static form until
power supply is turn off, so due to this nature this memory is
known as volatile memory.
 Main objective of using the static RAM is to make Cache
Memory.
 Static Ram is more expensive as well as its power consumption
more to dynamic RAM, but Static Ram has higher speed
compare to dynamic RAM.
 In S RAM, All data has been stored in flip-flop. Flip-flop
contains the every bit of this Ram.
 Flip-flop uses 4-6 transistors for making a memory cell and its
circuit do not need to refreshment continuously.
 6T Static RAM

Write : if i) Q= 0, Q’ =1
Read : if i) Q= 1, Q’ =0
ii) WL= 1
ii) WL = 1
ii) BL, BL’ input lines
iii) BL, BL’ output lines
iii) BL’ should connected to ground
iii) BL’ value decreases
iv) if BL’ Decreases output will be 1
iv) if BL’ Decreases output will be 1
CMOS Inverter
 Advantages and Disadvantages of SRAM

Advantages:
• Not require periodically refreshment circuit.
• Great Performance
• Good reliability
• Less idle time during power consumption

Disadvantages:
• Expensive
• High density
• More power consumption while performing its tasks.
 Dynamic RAM(DRAM)
 DRAM is another type of semiconductor memory, and it is
designed specially to store data or program files which are
needed by computer processors for performing their functions.

 In DRAM, several capacitors are used for storing every bit of

data. This is very simple path to save data in its memory
because it needs small area to store same data to SRAM as
well as it is capable to store massive data than to SRAM but it
requires the frequently refreshing of its circuit for its charging,
so it consumes more power compare to SRAM.
 Advantages and Disadvantages
Advantages
• DRAM is designed with simple technique because in
which use single transistor.
• It allows the great integration density levels.
• It is capable to refresh and delete itself while processing.
• Cost effective
• Less power consumption
• It needs small area

Disadvantages
• Its accessing speed is very slow compare to SRAM.
• It consumes more power to SRAM.
• Data needs to refreshment continuously.
Memory Organization and Operation
Write Operation
Timing Diagram
Read Operation
Timing Diagram
 Expanding Memory
Procedure to expand Word Size:

Procedure to expand Capacity

Example to Expand word size
Example to Expand Capacity
 Finite State Machine
A Finite State Machine (FSM) is a mathematical model that is used to explain and
understand the behavior of a digital system. More specifically, it is a structured and
systematic model that helps to understand the behavior of a sequential circuit that
exists in a finite number of states at a given point of time.
Capabilities and Limitations of Finite-State Machine.
1. Periodic sequence of finite states: With n-state machine we can generate
periodic sequence of n states or smaller than n states. For example in 5 state
machine we can have maximum periodic sequence as 0, 1, 2, 3, 4, 0, 1, 2.
2. No infinite sequence: Consider an infinite sequence such that an output is 1
when and only when the number of inputs received so far is equal to K(k + 1) / 2
for K = 1, 2, 3 i.e., the desired input output sequence has the form.
Input: XX X X X X X X X X X X X X X X X X X X X
Output: 10 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1
Such infinite sequence can not be produced by finite state machine.
3. Limited memory: The finite-state machine has a limited memory and due to
limited memory it can not produce certain outputs.
 Successor: Looking at state diagram, we
can say that, when present state is A and
input is 1, the next state is B. In order
words, this condition is specified as B is
the 1-successor of A. Similarly, we can
say that A is the 0-successor of C, C is a
11-successor of A, D is a 111-successor
of A and so on. In general we can say
that, if an input sequence X takes a
machine from state s_{i} to state then is
said to be the s_{j} X-successor of s_{i}
s_{i}

Terminal state: Looking at state diagram, we can realise that, there is no such input
sequence exists which can take sequential machine out of state D and thus D is said to be a
terminal state. In general, we say a state is a terminal state when there are no outgoing arcs
which starts from it and terminate in other states.
 Simplification of Incompletely Specified Machines
 We often encountered conditions in designing combinational logic circuits where
the truth table was incompletely specified, which resulted in don't-care terms.
The same thing is happen in sequential circuits if either state transitions or output
variables are not completely specified. Such machines are said to be incompletely
specified.
 When the state transitions are not specified, the sequential machine is not
predictable. It is desirable to avoid such situations either by specifying inputs
sequences so that no next state is unspecified or by assigning next states that are
not contrary to the desired result.
 When reducing incompletely specified state table we use term state compatibility
instead of state equivalence.
 The state compatibility is defined as:
States si and sj said to be compatible states, if and only if for every input
sequence that affects the two states, the same output sequence occurs whenever both
outputs are specified and regardless of whether si and sj is the initial state.
 Merger Graph
Merger graphs is state reducing tool used to reduce states in the
incompletely specified machine. The merger graph is defined as
follows:
 It contains the same number of vertices as the state table
contains states
 Each compatible state pair is indicated by a line drawn
between the two state vertices.
 Every potentially compatible state pair, with outputs not in
conflict but whose next states are different, is connected by a
broken line. The implied states are drawn in the line break
between the two potentially compatible states.
 If two states are incompatible no connecting line is drawn. .
• States A and B are compatible because the next states and output entries of states A and
B are not conflicting. Therefore, line is drawn between vertices A and B.
• States A and C, on the other hand, have non conflicting outputs, but the successors
under input I2 are C and F. Therefore, states A and C are compatible only if implied
states C and F are compatible. This is indicated by drawing a broken line with CF
written in between.
• Similarly, states A and D are compatible if and only if implied states B and E are
compatible and hence BE is entered in the broken line from A to D.
• No line is drawn between states A and E because outputs under I2 and I3 are conflicting,
i.e., states A and E are incompatible.
• In similar way, the merger graph is drawn for all possible pair of states. We have seen
that, the merger graph displays all possible pairs of states and their implied pairs, and
we know that a pair of states is compatible only if its implied pair is compatible.
Therefore, it is necessary to check whether the implied pairs are indeed compatibles.
• The states are said to be incompatible if no line is drawn in between them.
If implied states are incompatible, they are crossed and the corresponding
line is ignored.
• For examples, implied states C and E are incompatible so states B and F are
also incompatible. Next, it is necessary to check whether the
incompatibility of B and F does not invalidate any other implied pair.
• The broken lines which remain in the graph, after all the implied pair have
been verified to be compatible, are regarded as complete lines.
• After checking all possibilities of incompatibility the merger graph gives
the following nine compatible pairs.
• (A, B) (A,C) (A, D) (B, C) (B, D) (B, E) (C, D) (C, F) (E, F)
• These compatible pair are further checked for further compatibility. For
example, pairs
• (A, B), (A, C) and (B, C) are compatible, so (A, B, C) is also compatible.
In this way entire set of compatibles of sequential machine can be
generated from its compatible pairs.
• To find the minimal set of compatibles for state reduction it is useful
to find what are called the maximal compatibles.
• A set of compatible-state pairs is said to maximal if it is not
completely covered by any other set of compatible state pairs.
• The maximum compatibles can be found by looking at merger graph
for complete polygons which are not contained within any higher-
order complete polygons.
• For examples in merger graph shown in Fig the polygon A B C D is
a higher-order complete polygon. It covers (A, B), (A, C), (A, D),
(B, D), (B, C) and (C, D) compatible pairs and these compatible
pairs are ignored from set of maximal compatibles for sequential
machine.
•
• The set of maximal compatibles for this sequential machine is then
given as
(A, B, C, D); (B, E); (C, F); (E, F)
 Merger Table
The merger table method is also called as Paull-Unger method or implication
chart method.
• Each cell of the merger table corresponds to the compatible pair represented by the
intersection of the row and column headings.
• The incompatibility of two states is indicated by placing cross mark ‘X’ in the
corresponding cell,
• compatibility is indicated by placing check mark ‘√’ in the cell. For example, states
A and D are incompatible because their outputs are conflicting and hence the cell
corresponding them contain cross mark X.
• The states C and E are compatible and hence the cell corresponding them contain
check mark.
• The implied pair or pairs corresponding to state-pair are written with the cell as
shown in the table. For example, states A and C are compatible only when implied
states B and C are compatible, therefore implied pair B C is written in the cell
corresponding to states A and C.
• In the similar way the entire merger table is written.
• Now it is necessary check whether implied pairs are compatible or not. This can be
checked by observing the merger table.
• The implied states are incompatible if corresponding cell contain X. For example,
implied pair BD is incompatible because cell BD contain X. Since BD is incompatible,
states D and F are also incompatible. As DF is in compatible, states B and F are also
incompatible. It is indicated by cross mark in table
Once the merger table is completed, the set of all maximal compatibles can be found by
procedure which is counter part to that of finding complete polygon in the merger
graph. The procedure is as follows:
1. Begin with right most column in the merger table and proceed left unit a column
containing a compatible pair is encountered. For example, the pair EF in the
merger table.
2. Proceed left to the next column containing at least one compatible pair. If the
state to which this column corresponds is compatible with all the states in the set
of previously determined compatible states then add this state to that set of
compatible states to form a larger compatible.
3. If the state is not compatible with all the states of previously determined set, but
is compatible with some other state, form a new set of compatible states. For
example, state D is not compatible with both E and F which are previously
determined set of states. However, it is compatible with state E. Therefore, it is not
added in the previous set, but the new set is formed, DE. On the other hand, state
C is compatible with both E and F which are previously determined set of states
and hence it is included in that set to form a new set CEF. Similarly, C is also
included in set DE to get a new set CDE.
3. Repeat step 2 until the left most column is reached. After application of above
mentioned procedure the merger table, gives following set of maximal compatibles
Column E: (E,F)
Column D: (E, F); (D, E)
Column C: (C, E, F); (C, D, E)
Column B: (C, E, F); (C, D, E); (B, C)
Column A: (C, E, F); (C, D, E); (A, B, C); (A, C, F)

 The right most column is E. It indicates that the state E is compatible with state F,
resulting a compatible pair (EF).
 The column D indicates that the state D is compatible with state E, thus compatible
pair (DE) is included in the compatible list.
 The column C shows that the state C is compatible with states D, E and F and
consequently the compatibles generated previously are enlarged to include state C.
 The column B consists of a single compatible pair (BC), which is added to the
previously generated compatible list.
 The column A indicates that the state A is compatible with states B, C and F. Thus,
the previously generated compatible pair (BC) is enlarged to give the compatible
(ABC), while rows C and F, together with preciously available compatibility
relations, give the compatible (ACF). Therefore, the set of maximal compatibles is

(C, E, F); (C, D, E); (A, B, C); (A, C, F)

 Race-Free state Assignment Hazards
 The unwanted switching transients that may appear at
the output of called Hazards
 The main cause of hazards is the different propagation
delays at different paths.
 Hazards occur in the combination circuits, where they
may cause a temporary false output value
 When such circuits are used in the asynchronous
sequential circuits, they may result a wrong stable state
 A hazard is a condition where a single variable change
produces a momentary output change when no output
change should occur.
 Hazards in combinational ciruits
Types of Hazards:
• Static-0 hazard – The output may go to 1 when it should remains at 0
• Static-1 hazard – The output may go to 0 when it should remains at 1
• Dynamic hazard – It causes the output to change three or more times
when it should change from 1 to 0 or 0 to 1.
 Fig -1 Fig -2
Combinational Circuit with Hazards

 Assume that, initially, inputs X1, X2 and X3= 1. This causes the output of gate
1 to be 1, that of gate 2 to be 0. and the output of the circuit to be equal to 1.
 Now consider change in X2 from 1 to 0. The output of gate 1 changes to 0 and
that of gate 2 changes to 1, leaving the output at 1.
 However, the output momentarily goes to 0 if the propagation delay through
the inverter is taken into consideration. The delay in the inverter causes the
output of gate 1 to change to 0 before the output of gate 2 changes to 1.
 In this situation, both inputs of gate-3 momentarily equal to 0, causing the
output to go to 0 for the short time equal to propagation delay of the inverter
called Static-1 Hazard
 Same explanation holds true for NAND Gates.
Hazards can be eliminated by enclosing two minterms or
maxterms in question. For example, if the circuit has minterms
X1X2 + X’2 X3, then these two minterms must be enclosed by
introducing another minterm X1X3 is illustrated in Fig.
Sol: Convert to Standard SoP
X1X2 (X3 + X’3)+ X’2 X3(X1 + X’1)
X1X2 X3 + X1X2 X’3+ X1X’2 X3 + X’1X’2 X3

Hazard Free Circuit

For a given Boolean function obtain the hazard-free circuit. F(A,
B, C, D) = ∑m(1, 3, 6, 7, 13, 15)
 Essential Hazards
• There is another type of hazard that may occur in asynchronous sequential
circuits, called essential hazards. An essential hazard is caused by unequal
delays along two or more paths that originate from the same input. Such
hazards can be eliminated by adjusting the amount of delays in the affected
path.
Example:
F(A, B, C, D) = ∑ m (0, 2, 6, 7, 8, 10, 12)
Solution:
The given function can be implemented using K-map as shown in the Fig a
and fig b. The figure b shows the additional product term, ACD overlapping
two groups (group 1 and group 2) for hazard free realization. Group 1 and
group 3 are already overlapped hence they do not require additional minterm
for grouping