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Team Project 01

IC project

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4 views

Team Project 01

IC project

Uploaded by

j0978387873
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Dept. EE, NSYSU Lecturer: Prof.

Tzung-Je Lee

Final Team Project


Introduction to VLSI Design

Please organize a team to complete the educational IC tapeout at the end of this semester. Each team
is composed of no more than 3 persons. For the first week, each team must decide what circuit your team
would like to design. Notably, at least one member of the team must still stay at NSYSU in the next
semester for preparing the testing report, so that you could submit the tapeout. Besides, your rport
need to meet the requirement of the TSRI’s rules for EDU chip. Otherwise, you could not submit the
final tapeout, however, you still could hand in the files for the final project.
Please submit the report for final team project of the week 1, addressing the team member’s name
and their student ID. Please also include the block diagram and the detailed circuit (must prepared by using
the office tool: visio) and addresses their functions in the report.

The recommended schedule is as follows.


Week 1 May 04 – May 10 Organize the team, and decide the topic of the final project.
Week 2 May 11 – May 17 Pre-layout simulation with at least 9 corners*
Week 3 May 18 – May 24 Layout including the power ring, guard ring, and PAD. DRC and LVS check
Week 4 May 25 – May 31 Post-layout simulation with at least 9 corners
Week 5 Jun. 01 – Jun. 07 Final tapeout report
Week 6 Jun. 08 – Jun. 14 Buffer week
Notably, the deadline of the final project is 23:00 Jun. 14, 2023.
The target shuttle is U18-112C, whose submission deadline is Oct. 02, 2023.
Note: * the 9 corners are shown as follows.
Corner1 Corner2 Corner3 Corner4 Corner5 Corner6 Corner7 Corner8 Corner9

TT, FF, SS, FF, SS, FS, FS, SF, SF,


o o o o o o o o o
25 C, 100 C, 0 C, 0 C, 100 C, 100 C, 0 C, 0 C, 100 C,
1.8 V 1.98 V 1.62 V 1.62 V 1.98 V 1.98 V 1.62 V 1.62 V 1.98 V

The possible circuits for your final project, but not limit to these circuits.
Basic digital circuits: 8-bit Baugh-Wooley multiplier
8-bit signed/unsigned CLA 8-bit universal shifter
8-bit Manchester adder 8bit/4bit signed/unsigned integer divider
8-bit array multiplier 8-bit signed/unsigned accumulator
8-bit Booth multiplier 8-bit up/down module-N loadable counter
8-bit up/down loadable counter 1-Kb SRAM

The grade of the final project, which is worth 20% of the final scores, is calculated as follows.
 Presim: 5 points  Posim: 5 points
 Layout, DRC&LVS: 5 points  Report: 5 points
Dept. EE, NSYSU Lecturer: Prof. Tzung-Je Lee
Appendix
Simplified Annotation of EDU IC tapeout from TSRI

Submission deadline: 14:00


Prepared documents:
1. Register your ID
2. On-line submission application.
3. The files you have to prepare for EDU IC tapeout.
[1] Edu_Report.doc
[2] Layout file (TopCellName.gds)
[3] DRC results (TopCellName.drc.summary)
[4] LVS results (TopCellName.lvs.report)
[5] Tapeout review form (TopCellName_TRF.doc)
4. The additional files you have to hand in for final project.
[1] Prelayout simulation file (TopCellName_presim.sp)
[2] Postlayout simulation file (TopCellName_posim.sp) and the corresponding extracted files.
[3] Compressed file of your design library (LibraryName.tar.gz)

For further detailed information, please refer to the annotation of TSRI Edu IC tapeout.

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