Fundamentals of Electronic

Packaging
Lecture 2
08/26/24

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 Alternative definition: Electronic Packaging
Physical realization of an electronic system based on:
• Design
• Materials
• Choice of technology to implement design
• Electrical and thermal analysis
• Reliability analysis
• Much more

Packaging is the first step after semiconductor design and fabrication

Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing

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 Why packaging important?
Processor capability Challenges:
• 64 bits processor • Connections of a small chip with
• Billions of transistors so many I/Os over a tiny area
• Ensure that the transistors do-not
overheat

The processor or central processing unit (CPU) of a device acts like its brain, telling other components what
to do.
Source: Prof. Anandaroop Bhattacharya, NOC Jan 2019: Electronic Packaging and Manufacturing 3
 Transistors
• A transistor is a miniature semiconductor that regulates or controls current or voltage flow in
addition amplifying and generating these electrical signals and acting as a switch/gate for them

➢ Heterojunction bipolar transistor (HBT)

➢ Field effect transistor (FET)
• Junction FET
• Metal-Oxide-Semiconductor FET(MOSFET)
➢ Bipolar junction transistor (BJT)
➢ Avalanche transistor
➢ Insulated gate bipolar transistor (IGBT)

➢ What do transistors do in a CPU?

• Transistors are the main component of the microchips used in computers. Computers operate on a
binary system, which uses only two digits: 0 and 1. In a computer microchip, transistors act as
switches, letting current through to represent the binary digit 1, or cutting it off to represent 0.
• More transistors can increase parallelism which increases speed, more things done at the same
time rather than serially
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 Transistors
• Bipolar Junction Transistors are transistors that are
built up of 3 regions, the base, the collector, and the
emitter.
• Bipolar junction transistors come in two major types,
NPN and PNP.
• An NPN transistor is one in which the majority of the
current carriers are electrons.

• Field Effect Transistors are made up of 3 regions, a gate,

a source, and a drain.
• A voltage placed at the gate controls current flow from
the source to the drain of the transistor.
• MOSFET is most frequently used among all kinds of
transistors (Suitable for modern electronic applications)

Source: https://www.elprocus.com/different-types-of-transistors-and-their-functions/ 5
 N-type MOSFET
➢ A block, also known as a substrate of p-type
semiconductor acts as the base for MOSFET
➢ Two sides on this p-type substrate are made highly
doped with an n-type impurity (marked as n+)
• The drain terminals (Source and Drain) are then
brought out from these two end regions
➢ The entire surface of the substrate is coated with a layer
of silicon dioxide
• Silicon dioxide acts as insulation
➢ A thin insulated metallic plate is then placed on top of
the silicon dioxide, acting as a capacitor plate
• The gate terminal is then brought out from the thin
metallic plate
Source: Hiroshi Iwai. Downsizing of transistors towards its Limits. Tokyo Institute of
Technology.
➢ A DC circuit is then formed by connecting a voltage
source between these two n-type regions (marked in red)
Watch Video:
https://www.youtube.com/watch?v=Bine_PbyFSQ&t=69s

➢ When voltage is applied at the gate, it generates an electrical field that changes the width of the channel region,
where the electrons flow. The wider the channel region, the better conductivity of a device will be.
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 Miniaturization and Transistor Scaling
• Digital integrated circuits generally contain transistors and interconnections. Depending on the
complexity and sophistication of the device design, the structure may contain several overlapping
layers.
• Many millions of gates are accommodated on a single chip with a multiplicity of layers and associated
interconnects. A transistor is formed whenever a gate layer crosses a diffusion layer.
• A variety of materials is used for interconnection, including tungsten, copper, aluminum.
• Fabrication of transistors include photolithography, etching, ion implantation, doping, and
metallization to create the intricate circuitry on a wafer.
• A silicon nitride layer is applied as the last layer to protect the circuits as a passivation layer. Sometimes
silicon dioxide or polyimides are also used as passivation films

➢ Intel Core i7-12700K (12th Generation):

• Transistor Count: Approximately 7 billion transistors
• Transistor size: 10nm

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 Evolution of Transistor Sizes

Source: Hiroshi Iwai. Downsizing of transistors towards its Limits. Tokyo

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Institute of Technology.
 Moors’s Law
• Moore’s Law: States that the number of transistors on a microchip
doubles approximately every 2 years, leading to smaller, faster, and
more powerful chips over time.

Intel co-founder Gordon Moore predicted a doubling of transistors every

year for the next 10 years in his original paper published in 1965.

Ten years later, in 1975, Moore revised this to doubling every two years -
Predicted that one can integrate 6.5 x 104 components by 1975

This extrapolation based on an emerging trend has been a guiding

principle for the semiconductor industry for close to 60 years.

In 1965, number of transistors in a single chip was roughly 50 transistors

per square inch.

Gordon Moore (1929 – 2023)

Source: Viswanadham, Puligandla. Essentials of Electronic Packaging: A Multidisciplinary Approach. ASME. 2011.
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 Moore's Law (Cont.)

• At different times, interpretation of

“Moore’s law” revised

• Generally accepted definition:

• Number of components per chip
double every 18 months

Source: Adamu-Lema, Fikru (2005) Scaling and intrinsic parameter fluctuations in nanoCMOS devices.
PhD thesis. Chapter 2. The scaling of MOSFETs, Moore’s law, and ITRS.
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 Moore's Law Implications
• Some of the implications include:
• Increase functionality
• Cost per function reduction
• Better Performance

• According to International Technology Roadmap for Semiconductors

(ITRS), functionality is defined as the number of bits in a DRAM chip
or the number of logic transistors in a microprocessor unit

• Reduction on the manufacturing cost per function is one of the

primary implications
Source: Adamu-Lema, Fikru (2005) Scaling and intrinsic parameter fluctuations in nanoCMOS devices.
PhD thesis. Chapter 2. The scaling of MOSFETs, Moore’s law, and ITRS. 11
 Challenges
• Compliance to “Moore’s law” requires geometrical shrinkage of transistor feature
sizes
• Delays due to metal interconnects and formation of hot spots limit performance due
to density improvements
• Circuit density increasing
• Operation frequency saturated

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Source: Dr. Burhan Bayraktaroglu. Heterogeneous Integration Technology. AFRL/RYDD.
 Dennard’s Scaling
• In 1974, Dennard outlines:
• Rules for scaling of transistors
• Rules for scaling of interconnection lines
• Scaling of Transistors: Dennard's Scaling states that as
transistors are miniaturized, their power density
remains constant, meaning that power consumption
per transistor remains the same while transistor density
increases.
• Predicted that the fact the “line response time” for the
interconnects did not scale would create an issue
Source: Dennard, Robert H., et al. "Design of ion-implanted MOSFET's with
very small physical dimensions." IEEE Journal of Solid-State Circuits 9.5 (1974):
256-268.

Watch Video:
https://www.youtube.com/watch?v=dK66m
V6RU5Q

Source: Adamu-Lema, Fikru (2005) Scaling and intrinsic parameter fluctuations in nanoCMOS devices. PhD 13
thesis. Chapter 2. The scaling of MOSFETs, Moore’s law, and ITRS.
 ITRS
• International Technology Roadmap for Semiconductors (ITRS)
• Comprehensive guide that enables the semiconductor industry to transform
“Moore’s law” observations into reality

• Outlines requirements and identifies challenges that allow “Moore’s

law” to be maintained in the coming years
• Needs and requirements of solutions under development
• Outline limitations of interim solutions
• Identify areas where there are “no known manufacturing solutions”

• Help in synchronize technology development efforts by providing

guidance to research communities and funding agencies
Source: Dr. Burhan Bayraktaroglu. Heterogeneous Integration Technology. AFRL/RYDD.
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 2015 ITRS Roadmap
• Expectation on device feature size
reduction revised on 2015

• Other approaches without reducing

transistor size

• Any further increase in circuit density

to come from 3D architectures
• Homogenous integration

Source: Dr. Burhan Bayraktaroglu. Heterogeneous Integration Technology. AFRL/RYDD.

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 Looking Forward
• Integration density improvements
are saturating

• Two paths for increasing integration

and functional density:
• More Moore (MM) roadmap
• New path to increase integration density

• More than Moore (MtM) roadmap

• Increase in functionality density

Source: Dr. Burhan Bayraktaroglu. Heterogeneous Integration Technology. AFRL/RYDD. 16

 More than Moore (MtM)
• More functions are offered per given chip area through heterogeneous
integration

• Heterogenous integration
• IEEE definition “Integration of separately manufactured components into a
higher-level assembly that, in the aggregate, provides enhanced functionality
and improved operating characteristics.”

• Allows the best available technology node to be used for each application to
maintain maximum performance

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Source: Dr. Burhan Bayraktaroglu. Heterogeneous Integration Technology. AFRL/RYDD.
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Source: Will Chen. HIR Roadmap Workshop Presentation. 2017.
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Source: Will Chen. HIR Roadmap Workshop Presentation. 2017.
END

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