Computer Organization

MODULE –I

Functional units of a Computer System

A computer consists of the following functionally independent main parts:

a. Input unit
b. Memory
c. Central Processing Unit (CPU) that contains Arithmetic and Logic Unit, Control Unit and Registers
d. Output unit
Input unit -The input unit accepts coded information from human operators using devices such as
keyboards, or from other computers over digital communication lines.
Memory unit - Memory stores programs and data. There are two classes of storage, called primary and
secondary. Primary Memory : Primary memory, or main memory, is a fast memory that operates at
electronic speeds. Programs must be stored in this memory while they are being executed. Instructions
and data can be written into or read from the memory under the control of the processor Cache
Memory: Cache is a smaller, faster memory unit that holds sections of a program that is currently being
executed, along with any associated data. Secondary Storage: This is less expensive, permanent
secondary storage that is used when large amounts of data and many programs have to be stored,
particularly for information that is accessed infrequently.
Arithmetic and Logic Unit (ALU) – It carries out arithmetic and logical operations Output Unit- Its
function is to send processed results to the outside world. Eg: Printer
Control Unit- It controls and coordinates the activities of all the other units with the help of control
signals.
BUS INTERCONNECTION
▪ A bus is a communication pathway connecting two or more devices.
▪ A bus is a shared transmission medium. Typically, a bus consists of multiple communication pathways,
or lines.
▪ Each line is capable of transmitting signals representing binary 1 and binary 0.
▪ A bus that connects major computer components (processor, memory, I/O) is called a System bus.
Bus Structure
 Bus designs can be classified into three functional groups Data, address, and control lines.
 Data Bus
 The data lines provide a path for moving data (data & instructions) among system modules.
 The data bus may consist of 32, 64, 128, or even more separate lines .
The number of lines determines how many bits can be transferred at a time.
The width of the data bus is a key factor in determining overall system performance
 Address bus -The address lines are used to identify the source or destination of the data on the
data bus.
 The width of the address bus determines the maximum possible memory capacity of the
system.
 Control Bus – The control lines are used to control the access to and the use of the data and
address lines.
 Control signals transmit both command and timing information among system modules. –
Timing signals indicate the validity of data and address information. – Command signals specify
operations to be performed.
 The simplest way to interconnect functional units is to use a single bus. All units are connected
to this bus. Because the bus can be used for only one transfer at a time, only two units can
actively use the bus at any given time.

Compare SRAM & DRAM

Memory hierarchy with respect to speed, size and cost

CACHE MEMORY
 Cache memory is a chip-based computer component that makes retrieving data from the
computer's memory more efficient.
 Cache memory is fast and expensive
 It acts as a temporary storage area that the computer's processor can retrieve data from easily.
 Cache memory is sometimes called CPU (central processing unit) memory because it is typically
integrated directly into the CPU chip or placed on a separate chip that has a separate bus
interconnect with the CPU. Therefore, it is more accessible to the processor, and able to
increase efficiency, because it's physically close to the processor.
  Cache memory operates between 10 to 100 times faster than RAM, requiring only a few
nanoseconds to respond to a CPU request.
 Types of cache memory :-
 L1 cache, or primary cache, is extremely fast but relatively small
  L2 cache, or secondary cache, is often more capacious than L1. L2 cache may be embedded on
the CPU
 Locality of Reference – it also known as the principle of locality, is the tendency of a processor to
access the same set of memory locations repetitively over a short period of time.
 Locality of reference are of 2 types:-
 1. Temporal Locality - Temporal locality refers to the tendency of a program to access the same
memory locations repeatedly within a short period of time
 2. Spatial Locality- Spatial locality refers to the tendency of a program to access memory
locations that are physically close to each other. This means that if a particular data item is
accessed, nearby data items are likely to be accessed soon.
Virtual Memory
● Virtual memory is a memory management technique where secondary memory can be used as if it
were a part of the main memory.
● Virtual memory is a technique computers use to give the illusion of having more memory (RAM) than
they physically do.
● It does this by using a combination of RAM and disk space. When your computer runs out of physical
memory, it moves less frequently used data from RAM to a special file on the disk called a swap file or
page file. This frees up space in RAM for other tasks. When that data is needed again, it's moved back
into RAM
Module 2

Explain I/O interfacing with memory mapped i/o and program controlled I/O
I/O Interfacing
In computing, input/output, or I/O, refers to the communication between computers and the outside
world. There is a huge difference in speed of a processor and other peripheral components (I/O
devices). Therefore an I/O interface is needed to connect any external peripheral with computer. A
simple arrangement to connect I/O devices to a computer is to use a single bus structure. It consists of
three sets of lines to carry. They are address bus, control bus and data bus.

This figure illustrates the hardware required to connect an I/O device to the bus.
● the address decoder enables the device to recognize its address when this address appears on the
address lines.
●The data register holds the data being transferred to or from the processor.
● the status register contains information relevant to the operation of the I/O device.
● Both the data and status registers are connected to the data bus and assigned unique addresses.

MEMORY-MAPPEDI/O
 ThearrangementofI/Odevicesandthememorysharethesameaddressspaceiscalled memory-
mapped I/O. With memory-mapped I/O, any machine instruction that can access memory can
be used to transfer data to or from an I/O device.
PROGRAMMEDI/O
 They are the result of i/o instructions written in the computer program
 Transferring data under program control requires constant monitoring of the peripheral by the
CPU
 The processor executes a program that gives it direct control of the I/O operation, including
sensing device status, sending a read or write command, and transferring the data.
 When the processor issues a command to the I/O module, it must wait until the I/O operation is
complete.
 Disadvantage: CPU is waiting time by checking flag .
 The working of programmed i/o is shown below.


HANDLING MULTIPLE INTERRUPTS

INTERRUPTS
The interrupt is a signal emitted by hardware (may be i/o device) or software when a process or
an event needs immediate attention.
  When more than one device raises an interrupt request signal, then additional information is
needed to decide which device to be considered first. The following methods are used to decide
which device to select
 Polling, Vectored Interrupts, and Interrupt Nesting.
 Polling: In polling, the first device encountered with IRQ bit set is the device that is to be
serviced first. Appropriate ISR is called to service the same. It is easy to implement but a lot of
time is wasted by interrogating the IRQ bit of all devices
 Vectored Interrupts: In vectored interrupts, a device requesting an interrupt identifies itself
directly by sending a special code to the processor over the bus. This enables the processor to
identify the device that generated the interrupt. The special code can be the starting address of
the ISR or where the ISR is located in memory, and is called the interrupt vector.
 Interrupt Nesting: In this method, I/O device is organized in a priority structure. Therefore,
interrupt request from a higher priority device is recognized whereas request from a lower
priority device is not. Processor accepts interrupts only from devices/processes having priority
more than it
DIRECT MEMORY ACCESS (DMA)
● It is a technique used for high speed I/O device.
●Here, the device interface transfer data directly to or from the memory without continuous
involvement by the processor
● A special control unit may be provided to allow the transfer of large block of data at high speed
directly between the external device and main memory, without continuous intervention by the
processor. This approach is called DMA.
● DMA transfers are performed by a control circuit called the DMA Controller.

Steps of data transfer through DMA controller

 Whenever an I/O device wants to transfer the data to or from memory, it sends the DMA request
(DRQ) to the DMA controller.
 DMA controller sending this request to CPU to get the control of system bus by using hold request
HLD
 CPU responds with an acknowledgment HLDA
 When DMA controller receives this acknowledgment it send a DACK to I/O device for data transfer
to inform that DMA controller is ready to take the charge of system bus
 When the data transfer is accomplished, the DMA raise an interrupt to inform the processor that the
task of data transfer is finished and the processor can take control over the bus again
 The figure is given below


DMA controller Transfers the block of data to and from memory in three modes burst mode, cycle
steal mode and transparent mode.
1. Burst Mode: Here, once the DMA controller gains the charge of the system bus, then it releases the
system bus only after completion of data transfer. Till then the CPU has to wait for the system buses.
2. Cycle Stealing Mode: In this mode, the DMA controller forces the CPU to stop its operation and
relinquish the control over the bus for a short term to DMA controller. After the transfer of every byte,
the DMA controller releases the bus and then again requests for the system bus. In this way, the DMA
controller steals the clock cycle for transferring every byte.
3. Transparent Mode: Here, the DMA controller takes the charge of system bus only if the processor
does not require the system bus.

Standard I/O Interfaces

The three major standard I/O interfaces are:-

 PCI (Peripheral Component Interconnect)

 SCSI (Small Computer System Interface)
 USB (Universal Serial Bus)
 PCI is a plug-and-play capability for connecting I/O devices. To connect a new device,
the user simply connects the device interface board to the bus. The software takes care
of the rest. The PCI bus is a good example of a system bus.
 SCSI- It's a fast bus that can connect lots of devices to a computer at the same time, including
hard drives, scanners, CD-ROM, printers and tape drives.
 The SCSI bus is connected to the processor bus through a SCSI controller. This controller uses
DMA to transfer data packets from the main memory to the device ,or vice versa
 USB - Provide a simple, low-cost and easy to use inter connection system that over comes the
difficulties due to the limited number of I/O ports available on a computer •Accommodate a
 wide range of data transfer characteristics for I/O devices, including telephone and Internet
connections
 plug-and-play mode of operation

Flat-Panel Display Monitor

The flat-panel display refers to a class of video devices that have reduced volume, weight and power
requirement in comparison to the CRT. You can hang them on walls or wear them on your wrists.
Current uses of flat-panel displays include calculators, video games, monitors, laptop computer ,and
graphics display.
The flat-panel display is divided in to two categories−
•Emissive Displays−Emissive displays are devices that convert electrical energy in to light.
Example: plasma panel and LED
•Non-Emissive Displays− Non-emissive displays use optical effects to convert sunlight or light from
some other source into graphics patterns.
Example: LCD (Liquid-Crystal Device).
Printer

Module 3

EXECUTING AN INSTRUCTION
A program is a set of instructions performing a meaningful task. An instruction is command to the
processor & is executed by carrying out a sequence of sub-operations called as micro-operations.
Processor fetches one instruction at a time and performs the operation specified.
Instructions are fetched from successive memory locations until a branch or a jump instruction is
encountered.
Processor keeps track of the address of the memory location containing the next instruction to be
fetched using Program Counter (PC).
Instruction Register (IR) stores currently executing instruction
Two phases of executing an instruction:-
1. Fetch phase
2. Execution phase
 Fetch the contents of the memory location pointed to by the PC.
 The contents of this location are loaded into the IR (fetch phase).
IR ← [[PC]]
 Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch
phase). PC ← [PC] + 4
 Carry out the actions specified by the instruction in the IR (execution phase).
Explain about Internal Structure of a CPU
Internal organization (Functional units) of a processor contains:
● Registers for temporary storage
● Various digital circuits for executing different micro operations.(gates, MUX, decoders,
counters).
●internal path for movement of data between ALU and registers.
● Driver circuits for transmitting signals to external units. Receiver circuits for incoming signals
from external units.
PC:
❖ Keep track of execution of a program
❖ Contains the memory address of the next instruction to be fetched and executed.
MAR:
❖ Holds the address of the location to be accessed
. ❖ I/P of MAR is connected to Internal bus and an O/p to external bus.
MDR:
❖ Contains data to be written into or read out of the addressed location.
❖ Data can be loaded into MDR either from memory bus or from internal processor bus. ● The
data and address lines are connected to the internal bus via MDR and MAR
Registers:
❖ The processor registers R0 to Rn-1 vary considerably from one processor to another.
❖ Registers are provided for general purpose used by programmer.
❖ Special purpose registers-index & stack registers
❖ Registers Y,Z &TEMP are temporary registers used by processor during the execution of
some instruction.
Multiplexer:
❖ Select either the output of the register Y or a constant value 4 to be provided as input A of
the ALU
❖ Constant 4 is used by the processor to increment the contents of PC.
ALU:
Used to perform arithmetic and logical operation.
Data Path:
❖ The registers, ALU and interconnecting bus are collectively referred to as the data path.

BASIC REGISTER TRANSFER

● The input and output gates for register Ri are controlled by signals isRin and Riout .
● Riin Is set to1 – data available on common bus are loaded into Ri.
● Riout Is set to1 – the contents of register are placed on the bus.
● Riout Is set to 0 – the bus can be used for transferring data from other registers EX: Transfer
the contents of R1 to R4.
● Enable output of register R1 by setting R1out=1. This places the contents of R1 on the
processor bus.
Enable input of register R4 by setting R4in=1. This loads the data from the processor bus into
register R4.
PIPELINING
 Pipelining is a process of arrangement of hardware elements of the CPU such that its
overall performance is increased
 Execution of a program consists of a sequence of fetch and execute steps shown in
figure below
 Let F1 and E1 refer to the fetch and execute steps for instruction I1.
 The figure below contains sequential execution and pipeline execution.
 In sequential the processor executes a program by fetching and executing instructions,
one after the other.
 But Pipelined execution is a technique used in CPUs to improve performance by
processing multiple instructions simultaneously, like an assembly line.
 Instead of waiting for one instruction to fully complete before starting the next, the CPU
breaks down instructions into smaller stages (fetch, decode, execute, etc.).
 Each stage can handle a different instruction at the same time.
 For example:
• While one instruction is being executed, another is being decoded, and a third is
being fetched from memory.

 This overlap increases throughput, allowing more instructions to be processed in a given

time.
 Module 4
8086 Internal Architecture
 It is internally divided into two separate functional units. These are the Bus Interface
Unit (BIU) and the Execution Unit (EU).
 These two functional units can work simultaneously to increase system speed and hence
the throughput.
 Throughput is a measure of number of instructions executed per unit time.
 Fig. 6.2 shows a block diagram of the 8086 internal architecture


 Functions of Bus Interface Unit
 It sends address of the memory or I/O.
 It fetches instruction from memory.
 It reads data from port/memory.
 It Writes data into port/memory.
 It supports instruction queuing.
Instruction Queue:
•To speed up program execution, the BIU fetches six instruction bytes ahead of time from
the memory.
• These pre-fetched instruction bytes are held for the execution unit in a group of registers
called Queue.
• With the help of queue it is possible to fetch next instruction when current instruction is
in execution.
• During this execution time the BIU fetches the next instruction or instructions from
memory into the instruction queue.
Execution Unit[EU]
 The execution unit of 8086 Internal Architecture tells the BIU from where to fetch
instructions or data, decodes instructions and executes instructions. It contains :-
 Control Circuitry • Instruction Decoder • Arithmetic Logic Unit (ALU) • Flag Register
• General Purpose Registers • Pointers and Index Registers
Mention the purpose of segment registers of 8086
The 8086 microprocessor uses segment registers to address memory locations.
It uses a segmented memory model, which means memory is divided into segments, and the
segment registers hold the starting address of these segments.
Here are the four main segment registers and their purposes:

1. Code Segment (CS):

• Holds the base address of the code segment where the program instructions
(code) are stored. The CPU fetches the instructions to be executed from this segment.
2. Data Segment (DS):
• Contains the base address of the data segment where the program’s data
(variables, constants) is stored. Data can be accessed or manipulated from this segment.
3. Stack Segment (SS):
• Holds the base address of the stack segment. The stack is used for managing
function calls, local variables, and storing return addresses. It grows downward in memory.
4. Extra Segment (ES):
• Provides an additional segment that is mainly used for string operations. It
allows data movement between segments.
MULTICOREPROCESSOR
A multicore processor is a single integrated circuit that contains multiple core processing units,
more commonly known as cores.
There are many different multicore processor architectures, which vary in terms of
● Number of cores -Different multicore processors often have different numbers of cores.
For example, a quad-core processor has four cores. The number of cores is usually a power of
two.
● Number of core types:-
1. Homogeneous (symmetric) cores. All of the cores in a homogeneous multicore processor are
of the same type; typically the core processing units are general-purpose central processing
units that run a single multicore operating system.
2. Heterogeneous (asymmetric) cores. Heterogeneous multicore processors have a mix of core
types that often run different operating systems and include graphics processing units.
General purpose registers of 8086
 The *8086 microprocessor* has a set of *general-purpose registers
 They are used for data manipulation, arithmetic, logic operations, and addressing
purposes.
 These registers are 16-bit and can also be used as 8-bit registers (splitting into high and
low bytes).
 The general-purpose registers in the 8086 microprocessor are :-
1. AX (Accumulator Register)
2. BX (Base Register)
3. CX (Count Register)
4. DX (Data Register)
5. SI (Source Index)
6. DI (Destination Index)
7. BP (Base Pointer)
8. SP (Stack Pointer)
 General purpose registers and their uses given below
  These registers can be used directly by the programmer for different tasks and
provide a versatile mechanism for managing data and memory in the 8086
microprocessor.
Pentium processor
Outline any three features of Pentium processor
Three key features of the Pentium processor:

1. Superscalar Architecture: The Pentium processor features a dual pipeline that allows it to
execute two instructions simultaneously, improving processing speed compared to earlier
processors like the 486, which could only execute one instruction at a time.

2. 64-bit Data Bus: The Pentium has a 64-bit external data bus, which allows it to transfer more
data at once between the processor and memory, enhancing performance. Internally, it
processes data using a 32-bit architecture.

3. Branch Prediction: Pentium processors include branch prediction technology, which predicts
the outcome of conditional operations. This helps to reduce delays by pre-loading instructions,
thus improving execution efficiency.
 SELF EVALUATION SHEET
SL TOPIC STUDIED/NOT SIGNATURE SIGNATURE OF
NO. STUDIED OF STUDENT STAFF
1. Functional Units of a computer system

2. Bus interconnection
3. SRAM & DRAM comparison
4. Memory Hierarchy

5. Cache Memory
6. Virtual Memory

7. I/O Interfacing with memory mapped

& Programmed I/O
8. Handling Multiple Interrupts

9. DMA

10. Standard I/O interfaces

11. Flat panel Display Monitor & Printer

12. Executing an Instruction

13. Internal structure of CPU

14. Basic register transfer

15. Pipelining

16. 8086 internal Architecture

17. Segment registers of 8086

18. Multicore processor

19. General purpose registers of 8086

20. Pentium Processor