International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS-2017)

Performance Optimized Digital QPSK Modulator

Mansi Jain Pratyush Shandilya
Electronics and Communication Engineering Electronics and Communication Engineering
Maulana Azad National Institute of Technology Maulana Azad National Institute of Technology
Bhopal, India Bhopal. India

Palbha Kesharwani Sushmita Haldar

Electronics and Communication Engineering Electronics and Communication Engineering
Maulana Azad National Institute of Technology Maulana Azad National Institute of Technology
Bhopal, India Bhopal, India

Ashwini Kumar Malviya Himanshu Rai

Electronics and Communication Engineering Electronics and Communication Engineering
Maulana Azad National Institute of Technology Maulana Azad National Institute of Technology
Bhopal, India Bhopal, India

Kavita Khare Supriya Aggarwal

Electronics and Communication Engineering Electronics and Communication Engineering
Maulana Azad National Institute of Technology Maulana Azad National Institute of Technology
Bhopal, India Bhopal. India

Abstract— Quadrature Phase Shift Keying (QPSK) modulation is amplitude remain the same. Two consecutive bits of the input
a popular digital modulation technique. Though it consumes less sequence are observed, and the QPSK signal is generated
power and is quite compact as compared to other digital accordingly. The first bit gives the in-phase (I) component and
modulation technique, the objective of this paper is to propose a the second bit gives the quadrature (Q) phase component.
method for QPSK modulation which further reduces power
consumption, reduces memory requirement and improves the With four phases, QPSK modulator can encode 2 bits per
speed of operation by increasing the maximum operating symbol. This can be used either to make the bit rate of the
frequency. The proposed modulation method brings changes in signal twice as compared to the BPSK signal, maintaining the
Direct Digital Frequency Synthesizer (DDFS) block in the bandwidth, or to halve the required bandwidth, maintaining
conventional QPSK modulation technique, which results in the the same bit rate as of the BPSK modulator. Though QPSK
improvement of various performance parameters. Here, the modulator transmits symbols with lower bit rate as compared
input is the bit sequence generated by a pseudorandom number
(PN) generator and the output is the QPSK modulated signal.
to other digital modulation technique like Quadrature
Amplitude Modulation (QAM) 32 and QAM 64, its low power
Keywords— Quadrature Phase Shift Keying, CORDIC, sine, consumption and less complex transmitting and receiving
cosine circuit make it more popular.

I. INTRODUCTION For the last few decades, efforts have been made to produce
With the increasing need for cellular telephony and high speed, low power and compact devices. Speed, power
wireless data application, wireless communication has become and size are the three basic design constraints and improving
the base for the communication system today. For wireless either of them may result in degradation of the other two
communication, high data rate is required, which is achieved performance parameters. However, efforts are made to
by modulation. One very popular digital modulation technique improve all the three parameters at the same time.
is Quadrature Phase Shift Keying (QPSK). QPSK is used in
various cellular wireless standards such as GSM, CDMA, II. QPSK MODULATOR IMPLEMENTATIONS
LTE, 802.11 WLAN, 802.16 fixed and mobile WiMAX, A. Conventional QPSK Modulator
Satellite and CABLE TV applications [1].
A QPSK modulator works by dividing the input binary
In case of QPSK modulation technique, change in phase is sequence into 2 streams, even and odd, using a de-multiplexer.
observed with the input bit sequence, while the frequency and Non-Return to Zero (NRZ) coding technique is then applied to

978-1-5386-1887-5/17/$31.00 ©2017 IEEE

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 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS-2017)

the resultant unipolar data. The coded data is then mixed with phase accumulator. Thus, the cosine and sine waveforms are
the high frequency carrier wave, generated from Direct Digital generated.
Frequency Synthesizer (DDFS) as shown in figure (1). The
DDFS block produces sine and cosine waves of same
frequency. These sine and cosine waves are then mixed with
the generated odd and even stream to produce I phase and Q
phase respectively.
The two phases produced are then added together to
produce a QPSK modulated wave. The general mathematical
form of QPSK signal is shown in Eq. 1, where fc is the carrier

Figure 1: Block diagram of QPSK

B. Modulator
C.

frequency produced from the DDFS block, Es is energy per B. Optimized QPSK Modulator-I
symbol and Ts is symbol period [1]:
In order to optimize the performance of QPSK modulator [1],
ଶ୉౏ ሺଶ୧ିଵሻ we tried an implementation in which the values of the sinusoid
ܳሺ‫ݐ‬ሻ ൌ ට ‘•ቀʹɎˆୡ – ൅  Ɏቁ (1)
୘౏ ସ for 4 phases of the QPSK modulated signal are stored in four
separate RAM blocks, each RAM block storing the values for
Where i=1,2,3,4
one phase. The values for one phase corresponding to the
In case of digital QPSK modulator, RAM blocks are used combination of bit pair at the input (00, 01, 10, 11) are given
to store values of sine and cosine. The values of these RAM at the output. The QPSK modulated signal is thus generated.
blocks are then added or subtracted depending on the values of Due to these 4 RAM blocks, QPSK modulator no longer
odd and even data bits, creating phases for QPSK signal. needs to generate the phase for each bit pair by
Table 1shows distinct phases for a QPSK signal. adding/subtracting the I and Q phases. This eliminates
arithmetic operations, hence reducing power consumption and
Table 1: I and Q phase for QPSK modulated signal increasing the maximum frequency allowed.

Odd bit Even bit I-phase Q-phase C. Optimized QPSK Modulator-II

0 0 -cos(Ȧct) -sin(Ȧct) To further optimize the QPSK modulator, CORDIC

algorithm was used to generate sine and cosine values for the
0 1 -cos(Ȧct) sin(Ȧct) angles given by phase accumulator [3]. Because of this
1 0 cos(Ȧct) - sin(Ȧct) algorithm, no RAM block was required to store the values of
sine and cosine; rather, the values for a particular angle were
1 1 cos(Ȧct) sin(Ȧct)
generated at run-time.
This digital QPSK modulator reduces power consumption by CORDIC algorithm gives sine and cosine value for an
using RAM blocks and a phase accumulator, instead of using angle after i iterations, with i less than or equal to the length of
analog oscillators for sinusoidal waveform generation. The bit vector used to represent the value. However, with the help
phase accumulator gives the values of angles at each clock of pipelined CORDIC algorithm, i iterations are performed
edge, the sine and cosine values of whose are provided by the simultaneously, thus generating one value in each clock cycle.
RAM. The angles are spaced by a constant step size of the

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The computation of values using the algorithm eliminated Figure 2 shows the QPSK modulated waveform obtained
the use of Look up tables of sine and cosine values. Thus, the through simulation.
memory required was reduced by a large amount. The only
values stored were inverse tangents of 2-i, with i varying from IV. PERFORMANCE ANALYSIS
0 to 7 for 8 iterations. The use of pipelining allowed 8 The project was designed in Xilinx ISE Design Suite 14.4
computations simultaneously and hence the throughput was using VHDL. The device used was Spartan 3E Starter Kit. The
equal to the clock frequency, as opposed to clock frequency performance of different implementations was analyzed with
divided by 8 in case of non-pipelined mode [4]. the help of synthesis reports generated by ISE Design Suite
and Power Analyzer. Table 1 summarizes the performance of
D. The CORDIC Algorithm the three implementations.

CORDIC algorithm works on the principle of vector rotation

[3]. It can be used to compute all the trigonometric functions. A. Power Analysis
This algorithm uses iterative method for performing vector For all the 3 implementations for QPSK modulator, power
rotation by performing shifts and adds [2],[3]. The algorithm consumption is estimated using Power Analyzer. For the
is derived from general rotation theorem [2],[3]: conventional digital QPSK modulator, the power consumption
obtained was about 0.083W.
‫ ݔ‬ᇱ ൌ ‫ ߮ݏ݋ܿݔ‬െ ‫߮݊݅ݏݕ‬ሺʹሻ
‫ ݕ‬ᇱ ൌ ‫ ߮ݏ݋ܿݕ‬൅ ‫߮݊݅ݏݔ‬ሺ͵ሻ The second implementation of QPSK modulator included use
which rotates in Cartesian plane at an angle ij, that can be of 4 RAM blocks to store 4 distinct phases of QPSK
arranged as [2],[3]: modulator. In this implementation, the power consumption
was found to be reduced to 0.081W, because unlike
‫ ݔ‬ᇱ ൌ ܿ‫߮ݏ݋‬ሾ‫ ݔ‬െ ‫߮݊ܽݐݕ‬ሿሺͶሻ conventional method, this implementation used no arithmetic
‫ ݕ‬ᇱ ൌ ܿ‫߮ݏ݋‬ሾ‫ ݕ‬൅ ‫߮݊ܽݐݔ‬ሿሺͷሻ operation for phase calculation, rather the phases were pre-
calculated and stored in RAM blocks.
If the rotation angle is taken as tan(ij) = ±2-i, the multiplication
For the third implementation, involving CORDIC algorithm
by tangent term is simply reduced to shift operation. Now, the
for sine and cosine values generation, the power consumption
angle of rotation can be obtained by a series of small rotation
obtained from the Power Analyzer report was same as that of
operations. The decision is then taken in which direction, the
the second implementation, i.e. no extra power was consumed
vector to be rotated at each iteration, i. The iterative rotation
in case of CORDIC implementation.
can be explained as [2],[3]:
B. Memory Analysis
‫ݔ‬௜ାଵ ൌ ‫ܭ‬௜ ሾ‫ݔ‬௜ െ ‫ݕ‬௜ Ǥ ݀௜ Ǥ ʹି௜ ሿ (6) As per the Synthesis reports generated in Xilinx ISE Design
‫ݕ‬௜ାଵ ൌ ‫ܭ‬௜ ሾ‫ݕ‬௜ ൅ ‫ݔ‬௜ Ǥ ݀௜ Ǥ ʹି௜ ሿ (7) Suite, the conventional QPSK modulator made use of 2 ROM
where blocks to store sine and cosine values. The second
‫ܭ‬௜ ൌ ‘•ሺ‫ି݊ܽݐ‬௜ ʹି௜ ሻ ൌ ͳൗ (8) implementation used 4 RAM blocks for storing 4 phases of
ξͳ ൅ ʹିଶ௜ QPSK modulator. Though this implementation reduced power
݀௜ ൌ േͳ consumption, area was increased because of use of more
Removing the scale constant from the equations gives a shift-
memory blocks than the conventional technique.
add algorithm for vector rotation. This Ki can act as a system
processing gain. When the number of iterations approaches
Third implementation, using CORDIC algorithm made use of
infinity, then the product approaches 0.6073. and the gain, An
no RAM/ROM block, as the values were generated during run
approaches 1.647[1], as the gain is given by:
time. This reduces the overall area for this implementation of
the QPSK modulator.
‫ܣ‬௡ ൌ ς ξͳ ൅ ʹିଶ௜ (9)

This processing gain An depends on the number of iterations C. Speed Analysis

performed. Maximum allowed frequency of a circuit is the performance
parameter which decides the overall speed of the circuit.
III. SIMULATION RESULTS Maximum allowed frequency in case of the conventional
For simulation, a pseudo noise (PN) sequence generator is QPSK modulator was found to be 103.008MHz.
used, which generates random bit sequence to give different
combinations of input. In the random bit sequence generated, Maximum allowed frequency for the second implementation
2 consecutive bits are taken at a time to form a symbol and was 133.458MHz. This implies that the speed is more in case
according to those 2 bits, the required RAM block is accessed. of second implementation as compared to the conventional
The simulation results were observed in ISim and Vivado. method. Maximum frequency for the third implementation
was found to be 156.611MHz, which is the maximum among

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all the three implementations. This implies that the QPSK

modulator created using CORDIC algorithm is the fastest
among the implementations discussed in the paper.

Figure 2: Simulation result- QPSK modulated signal

Table 2: : Performance results of the three implementations

Implementation Power Memory Maximum Frequency Complexity

1. DDS-Based 0.083 W 36 X 7 X 8 103.008MHz Minimum

ROM
2. 4 RAM Blocks-Based 0.081 W 36 X 17 X 4 RAM 133.458MHz Medium

3. CORDIC 0.081 W 0 RAM/ROM 156.611MHz Maximum

Acknowledgement
V. CONCLUSION
We would like to thank our Head of the Department and all
The performance analysis shows that the QPSK modulator the lab staff who supported us and helped us to carry out our
using CORDIC algorithm for sine and cosine waveform work.
generation gave the best results in terms of speed, memory
requirements and power consumption.

References [3]. Ansuman Mishra, Sivanantham S and Sivasankaran K, “Sine

and cosine generator using CORDIC algorithm implementation in
[1]. A.M. Moubark, Mohd Alauddin Mohd Ali, H. Sanusi, S. Md ASIC”, in Online International Conference on Green Engineering
Ali, “FPGA Implementation of low power digital QPSK modulator and Technologies (IC-GET 2015)
using Verilog HDL” in Journal of Applied Sciences 13(3):385-
392, 2013 [4]. Deprettere, E., Dewilde, P., and Udo, R., “Pipelined CORDIC
architecture for fast VLSI filtering and array processing,” Proc.
[2]. R. Andraka, “A survey of CORDIC algorithms for FPGA ICASSP’84, 1984, pp. 41.A.6.1-41.A.6.4
based computers,” in Sixth International Symposium on Field
Programmable Gate Arrays, Monterey, CA, February 22-24, 1998.

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