REVIEW ARTICLE | JUNE 03 2020

Pathways to efficient neuromorphic computing with non-

volatile memory technologies 
Special Collection: Brain Inspired Electronics

I. Chakraborty  ; A. Jaiswal; A. K. Saha; S. K. Gupta ; K. Roy

Appl. Phys. Rev. 7, 021308 (2020)

https://doi.org/10.1063/1.5113536
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Pathways to efficient neuromorphic computing

with non-volatile memory technologies
Cite as: Appl. Phys. Rev. 7, 021308 (2020); doi: 10.1063/1.5113536
Submitted: 5 June 2019 . Accepted: 1 May 2020 .
Published Online: 3 June 2020

I. Chakraborty,a) A. Jaiswal, A. K. Saha, S. K. Gupta, and K. Roy

AFFILIATIONS
School of Electrical and Computer Engineering, Purdue University, 465 Northwestern Ave., West Lafayette, Indiana 47906, USA

Note: This paper is part of the special collection on Brain Inspired Electronics.
a)
Author to whom correspondence should be addressed: [email protected]

ABSTRACT
Historically, memory technologies have been evaluated based on their storage density, cost, and latencies. Beyond these metrics, the need to
enable smarter and intelligent computing platforms at a low area and energy cost has brought forth interesting avenues for exploiting non-
volatile memory (NVM) technologies. In this paper, we focus on non-volatile memory technologies and their applications to bio-inspired
neuromorphic computing, enabling spike-based machine intelligence. Spiking neural networks (SNNs) based on discrete neuronal “action
potentials” are not only bio-fidel but also an attractive candidate to achieve energy-efficiency, as compared to state-of-the-art continuous-

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valued neural networks. NVMs offer promise for implementing both area- and energy-efficient SNN compute fabrics at almost all levels of
hierarchy including devices, circuits, architecture, and algorithms. The intrinsic device physics of NVMs can be leveraged to emulate dynam-
ics of individual neurons and synapses. These devices can be connected in a dense crossbar-like circuit, enabling in-memory, highly parallel
dot-product computations required for neural networks. Architecturally, such crossbars can be connected in a distributed manner, bringing
in additional system-level parallelism, a radical departure from the conventional von-Neumann architecture. Finally, cross-layer optimization
across underlying NVM based hardware and learning algorithms can be exploited for resilience in learning and mitigating hardware inaccu-
racies. The manuscript starts by introducing both neuromorphic computing requirements and non-volatile memory technologies.
Subsequently, we not only provide a review of key works but also carefully scrutinize the challenges and opportunities with respect to various
NVM technologies at different levels of abstraction from devices-to-circuit-to-architecture and co-design of hardware and algorithm.
Published under license by AIP Publishing. https://doi.org/10.1063/1.5113536

TABLE OF CONTENTS 2. Metal-oxide RRAMs and CBRAMs as

I. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 synapses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
II. GENERIC NEURO-SYNAPTIC BEHAVIORAL AND 3. Metal-oxide RRAM and CBRAM crossbars. . . 13
LEARNING REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . 4 C. Spintronic devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
A. Neurons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. Spin devices as neurons. . . . . . . . . . . . . . . . . . . . 13
B. Synapses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Spin devices as synapses . . . . . . . . . . . . . . . . . . . 15
1. Unsupervised learning . . . . . . . . . . . . . . . . . . . . . 5 3. Spintronic crossbars . . . . . . . . . . . . . . . . . . . . . . . 16
2. Supervised learning . . . . . . . . . . . . . . . . . . . . . . . 6 D. Ferroelectric FETs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
III. NON-VOLATILE TECHNOLOGIES FOR 1. FEFETs as neurons. . . . . . . . . . . . . . . . . . . . . . . . 18
NEUROMORPHIC HARDWARE . . . . . . . . . . . . . . . . . . 6 2. FEFETs as synapses . . . . . . . . . . . . . . . . . . . . . . . 18
A. Phase change devices . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. FEFET crossbars . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1. PCM as neurons . . . . . . . . . . . . . . . . . . . . . . . . . . 7 E. Floating gate devices . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2. PCM as synapses . . . . . . . . . . . . . . . . . . . . . . . . . 8 1. Floating gate devices as neurons . . . . . . . . . . . . 19
3. PCM crossbars . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2. Floating gate devices as synapses . . . . . . . . . . . . 20
B. Metal-oxide RRAMs and CBRAMs . . . . . . . . . . . . . 10 3. Floating gate crossbars. . . . . . . . . . . . . . . . . . . . . 20
1. Metal-oxide RRAMs and CBRAMs as F. NVM architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
neurons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IV. PROSPECTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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A.
Stochasticity—Opportunities and challenges . . . . . 22 efficient spike-based information passing, robustness, and adaptability.
B.
Challenges of NVM crossbars . . . . . . . . . . . . . . . . . . 22 Interestingly, both the brain’s cognitive ability and its energy-
C.
Mitigating crossbar non-idealities . . . . . . . . . . . . . . 24 efficiency stem from basic computation and storage primitives called
D.
Multi-memristive synapses . . . . . . . . . . . . . . . . . . . . 24 neurons and synapses, respectively.
E.
Beyond neuro-synaptic devices and STDP . . . . . . . 25 Networks comprising artificial neurons and synapses have, there-
F.
NVM for digital in-memory computing . . . . . . . . . 25 fore, been historically explored for solving various intelligent problems.
G.
Physical integrability of NVM technology with Over the years, neural networks have evolved significantly and are
CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 usually categorized based on the characteristic neural transfer function
V. CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 as first, second, and third generation networks.4 As shown in Fig. 2,
AUTHORS’ CONTRIBUTION . . . . . . . . . . . . . . . . . . . . . . . . . 26 the first generation neurons, called as perceptrons,4 had a step function
response to the neuronal inputs. The step perceptrons, however, were
I. INTRODUCTION
not scalable to deeper layers and were extended to Multi-Layer
The human brain remains a vast mystery and continues to baffle Perceptrons (MLPs) using non-linear functional units.5 This is alluded
researchers from various fields alike. It has intrigued neuroscientists by to as the second generation neurons based on a continuous neuronal
its underlying neural circuits and topology of brain networks that output with non-linear characteristic functions such as sigmoid5 and
result in vastly diverse cognitive and decision-making functionalities ReLU (Rectified Linear Unit).6 Deep Learning Networks (DLNs) as we
as a whole. Equivalently, computer engineers have been fascinated by know it today are based on such second generation neural networks.
the energy-efficiency of the biological brain in comparison to the state- The present revolution in artificial intelligence is being currently fueled
of-the-art silicon computing solutions. For example, the Bluegene by such DLNs using global learning algorithms based on the gradient
supercomputer1 consumed mega-watts of power2 for simulating the descent rule.7 Deep learning has been used for myriad of applications
activity of cat’s brain.3 This is in contrast to 20 W of power account- including classification, recognition, prediction, cognition, and deci-
ing for much more complex tasks including cognition, control, move- sion making with unprecedented success.8 However, a major require-
ment, and decision making, being rendered simultaneously by the ment to achieve the vision of intelligence everywhere is to enable
brain. The massive connectivity of the brain fueling its cognitive abili- energy-efficient computing much beyond the existing Deep learning
ties and the unprecedented energy-efficiency makes it by far the most solutions. Toward that end, it is expected that networks of spiking neu-
remarkable known intelligent system. It is, therefore, not surprising rons hold promise for building an energy-efficient alternative to tradi-

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that in the quest to achieve “brain-like cognitive abilities with brain- tional DLNs. Spiking neural networks (SNNs)—the third generation
like energy-efficiency,” researchers have tried building Neuromorphic of neural networks—are based on the bio-plausible neural behavior
Systems closely inspired by the biological brain (refer Fig. 1). Worth and communicate through discrete spikes as opposed to the continu-
noting is the fact that neuromorphic computing not only aims at ous valued signal of DLNs. Note that for this paper, we refer the sec-
attaining the energy-efficiency of the brain but also encompasses ond generation networks as DLNs and the third generation spiking
attempts to mimic its rich functional principles such as cognition, networks as SNNs.

FIG. 1. Neuromorphic computing as a brain-inspired paradigm to achieve cognitive ability and energy-efficiency of the biological brain. “Hardware” and “Algorithms” form the
two key aspects for neuromorphic systems. As shown in the right hand side, a generic neuromorphic chip consists of several “Neuro-Cores” interconnected through the
address event representation (AER) based network-on-chip (NOC). Neuro-Cores consist of arrays of synapses and neurons at the periphery. Non-volatile technologies
including PCM, RRAM, MRAM, and FG devices have been used to mimic neurons and synapses at various levels of bio-fidelity.

Appl. Phys. Rev. 7, 021308 (2020); doi: 10.1063/1.5113536 7, 021308-2

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FIG. 2. Three generations of neural networks. First generation (Gen-I) of networks used step transfer functions and were not scalable, and second generation (Gen-II) uses transfer functions
such as Rectified Linear Unit (ReLU) that has fueled today’s deep learning networks. The third generation (Gen-III) uses spiking neurons resembling the neural activity of their biological coun-
terparts. The three components of an SNN are (1) neurons, (2) synapses, and (3) learning. (1) Neurons: three broad classes of spiking neurons that researchers attempt to mimic using NVMs
are Leaky-Integrate-Fire (LIF), Integrate-Fire (IF), and Stochastic Neurons. (2) Synapses: the key attributes needed for a particular device to function as a synapse are its ability to map synaptic
efficacy (wherein a synaptic weight modulates the strength of the neuronal signal) and that they can perform multiplication and dot-product operations. (3) Learning: as shown in the figure,
learning can be achieved either through supervised or unsupervised algorithms. From an NVM perspective, various NVM technologies are being used to mimic neuronal and synaptic function-
alities with appropriate learning capabilities. At an architectural level, arrays of such NVMs are connected through the network-on-chip to enable seamless integration of a large neural network.

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From the energy-efficiency perspective, SNNs have two key aspects of biological neurons and synapses. Let us highlight few repre-
advantages. First, the fact that neurons exchange information through sentative behaviors for both neurons and synapses that form the basic
discrete spikes is explicitly utilized in hardware systems to enable set of neuro-synaptic dynamics usually replicated through non-volatile
energy-efficient event-driven computations. By event-driveness, it is devices.
implied that only those units in the hardware system are active, which
have received a spike, and all other units remain idle reducing the A. Neurons
energy expenditure. Second, such an event-driven scheme also enables Neural interactions are time varying electro-chemical dynamics
Address Event Representation (AER).9 AER is an asynchronous com- that gives rise to brain’s diverse functionalities. These dynamical
munication scheme, wherein the sender transmits its address on the behaviors in turn are governed by voltage dependent opening and
system bus and the receiver regenerates the spikes based on the closing of various charge pumps that are selective to specific ions such
addresses it receives through the system bus. Thereby, instead of trans- as Naþ and Kþ.10,11 In general, a neuron maintains a resting potential,
mitting and receiving the actual data, event addresses are exchanged across its cell membrane by maintaining a constant charge gradient.
between the sender and the receiver, leading to energy-efficient trans- Incoming spikes to a neuron lead to an increase in its membrane
fer of information. potential in a leaky-integrate manner until the potential crosses a cer-
In addition to emulation of neuro-synaptic dynamics and use of tain threshold after which the neuron emits a spike and remains non-
event-driven hardware, two notable developments, namely, (1) the responsive for a certain period of time called as the refractory period. A
emergence of various non-volatile technologies and (2) the focus on typical spike (or action potential) is shown in Fig. 3 highlighting the
learning algorithms for networks of spiking neurons, have accelerated specific movements of charged ions through the cell membrane.
the efforts in driving neural network hardware closer toward achieving Additionally, it has been known that the firing activity of neurons is
both energy-efficiency and improved cognitive abilities. Non-volatile stochastic in nature.12,13
technologies have facilitated area- and energy-efficient implementa- Having known the generic qualitative nature of neural function-
tions of neuromorphic systems. As we will see in Sec. III of the manu- ality, it is obvious that a resulting model, describing the intricacies of a
script, these devices are of particular interest since they are governed biological neuron, would consist of complex dynamical equations. In
by intrinsic physics that can be mapped directly to certain aspects of fact, detailed mathematical models such as Hodgkin–Huxley model14
biological neurons and synapses. This implies that instead of using and spike response model have been developed, which closely match
multiple transistors to imitate neuronal and synaptic behavior, in the behavior of biological neurons. However, implementing such mod-

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many cases, a single non-volatile device can be used as a neuron or a els in hardware turns out to be a complex task. As such, hardware
synapse with various degrees of bio-fidelity. In addition, a major bene- implementations mostly focus on simplified neuronal models, such as
factor for non-volatile memory (NVM) technologies is that they can Leaky-Integrate-Fire (LIF) model15–17 shown in Fig. 3. Consequently,
be arranged in dense crossbars of synaptic arrays with neurons at the the diverse works on mimicking neurons using non-volatile technolo-
periphery. This is of immense importance since the co-locations of gies can be categorized into three genres—(1) the Leaky-Integrate-Fire
compute (neuronal primitives) and storage (synaptic primitives) are (LIF) neurons, (2) the Integrate-Fire (IF) neurons, and (3) Stochastic-
inherent characteristics that make the biological brain so effective. Firing (s-F) neurons. Figure 2 graphically represents the typical neural
Note that this closely intertwined fabric of compute and storage is con- behavior for each type of neuron, while Fig. 3(c) presents a Venn-
spicuously different from state-of-the-art computing systems that rely diagram highlighting various works based on non-volatile technologies
on the well-known von-Neumann model with segregated compute and the corresponding neural behavior that they are based on.
and storage units. Additionally, learning algorithms for networks of
spiking neurons has recently attracted considerable research focus. For • Leaky-Integrate-Fire (LIF) neurons: The membrane potential of
this paper, we would define neuromorphic computing as SNN based an LIF neuron is incremented at every instance when the neuron
neural networks, associated learning algorithms, and their hardware receives an input spike. In the interval between two spikes, the
implementations. neuron potential slowly leaks, resulting in the typical leaky-
In this paper, we focus on non-volatile technologies and their integrate behavior shown in Fig. 2. If the neuron receives suffi-
applications to neuromorphic computing. With reference to Fig. 2, we cient input spikes, its membrane potential crosses a certain
start in Sec. II by first describing the generic neural and synaptic threshold, eventually allowing the neuron to emit an output
behavioral characteristics that are in general emulated through non- spike.
volatile devices. Subsequently, in Sec. III, we describe learning strate- • Integrate-Fire (IF) neurons: The IF neuron is a simplified version
gies for SNNs and associated topologies. With the knowledge of basic of the LIF neuron without the leaky behavior. Essentially, an IF
neuro-synaptic behavior and learning methodologies, Sec. IV presents neuron increments its membrane potential at every spike main-
non-volatile memories as the building block for neuromorphic sys- taining its potential at a constant value between two spikes, as
tems. Finally, before concluding, we highlight on future prospects and shown in Fig. 2. IF neurons fire when the accumulated mem-
key areas of research that can further the cause of neuromorphic hard- brane potential crosses a pre-defined threshold.
• Stochastic-Firing neurons: In contrast to deterministic neurons
ware by exploiting non-volatile technologies.
that fire whenever the neuron crosses its threshold, a stochastic
II. GENERIC NEURO-SYNAPTIC BEHAVIORAL AND firing neuron fires with a probability, which is proportional to its
LEARNING REQUIREMENTS membrane potential. In other words, for a stochastic neuron, an
One of the key advantages of non-volatile technologies is that output spike is emitted with a certain probability, which is a
their intrinsic device characteristics can be leveraged to map certain function of the instantaneous membrane potential. In its simplest

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FIG. 3. (a) The biological neuron and a typical spiking event. Various ions and the role they play in producing the spiking event are shown. (b) A simplified neural computing

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model highlighting the flow of information from the input of neurons to the output. Spikes from various pre-neurons are multiplied by the corresponding weights and added
together before being applied as an input to the neuron. The neuron shows a typical leaky-integrate behavior unless its membrane potential crosses a certain threshold, leading
to emission of a spike. (c) The LIF differential equation.

form, a stochastic firing behavior can be modeled by a firing manipulating the release of neurotransmitters and controlling the
probability, which increases with the input stimulus. However, responsiveness of the cells to them. Such plasticity is believed to be the
stochasticity can also be combined with LIF and IF neurons, such fundamental basis of learning and memory in the biological brain.
that once the neuron crosses the threshold, it only emits a spike From the neuromorphic perspective, synaptic learning strategies can
based on a probabilistic function. be broadly classified into two major classes: (1) unsupervised learning
and (2) supervised learning.
LIF neurons are most widely used in the domain of SNNs. The
leaky nature of LIF neurons renders a regularizing effect on their firing
rates. This can help particularly for frequency based adaptation mech- 1. Unsupervised learning
anisms that we will discuss in the next section.18 IF neurons are typi-
cally used in supervised learning algorithms. In these algorithms, the Unsupervised learning is a class of learning algorithms associated
learning mechanism does not have temporal significance, and hence, with self-organization of weights without the access to labeled data. In
temporal regularization is not required. Stochastic neurons, on the the context of hardware implementations, unsupervised learning
other hand, have a different computing principle. Due to the probabil- relates to biologically inspired localized learning rules where the weight
istic nature of firing, it can also act as a regularizer and also lead to bet- updates in the synapses depend solely on the activities of the neurons
ter generalization behavior in neural networks. All the aforementioned on its either ends. Unsupervised learning in spike-based systems can
neurons can leverage the inherent device physics in NVM devices for be broadly classified into (i) Spike Timing Dependent Plasticity
efficient hardware implementation. (STDP) and (ii) frequency dependent plasticity.
Spike timing dependent plasticity (STDP), shown in Fig. 4, is a
learning rule, which strengthens or weakens the synaptic weight based
B. Synapses on the relative timing between the activities of the connected neurons.
Information in biological systems is governed by transmission of This kind of learning was first experimentally observed in rat’s hippo-
electrical pulses between adjacent neurons through connecting bridges, campal glutamatergic synapses.19 It involves both long-term potentia-
commonly known as synapses. Synaptic efficacy, representing the tion (LTP),20 which signifies the increase in the synaptic weight2þ, and
strength of connection through an internal variable, is the basic crite- long-term depression (LTD), which signifies a reduction in the synap-
rion for any device to work as an artificial synapse. Neuro-chemical tic weight. LTP is realized through STDP when the post-synaptic neu-
changes can induce plasticity in synapses by permanently ron fires after the pre-synaptic activity, whereas LTD results from an

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acausal spiking between the pre-synaptic and post-synaptic neurons,

wherein the post-synaptic neuron fires before the pre-synaptic neuron.
Mathematically, the relative change in synaptic strength is depen-
dent on the timing difference of the post-synaptic and pre-synaptic
spikes as

dwðDtÞ ¼ Aþ expðDt=sþ Þ if Dt > 0; (1)

¼ A expðDt=s Þ if Dt < 0: (2)
Here, Aþ, A, sþ ; s are the amplification coefficients and time-
constants, respectively, and Dt is defined as the difference between the
pre-synaptic and post-synaptic firing instants. STDP has been widely
adopted in not only computational neuroscience but also neuromor-
phic systems as the de facto unsupervised learning rule for pattern
detection and recognition.
In conjunction to long-term modification of synaptic weights,
the physiology of synapses induces yet another type of learning, i.e.,
frequency dependent plasticity, dependent on the activity of the pre-
synaptic potential.21,22 Activity-dependent learning can induce two
types of changes in the synaptic strength. The change occurring over a
short timescale (hundreds of milliseconds in biological systems) is
known as Short-Term Plasticity (STP), while the long-term effects are
a form of LTP that can last between hours to years. In general, at a
given instance, a pre-synaptic activity induces STP; however, when the
pre-synaptic activity reduces, the synaptic efficacy is reverted back to
its original state. Repeated stimuli eventually result in LTP in the syn-
apses. As STP corresponds to the recent history of activity and LTP

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relates to long-term synaptic changes resulting from activity over a
period of time, they are often correlated with short-term memory
(STM) and long-term memory (LTM), respectively, in mammals.23

2. Supervised learning
Although unsupervised learning is believed to form the dominant
part of learning in biological synapses, the scope of its applicability is
still in its nascent stages in comparison to conventional deep learning.
An alternative ex situ learning methodology to enable spike-based
processing in deep SNNs is restricting the training to the analog
domain, i.e., using the greedy gradient descent algorithm as in conven-
tional DLNs and converting such an analog valued neural network to
the spiking domain for inferencing. Various conversion algo-
rithms24–26 have been proposed to perform nearly lossless transforma-
tion from the DLN to the SNN. These algorithms address several
concerns pertaining to the conversion process, primarily emerging due
to differences in neuron functionalities in the two domains. Such con-
version approaches have been demonstrated to scale to state-of-art
neural network architectures such as ResNet and VGG performing
classification tasks on complex image datasets as in ImageNet.27 More
FIG. 4. Different kinds of learning strategies can be broadly classified into (i) spiking
timing dependent plasticity (STDP), (ii) frequency dependent plasticity, and (iii) gradient- recently, there has been a considerable effort in realizing gradient-
based learning. STDP induces both potentiation and depression of synaptic weights in a based learning in the spiking domain itself28 to eliminate conversion
non-volatile fashion based on the difference in spike timing of pre-neurons and post- losses.
neurons, Dt. Classical STDP assumes an exponential relationship with Dt, as demon-
strated by Bi and Poo.19 Other variants of STDP have also been observed in mamma- III. NON-VOLATILE TECHNOLOGIES FOR
lian brains. Frequency dependent plasticity manifests itself in the form of short-term NEUROMORPHIC HARDWARE
plasticity (STP) and long-term potentiation (LTP). The change in the synaptic weight, in
this case, depends on how frequently the synapse receives stimulus. STP and LTP form
As elaborated in Sec. II, SNNs not only are biologically inspired
the basis of short-term and long-term memory in biological systems. Finally, gradient- neural networks but also potentially offer energy-efficient hardware
based learning is a supervised learning scheme where the change in the synaptic weight solutions due to their inherent sparsity and asynchronous signal
depends on gradients calculated from error between the predicted and the ideal output. processing. Advantageously, non-volatile technologies provide two

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additional benefits with respect to neuromorphic computing. First, the about possible commercial offerings—for high density, large-scale
inherent physics of such devices can be exploited to capture the func- storage solutions.31 These materials can encode multiple intermediate
tionalities of biological neurons and synapses. Second, these devices states, rendering them the capability of storing multiple bits in a single
can be connected in a crossbar fashion allowing analog-mixed signal cell. More recently, PCM devices have also emerged as a promising
in-memory computations, resulting in highly energy-efficient hardware candidate for neuromorphic computing due to their multi-level stor-
implementations. age capabilities. In this section, we discuss various neuromorphic
In this section, we first delve into the possibilities and challenges applications of PCM devices.
of such non-volatile devices, based on various technologies, used to
emulate the characteristics of synapses and neurons. Subsequently, we 1. PCM as neurons
describe how crossbar structures of such non-volatile devices can be
used for in-memory computing and the associated challenges. PCM devices show reversible switching between amorphous and
crystalline states, which have highly contrasting electrical and optical
properties. In fact, this switching dynamics can directly lead to inte-
A. Phase change devices grate and firing behaviors in PCM-based neurons. The device struc-
Phase change materials (PCMs) such as chalcogenides are the ture of such a neuron comprises a phase change material sandwiched
front-runners among emerging non-volatile devices—with speculation between two electrodes, as shown in Fig. 5(a). The mushroom

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FIG. 5. (a) Device structure of a PCM-based IF neuron.29 The thickness of the amorphous region (shown in red) represents the membrane potential of the neuron. The inte-
grating and firing behaviors for different incident pulse amplitudes and frequencies are shown (bottom). (b) Device structure of a photonic IF neuron based on PCM (GST).30
The input pulses coming through the INPUT port get coupled to the ring waveguide and eventually to the GST element, changing the amorphous thickness. The output at the
“THROUGH” port represents the membrane potential, which depends on the state of the GST element.

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structure shows the shape of the switching volume just above the performed when an exponential current above the threshold voltage
region known as the heater. The heater is usually made of resistive ele- leads to heating of the material above its crystallization temperature
ments such as W, and high current densities at the contact interface and switches it to the crystalline state, as depicted by the I–V charac-
between the phase change material and the heater cause locally con- teristics in Fig. 6(a). The crystallization (or “SET”) pulses are much
fined Joule heating. When the PCM in the neuron is in its initial amor- longer as opposed to amorphization (or RESET) pulses, as shown in
phous state, a voltage pulse that has an amplitude low enough so as to Fig. 6(b). Multiple states are achieved by progressively crystallizing the
not melt the device but high enough to induce crystal growth can be material, thus reducing the amorphous thickness.
applied. The resulting amorphous thickness, ua, on application of such These multi-level PCM synapses can be used to perform unsu-
a pulse is given as29 pervised on-chip learning using the STDP rule.33 LTP and LTD using
STDP involves a gradual increase and decrease in conductance of
dua PCM devices, respectively. However, such a gradual increase or
¼ vg ðRth ðua ÞPp þ Tamb Þ; ua ð0Þ ¼ u0 (3)
dt decrease in conductance needs to ensure precise control, which is diffi-
where vg is the crystal growth velocity dependent on the temperature cult to achieve using identical current pulses. As a result, by configur-
determined by its argument Rth ðua ÞPp þ Tamb . Here, Rth is the thermal ing a series of programming pulses of increasing or decreasing
resistance and Tamb is the interface temperature between amorphous amplitude [Fig. 7(a)], both LTP and LTD have been demonstrated
and crystalline regions. The variable, ua, in Eq. (1) can be interpreted using PCM devices.34–36 In this particular scheme, the pre-spikes con-
as the neuron’s membrane potential where Pp is the input variable sist of a number of pulses of gradually decreasing or increasing pulses,
controlling the dynamics. On successive application of crystallization whereas the post-spike consists of a single negative pulse. The differ-
pulses, the amorphous thickness, ua, decreases, leading to lower con- ence between the magnitude of the pre-spike and post-spike due to
ductance and temporal integration of the membrane potential. overlap of the pulses varies with the time difference, resulting in the
Beyond a certain threshold conductance level, the neuron fires, or in change in conductance of the synapse following the STDP learning
other words, the PCM changes to a crystalline state. A reset mecha- rule. The scheme for potentiation is explained in Fig. 7(a). A simplified
nism puts the neuron back in its original amorphous state. The afore- STDP learning rule with constant weight update can also be imple-
mentioned integrate-and-fire characteristics in PCM neurons are mented using a single programming pulse by shaping the pulses
accompanied by inherent stochasticity. The stochasticity arises from appropriately33 as shown in Fig. 7(b). However, such pulse shaping
different amorphous states created by repeated resets of the neuron. requires additional circuitry. These schemes rely on single PCM devi-
ces representing a synapse. Alternatively, using a “2-PCM” synapse,

28 May 2024 04:41:53

Different initial states lead to different growth velocities, which result
in an approximate Gaussian distribution of inter-spike intervals, the one can potentially implement LTP and LTD characteristics that can
interval between adjacent firing events. Populations of such stochastic be independently programmed. Such a multi-device implementation
IF neurons have also been used in detection of temporal correlation in becomes important for PCM technology as the amorphization is an
parallel data streams.32 abrupt process, and it is difficult to control the progression of different
Thus far, we have talked about electronic devices mimicking neu- amorphization states, which poses a fundamental limitation toward
ronal behavior using PCM. Such behavior can also be achieved with Si- realizing both LTP and LTD in a single device. Visual pattern recogni-
based photonic devices with PCM embedded on top of them.30 Such a tion has been demonstrated using such 2-device synapses, which are
device is shown in Fig. 5(b), which consists of a Si microring resonator able to learn directly from event-based sensors.37 While these works
on the SiO2 substrate with a phase change material, Ge2Sb2Te5 (GST), focus on asymmetric STDP, which forms the basis of learning spatio-
deposited on top of the ring waveguide. The membrane potential of temporal features, PCM synapses can also exhibit symmetric STDP
based learning enabling associative learning.38 As we had discussed
such a neuron or, in other words, the amorphous thickness of the
about IF neurons, the difference in optical responsivity of PCMs can
PCM can be modulated by guiding laser pulses through Si waveguides.
also lead to emulation of synaptic behavior on Si-photonic devices.
Light gets evanescently coupled to the PCM element and changes the
The change in optical transmission in photonic synaptic devices arises
thickness of the amorphous region, thereby allowing an optical IF neu-
from the difference in the imaginary part of the refractive index of
ron based on PCM elements, as shown in Fig. 5(b) (bottom).
PCMs in their amorphous and crystalline states. The gradual increase
2. PCM as synapses
We have discussed the ability of PCM to store multiple bits in a
single cell. This multi-level behavior of PCM-based devices makes
them a promising candidate to emulate synaptic characteristics. In
addition, the large contrast in electrical properties allows for a signifi-
cantly high ON/OFF resistance ratio in PCM devices. The same two-
terminal structure described in Fig. 5(a) can be used as a synaptic
device. The programming of such a synapse is performed through the
phase transition mechanism between amorphous and crystalline
states. Amorphization (or “RESET”) is performed by an abrupt melt-
quench process, where high and short voltage pulses are applied to FIG. 6. (a) I–V characteristics of PCM devices showing SET and RESET points for
heat the device followed by rapid cooling such that the material solidi- two states. (b) Pulsing schemes for SET and RESET processes to occur, showing
fies in the amorphous state. On the other hand, crystallization is the temperatures reached due to the pulses.

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FIG. 7. (a) STDP learning in PCM synapses34 by a series of pulses of increasing (decreasing) amplitude demonstrating LTP behavior (left) similar to neuroscientific experi-

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ments19 (right). Reprinted with permission from Kuzum et al., Nano Lett. 12(5), 2179–2186 (2012). Copyright 2012 American Chemical Society. (b) STDP learning effected due
to overlap of appropriately shaped pulses.33 Reprinted with permission from Ambrogio et al., Front. Neurosci. 10, 56 (2016). Copyright 2016 Author(s), licensed under a
Creative Commons Attribution (CC BY) license.

in the optical response of PCM elements by modulating the refractive Currents from all the devices in a column get added in accordance
index can be achieved through varying the number of programming with Kirchoff’s current law to produce a column-current, which is a
pulses. This has been exploited to experimentally demonstrate unsu- result of the dot-product of the voltages and conductance. Such a dot-
pervised STDP learning in photonic synapses.39 To scale beyond single product operation can be mathematically represented as
devices, the rectangular waveguides used in this work can be replaced X
with microring resonators to perform unsupervised learning in an Ij ¼ Vi Gij ; (4)
atemporal fashion.40 i

where Vi represents the voltage on the i-th row and Gij represents the
3. PCM crossbars conductance of the element at the intersection of the i-th row and j-th
We have thus far talked about isolated PCM devices mimicking columns. This ability of parallel computing within the memory array
the neuronal and synaptic behaviors. Interestingly, these devices can using single-element memory elements capable of packing multiple
be connected in an integrated arrangement to perform in-memory bits paves the way for faster, energy-efficient, and high-storage neuro-
computations involving a series of multiply and-accumulate (MAC) morphic systems.
operations. Such operations can be broadly represented as a multipli- In addition to synaptic computations, PCM crossbars can also be
cation operation between an input vector and the synaptic weight used for on-chip learning that involves dynamic writing into individ-
matrix, which is key to many neural computations. Vector–matrix ual devices. However, parallel writing to two-terminal devices in a
multiplication (VMM) operations require multiple cycles in a standard crossbar is not feasible as the programming current might sneak to
von-Neumann computer. Interestingly, arranging PCM devices in a undesired cells, resulting in inaccurate conductance updates. To allevi-
crossbar fashion (or in more general terms, arranging resistive memo- ate the concern of sneak current paths, two-terminal PCM devices are
ries in a crossbar fashion) can engender a new, massively parallel para- usually used in conjunction with a transistor or a selector. Such mem-
digm of computing. VMM operation, which is otherwise a fairly ory cell structures are termed as “1T-1R” or “1S-1R” (shown in Fig. 8)
cumbersome operation, can be performed organically through the and are extensively used in NVM crossbar arrays. Such 1T-1R crossbar
application of Kirchoff’s laws as follows. This can be understood arrays can be seamlessly used for on-line learning schemes such as
through Fig. 8, where each PCM device encodes the synaptic strength STDP. To that effect, PCM crossbars were used as one of the first of its
in the form of its conductance. The current through each device is pro- kind to experimentally demonstrate on-chip STDP based learning,41,42
portional to the voltage applied and the conductance of the device. and simple pattern recognition tasks were conducted using the arrays.

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However, further material and device research is necessary to truly

realize the full potential of PCM-based neuromorphic accelerators.
First, the most common PCM devices are based on the chalcogenide
material group comprising elements Ge, Sb, and Te due to their high
optical contrast, repeatability, and low reflectivity. In the GeSbTe sys-
tem ranging from GeTe to Sb2 Te3 , Ge2 Sb2 Te5 has been identified as
the optimum material composition47,48 based on the trade-offs
between stability and switching speed. Despite this development,
PCMs suffer from significantly high write power due to their inherent
heat dependent switching and high latency. Second, PCM devices suf-
fer from the phenomenon of resistance drift, which is more pro-
nounced for high resistance states (HRSs). The resistance drift is the
change in the programmed value of the resistance over time after pro-
gramming is completed. This has been attributed to structural relaxa-
tions occurring shortly after programming.49–51 The effect of drift on
neural computing has been studied, and possible mitigation strategies
have been proposed.52 However, the inability to reliably operate PCM
devices at high resistance states has an impact on large-scale crossbar
operations. In light of these challenges, it is necessary to investigate
newer materials that offer more stability and lower switching speeds
for efficient and scalable neuromorphic systems based on PCM
devices.

B. Metal-oxide RRAMs and CBRAMs

An alternative class of materials to PCMs for memristive systems
are perovskite oxides such as SrTiO3,53 SrZrO3,54 Pr0:7 Ca0:3 MnO3

28 May 2024 04:41:53

(PCMO),55 and binary metal oxides such as HfOx,56 TiOx,57 and
FIG. 8. Synaptic devices arranged in a crossbar fashion along with selector devices
to perform dot-product operations. The input voltages are applied to the different TaOx,58 which exhibit resistive switching with lower programming
rows of the crossbars, and the current from each column represents the dot- voltages and durations. Such resistive switching is also observed when
P
product, Ij ¼ Vi Wij , between the input voltages and the conductance, W, of the the oxide is replaced by a conductive element. Two-terminal devices
devices. based on these materials form the base of Resistive Random Access
Memories (RRAMs). The devices with oxides in the middle are known
Although these works focused on smaller scale crossbar arrays of size as metal-oxide RRAMs, whereas the ones with conductive elements
10  10, slightly modified 2T-1R memory arrays have also been are known as the Conductive Bridge RAM (CBRAM). Although the
explored for in situ learning on a much bigger scale.43 Using two tran- internal physics of these two classes of resistive RAMs is slightly differ-
sistors enables simultaneous LIF neurons and STDP learning charac- ent, both kinds of devices have a similar behavior and hence applica-
teristics in an integrated fashion. bility. In the initial years of research, RRAM was envisaged to be a
We have discussed how unsupervised STDP learning can be non-volatile high-density memory system along with CMOS-
implemented using PCM crossbars. However, on-line learning using compatible integration. With significant development over the years,
STDP requires complex programming schemes and is difficult to scale various other applications leverage the non-volatility of RRAMs for
to larger crossbars. On the other hand, networks trained with super- power and area-efficient implementations. Among these, neuromor-
vised learning can be mapped on to much larger PCM crossbar arrays phic computing is a dominant candidate, which exploits the multi-
for inferencing. These neural networks have been experimentally dem- level capability and the analog memory behavior of RRAMs to emulate
onstrated to perform complex image recognition tasks44,45 with reason- neuro-synaptic functionalities. In this section, we will discuss how
able accuracy. Note that for these works, the supervised learning RRAMs can directly mimic neuronal and learning synaptic behaviors
schemes were implemented with software and the PCM crossbars were using single devices.
used for forward propagation both during training and inferencing.
We have discussed how PCM crossbars leverage Kirchoff’s laws to 1. Metal-oxide RRAMs and CBRAMs as neurons
perform neuro-synaptic computations in the electrical domain. In the
optical domain, however, the dot-product operation can be implemented The dynamics of a voltage driven metal-oxide RRAM device was
using wavelength-division-multiplexing (WDM).40,46 The input is first investigated by HP labs in their iconic work on TiO2 , which iden-
encoded in terms of different wavelengths, and each synaptic device tified the first device61 showing the characteristics of a memristor, pre-
modulates the input of a particular wavelength. The resulting sum is fed dicted by Chua in 1971.62 The oxide material can be conceptually split
to an array of photo-detectors to realize the dot-product operation. into two regions, a conductive region and an insulating region. The
PCM technology shows remarkable scalability and high-storage conductance of such a device can be given by its state variable, w,
density, making them amenable to efficient neuromorphic systems. which varies as

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dw
I ¼ gM ðw=LÞVðtÞ; ¼ f ðwðtÞ; VðtÞÞ: (5)
dt
Interestingly, the RRAM device can be used in an integrator circuit as
a resistor in parallel to an external capacitance, as shown in Fig. 9
(top), to emulate the LIF characteristics where the conductance of the
device can be used as an internal variable.59 When the memristor is in
its OFF state, the current through the circuit is low, and hence, it does
not output a spike. Once the memristor reaches its ON state, the
current suddenly jumps, which can be converted to analog spike. The
voltage across the memristor, in that case, obeys the dynamics of a LIF
neuron, given by Eq. (1) in Sec. II A. A similar neuron circuit has also
been explored for CBRAM devices based on Cu=Ti=Al2 O3 60 [Fig. 9 FIG. 10. (a) Basic device structure for RRAM devices consisting of a metal-oxide
layer sandwiched between two electrodes. (b) I–V characteristics showing varying
(bottom)]. Unlike PCMs, to emulate the differential equations of the SET and RESET points, leading to different resistance states.
LIF neuron, an R-C circuit configuration is used. If the leaky behavior
is not required, the internal state of the neuron or the membrane
oxide RRAM, the switching mechanisms can be categorized as (a) fila-
potential can be directly encoded in the oxygen concentration in the
mentary and (b) non-filamentary. The filamentary switching results
device. By manipulating the migration of oxygen vacancies using
due to the formation and rupture of filamentary conductive paths due
post-synaptic pulses, IF neurons can be realized by oxide-based
to thermal redox reactions between metal electrodes and the oxide
devices.63 To that effect, oxide-based devices have been used to
material. The “forming” or SET process occurs at a high electric field
design common neuronal models involving leaky behavior, such as
due to the displacement and drift of oxygen atoms from the lattice.
the Hodgkin–Huxley model and leaky IF model.64
These oxygen vacancies form localized conductive filaments, which
form the basis of filamentary conduction in RRAM devices. The form-
2. Metal-oxide RRAMs and CBRAMs as synapses ing voltage can be reduced by thinning down the oxide layer65 and
Much like PCM devices, RRAM devices can also be programmed controlling annealing temperatures during deposition.66 The RESET
to multiple intermediate states between the two extreme resistance mechanism, on the other hand, is well debated, and ionic migration
has been cited as the most probable phenomenon.67,68 A unified model

28 May 2024 04:41:53

states, which are known as the high resistance state (HRS) and the low
resistance state (LRS). This capability of behaving as an analog mem- of RESET proposes that the oxygen ions that drifted to the negative
ory makes RRAMs suitable for mimicking synaptic operations in neu- electrode causes the insulator/anode interface to act as a “oxygen reser-
ral networks. The physics behind emulating such synaptic behavior voir.”69 Oxygen ions diffuse back into the bulk due to a concentration
rests on soft di-electric breakdown in metal-oxide RRAM devices and gradient and possibly recombine with the vacancies that form the fila-
dissolution of metal ions in CBRAM devices. The device structure for ment such that material moves back to the HRS. The I–V characteris-
a metal-oxide RRAM is shown in Fig. 10(a). In the case of the metal- tics are shown in Fig. 10(b) where varying SET and RESET pulses lead
to different resistance states. In order to emulate synaptic behavior
through analog memory states in filamentary RRAMs, various pro-
gramming techniques have been explored. For example, the SET cur-
rent compliance can be used to modulate the device resistance by
determining the number of conductive filaments. On the other hand,
varying the external stimulus can control the degree of oxidation at
the electrode and oxide interface, resulting in a gradual change in resis-
tance.70 These analog states in RRAM devices can be exploited to per-
form learning on devices using various pulsing techniques. To that
effect, the time dependence of synaptic conductance change in STDP
learning can be induced by manipulating the shapes of pre-synaptic
and post-synaptic voltage waveforms,71,72 shown in Fig. 11(a). Similar
to programming PCM devices, a gradual increase or decrease in con-
ductance can be achieved using a succession of identical pulses as well,
as shown in the figure. Such a pulsing scheme, despite requiring a
more number of pulses, provides a more granular control over the
synaptic conductance,73,74 shown in Fig. 11(b). Furthermore, adding
more peripheral transistors to programming circuits can further
enable precise control over STDP. For example, a 2T/1R synapse uses
the overlapping window of two different pulses to generate program-
ming current to induce time-dependent LTP and LTD.75 In the case of
FIG. 9. (a) RRAM59 and (b) CBRAM60 neuron circuits showing the memristive filamentary RRAMs, variability in the forming process induces sto-
device RN (below) or RON=OFF (top) in parallel to a capacitor to emulate LIF chasticity in resistive switching, which can be leveraged to design sto-
characteristics. chastically learning synapses. The switching probability can be

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FIG. 11. (a) Appropriately shaped pulses representing the post-synaptic and pre-synaptic potential.72 The overlap between the two pulses in time leads to STDP learning char-
acteristics in the form of the writing current flowing through the device. Reprinted with permission from Rajendran et al., IEEE Trans. Electron Devices 60(1), 246–253 (2012).
Copyright 2013 IEEE. (b) STDP characteristics can also be emulated by passing multiple pulses, repetitively.74 Reprinted with permission from Wang et al., in 2014 IEEE
International Electron Devices Meeting (IEEE, 2014), p. 28. Copyright 2014 IEEE.

controlled by using a higher pulse amplitude. Stochastic synapses have RRAM devices showing non-filamentary switching.80 In addition to
the ability to encode information in the form of probability, thus long-term learning methods, RRAM devices with controllable volatil-
achieving significant compression over deterministic counterparts. ity can also be used to mimic frequency dependent learning, thus
Learning stochastically using binary synapses has been demonstrated enabling a transition from short-term to long-term memory.81 By con-
to achieve pattern learning.76 Unsupervised learning using multi-state trolling the frequency and amplitude of the incoming pulses, STP-LTP
memristors can also be performed probabilistically to yield robust characteristics have been achieved in WO3 based RRAM synapses.82
learning against corrupted input data.77 In general, higher amplitude pulses in quick succession are required to
Oxides of some transition metals, such as Pr0:7 Ca0:3 MnO3 transition the device from decaying weights to a more stable persistent
(PCMO), exhibit non-filamentary switching as well. This type of state. Such metastable switching dynamics of RRAM devices have
switching, on the other hand, results from several possible phenomena been used to perform spatiotemporal computation on correlated
such as charge-trapping or defect migration at the interface of metal patterns.83
and oxide, which end up modulating the electrostatic or Schottky bar- Thus far, we have discussed how metal-oxide RRAM devices can
rier. Although the switching physics in non-filamentary RRAM devi- emulate synaptic behavior. Next, we will discuss CBRAM devices,
ces is different from that in filamentary RRAMs, the fundamental which also exhibit similar switching behavior by just replacing the
behavior of using these RRAM devices as synapses is quite similar. oxide material with an electrolyte. The switching mechanism is analo-
Non-filamentary RRAMs can also be programmed using different gous to filamentary RRAM except that the filament results in a metal-
voltage pulses to exhibit multi-level synaptic behavior. Moreover, vary- lic conductive path due to electro-chemical reactions. This technology
ing pulse widths can instantiate partial SET/RESET characteristics, has garnered interest due to its fast and low-power switching. Most
which have been used to implement STDP characteristics in RRAM CBRAM devices are based on Ag electrodes where resistive switching
synapses.78,79 By encoding the conductance change using the number behavior is exhibited due to the contrast in conductivity in Ag-rich
of pulses coupled with appropriate waveform engineering can enable and Ag-poor regions. The effective conductance of such a device can
various kinds of STDP behaviors, explained in Sec. II B, of isolated be written as88

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1 to achieve energy-efficiency and high density compared to standard

Geff ¼ ; (6)
RON w þ ROFF ð1  wÞ CMOS-based computing.
Thus far, we have discussed metal-oxide RRAM crossbar arrays.
where w defines the normalized position of the end of the conducting
From a scalability point of view, CBRAM crossbars exhibit similar
region at the interface of Ag-rich and Ag-poor regions. The conduc-
trends. To that effect, high-density 32  32 crossbar arrays based on
tance of such a device can also be gradually manipulated to implement Ag–Si systems have been experimentally demonstrated, which can be
STDP using a succession of pulses.88 Here, the exponential depen- potentially used to build neuromorphic circuits. Simulation studies
dence on spike timing is implemented using time-division multiplex- based on such Ag–Si systems show significant potential of using large-
ing where the timing information is encoded in the pulse width. scale crossbars for image classification tasks.97
CBRAM based STDP learning has been implemented on-chip using Of the two classes of materials belonging to the RRAM family,
CMOS integrate-and-fire neurons.89 As with filamentary RRAM devi- metal-oxide RRAM devices have been more dominantly explored in
ces, stochastic behavior in CBRAM devices can also enable low-power the context of developing large-scale neuromorphic circuits. However,
probabilistic learning. One such implementation uses the recency of despite significant progress, RRAM-based devices suffer from signifi-
spiking as a measure of manipulating the probability of the device for cant variability, particularly in the filament formation process. On the
visual and auditory processing.90 Some CBRAM devices also exhibit other hand, non-filamentary RRAM devices, being barrier-dependent,
decay in conductance, which can be leveraged to implement short- may lead to trade-offs between stability and programming speed.
term plasticity. Ag2 S based synapses also show the properties of sen- Overall, further material research is crucial toward making RRAMs
sory memory, wherein conductance does not change for some time, viable for large-scale neuromorphic systems.
before exhibiting STP.91
C. Spintronic devices
3. Metal-oxide RRAM and CBRAM crossbars Akin to other non-volatile technologies, spin based devices were
RRAMs are two-terminal devices, similar to PCMs. Hence, like conventionally investigated as a non-volatile replacement for the exist-
PCMs, RRAM devices can also be arranged into large-scale resistive ing silicon memories. What makes spin devices particularly unique as
crossbars, shown in Fig. 8, for building neuromorphic systems. RRAM compared to other non-volatile technologies is their almost unlimited
crossbar arrays can be integrated seamlessly with CMOS circuits for endurance and fast switching speeds. It is therefore not surprising that
hybrid storage and neuromorphic systems. To that effect, a 40  40 among various non-volatile technologies, spin devices are the only

28 May 2024 04:41:53

array with CMOS peripheral circuits has been demonstrated to reliably ones that have been investigated and have shown promise as on-chip
store complex bitmap images.92 Such an experimental demonstration cache replacement.98 With respect to neuromorphic computing, it is
is a testimony to the scalability of RRAM crossbars. Leveraging this the rich device physics and spin dynamics that allow efficient mapping
scalability, studies have proposed RRAM crossbar arrays to perform in of various aspects of neurons and synapses into a single device. As we
will discuss in this section, spintronics brings in an alternate paradigm
situ learning in single layer neural networks.93,94 This scalability has
in computing by using electron spin as the memory storage variable.
been corroborated by the recent development in the process technol-
The fact that spin dynamics can be controlled by multiple physics
ogy, which have led to the realization of large crossbars of sizes up to
including current induced torques,99 domain wall motion,100 voltage
128  128 to perform image processing tasks95 and in situ learning for
based spin manipulation,101 and elastic coupling adds to the rich
multi-layer networks.45 The aforementioned works focus on using
device possibilities with spintronics and their applications to neuro-
RRAM as an analog memory. To achieve more stability, RRAM cross-
morphic computing. In this section, we would describe key representa-
bar arrays have also been used as binary weights in a scalable and par-
tive works with spin devices showing their applicability as IF-, LIF-,
allel architecture85 to emulate a large-scale XNOR network.96 Both
and stochastic neurons, and synaptic primitives.
PCM and RRAM crossbars have been extensively explored at an
array-level, and Table I provides a comparative study of different
1. Spin devices as neurons
experimental demonstrations. It should be understood that large-scale
RRAM crossbars have been primarily explored for non-spiking type As mentioned earlier, it is the rich spin dynamics that allows
networks; however, the compute primitives can be easily ported to mapping of different aspects of biological neurons using a single
realize spike-based computing. We will later discuss NVM architec- device. In fact, the simplest and the most well-known spin device—the
tures based on these RRAM crossbars, which show immense potential two-terminal Magnetic Tunnel Junction (MTJ)—can be seen as a

TABLE I. NVM Technologies.

Technology PCM45 RRAM84 RRAM85 RRAM86 RRAM87

Crossbar size 512  512 108  54 128  128 128  16 512  512
ON/OFF ratio 10 5 N/A 10 N/A
Area per operation (lm2 ) 22.12 24 0.05 31.15 N/A
Latency (ns) 80 10 13.7 0.6 9.8
Energy-efficiency (TOPS/W) 28 1.37 141 11 121.38

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stochastic-LIF neuron. MTJs are composed of two ferromagnetic (FM) effectively using the stochastic-Landau–Lifshitz–Gilbert–Slonczewski
nanomagnets sandwiching a spacer layer105 as shown in Fig. 12(a). (s-LLGS) equation,
Nanomagnets encode information in the form of the direction of  
@m^ @m^ 1
magnetization and can be engineered to stabilize in two opposite ¼ jcjðm^  HEFF Þ þ a m^ þ ðm
^  Is  mÞ
^
directions. The relative direction of the two FMs—parallel (P) vs anti- @t @t qNs
 
parallel (AP)—results in two distinct resistive states—LOW vs HIGH 1 þ a2 @ m ^
resistance. Switching the MTJ from the P to the AP state or vice versa ¼ ðm^  HEFF Þ þ aðm^ m^  HEFF Þ
c @t
can be achieved by passing a current through the MTJ, resulting in 1
transfer of torque from the incoming spins to the FMs. Interestingly, þ ðm
^  Is  mÞ
^ (7)
qNs
the dynamics of the spin under excitation from a current induced tor-
que can be looked upon as a stochastic-LIF dynamics. Mathematically, ^ is the unit vector of free layer magnetization, c is the gyro-
where m
the spin dynamics of an FM, shown in Fig. 12(b), can be expressed magnetic ratio for the electron, a is Gilbert’s damping ratio, and HEFF

28 May 2024 04:41:53

FIG. 12. (a) MTJ-based neuron102 showing the device structure (top) and leaky-integrate characteristics (bottom). Sengupta et al., Sci. Rep. 6, 30039 (2016). Copyright 2016
Author(s), licensed under a Creative Commons Attribution (CC BY) license. The magnetization of the free layer of the MTJ integrates under the influence of incoming current
pulses. (b) ME oxide-based LIF neuron103 showing the device structure (top) and LIF characteristics (bottom). Reproduced with permission from Jaiswal et al., IEEE Trans.
Electron Devices 64(4), 1818–1824 (2017). Copyright 2017 IEEE. (c) SHE-MTJ-based stochastic neuron102 showing the device structure (top) and the stochastic switching
characteristics (bottom). Reprinted with permission from Sengupta et al., Sci. Rep., 6, 30039 (2016); Copyright 2016 Author(s), licensed under a Creative Commons Attribution
(CC BY) license. (d) DWM-based IF spiking neuron104 showing the device structure (top) and integration and firing behavior (bottom) over time. For incident input spikes, the
domain wall moves toward the MTJ at the end, thus decreasing the resistance of the device. When the domain wall is at the end, the resistance reaches its lowest, enough for
the neuron fires. Reproduced with permission from Sengupta and Roy, Appl. Phys. Rev. 4(4), 041105 (2017). Copyright 2017 AIP Publishing.

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is the effective magnetic field including the shape anisotropy field, the layer, and a spin-polarized current is generated, which rotates the
external field, and thermal field. This equation bears similarities with magnetization in the adjacent MTJ such that the switching probability
the leaky-integrate-and-fire behavior of a neuron. The last term repre- increases as the magnitude of the input current is increased. This in
sents the spin transfer torque (STT) phenomenon, which causes the turn implies that the incoming current passes through a much lower
magnetization to rotate by transferring the torque generated through metal resistance and sees a constant metal resistance throughout the
the change in angular momentum of incoming electrons. switching process as opposed to current based switching in conven-
Interestingly, the first two terms can be related to the “leak” dynamics tional two-terminal MTJs. As we will see later, the existence of a low
in an LIF neuron, while the last term relates to the integrating behavior input resistance for the neuron allows easy interfacing with synaptic
of the neuron as follows. When an input current pulse or “spike” is crossbar arrays. Second, the decoupled read-write path in SOT-MTJs
applied, the magnetization starts integrating or precessing toward the allows for independent optimization of the read (inferencing) and
opposite stable magnetization state owing to the STT effect (last term). write (learning) paths. A typical SOT-MTJ and its sigmoid-like
In the absence of such a spike, the magnetization leaks back toward stochastic switching behavior are shown in Fig. 12(c). While the
the original magnetization state (Gilbert damping, second term). aforementioned behaviors depicted in Fig. 12(c) correspond to an
Furthermore, due to nano-scale size of the magnet, the switching SOT-MTJ with a high energy-barrier (10–60 kT), telegraphic
dynamics is a strong function of a stochastic thermal field, leading to SOT-MTJ with an energy-barrier as low as 1 kT has also been explored
the stochastic behavior. This thermal field can be modeled using as stochastic neurons.107
Brown’s model.106 In terms of Eq. (7), the thermal field can be incor- In addition to smaller magnets, wherein the entire magnet
porated into HEFF as a magnetic field, switches like a giant spin, longer magnets known as domain wall mag-
sffiffiffiffiffiffiffiffiffiffiffiffiffiffi nets (DWMs)108 have been used as IF neurons. DWMs consist of two
2akT oppositely directed magnetic domains separated by a domain wall [see
Hthermal ¼ f ; (8)
jcjMs V Fig. 12(d)]. Electrons flowing through the DWM continuously
exchange angular momentum with the local magnetic moment.
where f is a zero mean, unit variance Gaussian random variable, V Current induced toque affects the misaligned neighboring moments
is the volume of the free layer, T is the temperature, and k is the around the domain wall region, thus displacing the domain wall along
Boltzmann constant. A typical, stochastic-LIF behavior using MTJ the direction of current flow. The instantaneous membrane potential
is shown in Fig. 12(a).102 While the two-terminal MTJ does repre- is encoded in the position of the domain wall, which moves under the

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sent the stochastic-LIF dynamics, the very fact that the leaky and influence of post-synaptic input current. The direction of movement is
integrate behaviors are controlled by intricate device physics and determined by polarity of the incident current. The resulting magnetic
intrinsic material parameters makes it difficult to control as needed polarity can be sensed by stacking a MTJ at an extremity of the DWM,
for a large-scale circuit/system implementation. As a result, alter- and subsequent thresholding is performed when the domain wall
nate physics such as the magneto-electric switching (ME) has been reaches that extremity. The leak functionality in such a neuron can be
proposed as stochastic-LIF neurons, wherein the leaky and inte- implemented by passing a controlled current in the opposite direction.
grating behaviors can be easily controlled through device dimen- A constant current driven leak would result in increased energy con-
sions and associated circuit elements. In ME devices, the voltage sumption; as such, voltage driven DWMs based on elastic coupling
induced electric field polarization induces a magnetic field at the can be used to reduce the energy consumption.109 However, a concern
interface of the FM and ME oxide, which induces switching of the with DWM-based neuromorphic devices is that the motion of domain
FM layer. The ME oxide layer acts a capacitor, and a series resis- walls might be pinned by the presence of defects.110 To that effect,
tance can enable LIF neuronal dynamics in such a device. The ME magnetic skyrmions promise enhanced stability and has been explored
switching process is susceptible to noise like the conventional MTJ in the context of emulating neuromorphic behavior.111 In summary,
switching and hence inherently mimics the stochastic dynamics we have described multiple devices and their physics and extent of
with the LIF behavior.103 By controlling the ME oxide dimension bio-fidelity, wherein spin is used as the basic state variable. Let us
in Fig. 12(b) and/or the leaky resistive path, the LIF dynamics can now consider the applicability of spin devices as synaptic elements
be easily tweaked as per requirement. In essence, we have seen that (Fig. 13).
both current induced MTJ and voltage driven ME switching can
act as stochastic-LIF neurons. However, on one hand, current 2. Spin devices as synapses
based MTJ is difficult to control, while on the other hand, ME
switching is still in its nascent stage of investigation and needs Recall that, for PCM and RRAM devices, the existence of multi-
extensive material research for bringing the device to mainstream ple non-volatile resistance states between the two extreme HIGH and
applications. LOW resistances makes them suitable as synaptic elements. On similar
Alternatively, at the cost of reduced dynamics, three terminal lines, spin devices can be engineered to enable a continuous analog
Spin-Orbit-Torque MTJ (SOT-MTJ) has been used as a reliable sto- resistive stable state between its AP (HIGH) and P (LOW) resistances.
chastic spiking neuron while neglecting the leaky-integrate dynam- This is achieved by stacking an MTJ over DWMs. The position of the
ics.102 SOT-MTJ is reasonably mature, and also its three terminal domain wall determines the resistance state of the device. In extreme
nature brings in attractive circuit implications. First, SOT-MTJ is cases, the magnetization direction of the entire DWM aligns with that
switched by passing a bi-directional current through a heavy-metal of the pinned layer, resulting in a LOW resistance state of the device,
(HM) layer, as shown in Fig. 12(c). When a charge current enters the shown in Fig. 13. Conversely, the magnetization direction of the
HM, electrons of opposite spins get scattered to the opposite sides of DWM in the opposite direction to that of the pinned layer leads to an

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FIG. 13. STDP learning scheme in the DWM-based spin synapse112 using peripheral transistors. The exponential characteristics of STDP are realized by operating MSTDP in
the sub-threshold region and applying a linearly increasing voltage at its gate. MSTDP is activated when a pre-neuron spikes, and the programming current (shown in blue)
through the transistor is injected into the HM layer (grey) when a post-neuron spikes. Reproduced with permission from Sengupta et al., Phys. Rev. Appl. 6(6), 064003 (2016).
Copyright 2017 American Physical Society.

Anti-Parallel (AP) configuration, which defines the HIGH resistance controlled by varying the amplitude or duration of the programming
state of the device. With respect to the position of the domain wall, x, pulse as shown in Fig. 12(c). This benefit of controlled stochasticity
the resistance of the device changes as leads to energy-efficient learning in binary synapses implemented
x Lx using MTJs.115,116 An advantage of on-chip stochastic learning is that
Geq ¼ GP þ GAP þ GDW : (9) the operating currents are lower than the critical current for switching,
L L

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thus ensuring low-power operations. Such multiple stochastic MTJs
Here, GP (GAP) is the conductance of the MTJ when the domain can be represented as a single synapse to achieve an analog weight
wall is at the extreme right (left) of the DWM. GDW is the conductance spectrum.117 These proposals of stochastic synapses based on MTJs
of the domain wall region, and L is the length of the DWM. Owing to have shown applications of pattern recognition tasks on a handwritten
low write currents, synaptic elements based on DWM devices113 can digit dataset.
achieve orders of magnitude lower energy consumption over corre- Finally, the precessional switching in the free FM layer in the
sponding realizations in other non-volatile technologies. Similar to MTJ inherently represents a dependence of switching on the frequency
spin neurons, inducing switching using the Spin-Hall effect (SHE) on programming inputs. On the incidence of a pulse, the magnetiza-
through a heavy-metal below the MTJ, the programming current can tion of the free FM layer moves toward the opposite stable state.
be further reduced. DWM-based devices have been explored to mimic However, if the pulse is removed before the switching is completed, it
the behavior of multi-level synapses in works such as Ref. 114. With a reverts back to its original stable state. These characteristics can be
few extra transistors, STDP learning can be enabled by a relatively sim- used to represent volatile synaptic learning in the form of STP-LTP
ple programming scheme as shown in Fig. 13.112 This scheme lever- dynamics.118
ages the exponential characteristics of transistors in the sub-threshold
regime. A linearly increasing voltage is applied to the gate of the tran- 3. Spintronic crossbars
sistor, MSTDP , which is activated when the pre-neuron spikes. When
the post-neuron fires, an appropriate programming current passes Synapses based on 2-terminal MTJs can be arranged in a crossbar
through the HM layer, which now depends exponentially to the timing fashion, similar to other memristive technologies. The currents flowing
difference due to the sub-threshold operation. It is worth noting that through the MTJs of each column get added in the crossbar and repre-
although the DWM provides a way to encode multiple stable states in sent the weighted sum of the inputs. Unlike the two-terminal devices,
spin devices, the key drawback of such devices is the extremely limited SHE based MTJs, being 3-terminal devices, have decoupled read and
HIGH–LOW resistance range. The resistance range for spin devices is write paths. As a result, they require a modified crossbar arrangement.
much lower than their PCM and RRAM counterparts. Encoding mul- One major advantage of spin neurons is that current through the syn-
tiple states within the constrained resistance range raised functionality aptic crossbars can be directly fed to the current controlled spin neu-
concerns considering variability. rons. As discussed earlier, spin devices suffer from very low ON/OFF
Alternatively, non-domain wall devices such as two-terminal resistance ratios compared to other technologies. Hence, despite exper-
MTJs of three terminal SHE based MTJs can be used as synapses. In imental demonstration of isolated synaptic spin devices,119 large-scale
the absence of DWMs, MTJs can only encode binary information, i.e., crossbar-level neuromorphic implementations have been mostly lim-
two resistance states. In such a scenario, stochasticity can play an inter- ited to simulation studies. Such simulation studies have been based on
esting role in realizing multi-level behavior by probabilistic switching. reasonable ON/OFF ratios considering a predictive roadmap.120 To
In spin devices, such thermally induced stochasticity can be effectively that effect, multi-level DWM-based synapses have been arranged in a

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crossbar fashion to emulate large-scale neural networks, both in a fully as a viable option to emulate synaptic behavior for large-scale neuro-
connected form114 and as convolutional networks.121 In addition to morphic systems.
inferencing frameworks based on spin synapses, STDP based learn-
ing112 has also been explored at an array-level, as shown in Fig. 14, to
perform feature recognition and image classification tasks. As dis- D. Ferroelectric FETs
cussed earlier, MTJ-based binary synapses require stochasticity for
effective learning. They can leverage the inherent stochasticity in the Similar to the phase change and ferromagnetic materials, another
network, and a population of such synapses can perform on-line learn- member of functional material family is ferroelectric (FE) materials. In
ing, which not only achieves energy-efficiency but also enables addition to being electrically insulating, ferroelectric materials exhibit
extremely compressed networks.116 non-zero spontaneous polarization (P), even in the absence of an
These simulation-based designs and results show significant applied electric field (E). By applying an external electric field (more
promise for spin based neuromorphic systems. However, several tech- than a threshold value, called the coercive field), the polarization direc-
nological challenges need to be overcome to realize large-scale systems tion can be reversed. Such an electric field driven polarization switch-
with spin. As alluded to earlier, the ON/OFF ratio between the two ing behavior of FE is highly non-linear (compared to di-electric
extreme resistance states is governed by the TMR of the MTJ, which materials) and exhibits non-volatile hysteretic characteristics. Due to
has been experimentally demonstrated to reach 600% (Ref. 122), lead- the inherent non-volatile nature, FE based capacitors have been histor-
ing to an ON/OFF ratio of 7. This is significantly lower than other ically investigated for non-volatile memory elements. However, in fer-
competitive technologies and poses a limitation on the range of synap- roelectric field effect transistors (FEFETs), an FE layer is integrated at
tic weight representation at an array level. Second, MTJs can only rep- the gate stack of a standard transistor and thus offers all the benefits of
resent binary information. For multi-bit representation, it is necessary CMOS technology in addition to several unique features offered by
to use domain wall devices or multiple binary MTJs at the cost of FE. The FE layer electrostatically couples the underlying transistor.
area density. However, since synapses in the neural networks usually Due to such coupling, FEFETs offer non-volatile memory states by vir-
encode information in an analog fashion, the lack of multi-state tue of polarization retention of FE. Beside CMOS process compatibil-
representation in MTJs can potentially limit the area-efficiency of ity, one of the most appealing features of FEFET based memory is the
non-volatile spin devices for neuromorphic applications. The lack of ability of voltage based READ/WRITE operation, which is unlike the
multi-bit precision can be alleviated with architectural design facets current based READ/WRITE schemes in other non-volatile memory

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such as “bit-slicing.” This involves multiple crossbars with binary devi- devices (spin based memory and phase change memory). Due to the
ces to represent multiple bits of storage. Despite such provisions, non-volatility and the intricate polarization switching dynamics of FE,
improved sensing circuits along with material exploration to achieve FEFETs have garnered immense interest in recent times as a potential
higher TMR is necessary to truly realize the potential of spin devices candidate for neuron-mimicking and multi-bit synaptic devices. In

FIG. 14. A crossbar arrangement of spintronic synapses connected between pre-neurons A and B and post-neurons C and D, showing peripheral circuits for enabling STDP
learning.112 Reproduced with permission from Sengupta et al., Phys. Rev. Appl. 6(6), 064003 (2016). Copyright 2017 American Physical Society.

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this section, we will briefly discuss the recent progress in FEFET based theoretically predicted in Ref. 126. Such spontaneous polarization
neuro-mimetic devices. relaxation has been attributed as the cause of domain wall instabil-
ity,126 and such a process has recently been experimentally demon-
1. FEFETs as neurons strated in an HfxZr1-xO2 (HZO) thin-film.127 By harnessing such a
quasi-leaky behavior along with the accumulative and abrupt polariza-
The dynamics in a ferroelectric FET device can be used to mimic tion switching in FE, a quasi-leaky-integration-fire (QLIF) type FEFET
the functionality of a biological neuron. In a scaled FEFET, if identical based neuron can offer an intrinsic homeostatic plasticity. Network
sub-threshold pulses (“sub-coercive” in the context of FE) are applied level simulations utilizing the QLIF neuron showed a 2.3 reduction
at the gate terminal [shown in Fig. 15(a) (leftmost)], the device in the firing rate compared to the traditional LIF neuron while main-
remains in the OFF state (since the sub-threshold pulses are insuffi- taining the accuracy of 84%–85% across varying network sizes.127
cient for polarization switching). However, after a certain number of Such an energy-efficient spiking neuron can potentially enable ultra-
pulses are received, the FEFET abruptly switches to the highly conduc- low-power data processing in energy constrained environments.
tive state [Fig. 15(a) (rightmost)]. Such phenomena can be understood
as the initial nucleation of nano-domains followed by an abrupt polari- 2. FEFETs as synapses
zation reversal of the entire grain connecting the source and drain of
FEFETs. Before the critical threshold is reached, the nucleated nano- We have seen how the switching behavior of a FEFET can mimic
domains are not capable of inducing a significant charge inversion in the behavior of a biological neuron. The switching behavior also pro-
the channel, leading to the absence of the conduction path (OFF state). duces bi-stability in FEFETs, which makes them particularly suitable
The accumulative P-switching presented in Ref. 125 appears to be for synaptic operations. The bi-stable nature of spontaneous polariza-
invariant with respect to the time difference between the consecutive tion of ferroelectric materials causes voltage induced polarization
excitation pulses, and therefore, the device acts as an integrator. switching characteristics to be intrinsically hysteretic. The device struc-
Moreover, the firing dynamics of such FEFET based neurons can be ture of a FEFET based synapse is similar to a neuronal device as shown
tuned by modulating the amplitude and duration of the voltage in Fig. 15(b) (leftmost). The FE electrostatically couples with the
pulse.123,125 However, to implement the leaky behavior, a proposed underlying transistor. Due to such coupling, FEFETs offer non-volatile
option is to modulate the depolarization field or insertion of a negative memory states by virtue of polarization retention of the ferroelectric
inhibit voltage in the intervals between consecutive excitation pulses. (FE) material. In a mono-domain FE (where the FE area is comparable
Apart from this externally emulated leaky process, an intrinsically to the domain size), two stable polarization states (P and þP) can be

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leaky (or spontaneous polarization relaxation) process has been achieved in the FE layer, which, in turn, yield two different channel

FIG. 15. (a) FEFET device structure showing an integrated ferroelectric layer in the gate stack of the transistor (leftmost). A series of pulses can be applied to emulate the inte-
grating behavior of neurons and the eventual firing through abrupt switching of the device.123 (b) A FEFET synaptic device (leftmost) showing programming pulsing schemes
generating the STDP learning curve based on the change in charge stored in the device.124

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conductances for the underlying transistor. Such states can also be 3. FEFET crossbars
referred to as “low VT” (corresponds to þP) and “high VT” (corre-
sponds to P) states.128 Even though the polarization at the lattice FEFETs utilize the electric field driven writing scheme, and such
level (microscopic polarization) can have two values (þP or P), in a a feature is unique when compared with the Spin-, PCM-, and
macroscopic scenario, multi-domain nature of FE films (with the area RRAM-based synaptic devices. Therefore, FEFET based synaptic devi-
significantly higher than the domain size), multiple levels of polariza- ces are potential candidates for low-power realization of neuro-
tion can be achieved. Furthermore, the polycrystalline nature of the FE mimetic hardware. These transistor-like devices can also be arranged
film offers a distribution in the polarization switching voltages (coer- in a crossbar fashion to perform dot-product operations. Simulation
cive voltage) and time (nucleation time) in different grains. As a result, studies using the population of neuronal and synaptic devices have
a voltage pulse dependent polarization tuning can be obtained such been studied for image classification tasks.130–132 We discussed earlier
that the overall polarization of the FE film can be gradually switched. that the multi-state conductance of FEFETs originates from the multi-
This corresponds to a gradual tuning of channel conductivity (or VT) domain behavior of the FE layer at the gate stack. However, such
in FEFETs and can be readily exploited to mimic multi-level synap- multi-domain features of FE (domain size and patterns) are highly
ses,124,129 in a manner similar to what has already been reported for dependent on the physical properties of FE (i.e., thickness, grain size,
PCM and RRAMs. As noted above, FEFETs are highly CMOS com- etc.).126 As a consequence, in a FEFET synaptic array, the multi-state
patible, which makes their applications as neuro-mimetic devices quite behavior of FEFETs may suffer from the variability of the FE layer
appealing. along with the variation induced by underline transistors. Therefore,
Recently, several FEFET based analog synaptic devices have been large-scale implementation of the synaptic array with identical FEFET
experimentally demonstrated,124,130,131 where the conductance poten- characteristics will be challenging, which can potentially be overcome
tiation and depression via a gradual VT tuning were obtained by apply- with high quality fabrication of FE films and variation aware designs.
ing a voltage pulse at the gate terminal. However, in the case of Despite the benefits offered by FEFETs, the technology is still at its
identical voltage pulses, the observed potentiation and depression nascent stage in the context of neuro-mimetic devices, and crossbar-
characteristics are highly non-linear and asymmetric with respect to level implementations will be potentially explored in the future.
the number of pulses. To overcome such non-ideal effects, different
non-identical pulsing schemes were proposed in Ref. 130, which utilize
a gradual modulation of pulse magnitude or pulse time. Such non- E. Floating gate devices

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identical pulsing schemes demonstrate a significant improvement in Most of the aforementioned non-volatile technologies are based
potentiation/depression linearity and symmetry. However, if pulses on non-Si platforms requiring effective integration and CMOS com-
are not identical throughout the programming process, an additional patibility. Si-based non-volatile memories, such as Flash memory, use
step of accessing the weight value is needed every time, and an update floating gate devices134 to store data. These devices have seen consider-
takes place so that an appropriate pulse can be applied. This leads to able commercial use in universal serial bus (USB) flash drives and solid
design overheads and may reduce the training efficiency. To overcome state drives. Owing to their non-volatility, floating gate devices were
such detrimental effects, an optimum weight update scheme using one of the first devices explored for emulating synaptic behavior in
identical pulses for improved linearity and asymmetry was experimen- neuromorphic systems. Furthermore, these devices are even more
tally demonstrated in a FE-Germanium-NanoWire-FET (FE- promising because of their standard process technology. In this sub-
GNWFET).131 Based on the experimentally extracted parameters of section, we will discuss how neuro-synaptic functionalities can be
the FE-GNWFET, simulation of the multi-layer perceptron neural net- effectively mimicked using floating gate devices.
work over 1  106 MNIST images predicts an on-line learning accu-
racy of 88%. It should be noted that the underlying physics in
potentiation/depression linearity and symmetry enhancement in FE- 1. Floating gate devices as neurons
GNWFETs over the conventional FEFET is still unclear. Hence, there
is a timely demand for further theoretical understanding that can A floating gate (FG) transistor has the same structure as a con-
enable aggressive device level engineering for achieving higher linearity ventional MOSFET, except for an additional electrode between the
and symmetry in FEFET based synaptic devices. gate and the substrate, called the floating gate, shown in Fig. 16(a).
FEFET synapses can also be used to enable learning with the The non-volatility is induced by the charge stored on the floating gate
STDP based update scheme, which can also be achieved.124 In order to of the transistor. As the charge stored in the floating gate increases, the
utilize the single FEFET as a two-terminal synapse connected to the threshold voltage of the transistor decreases, as shown in Fig. 16(b).
pre- and the post-neuron, a resistor is connected between the gate and This charge storage dynamics can also be leveraged to emulate inte-
drain [Fig. 15(b) (leftmost)] terminals. Thus, the pre-spike is applied grating behavior in a leaky IF neuron.133 Such a LIF neuron circuit is
to the gate and resistor, while the source and bulk are controlled by shown in Fig. 17. Block A shows the integrating circuit where a charge
the post-neuron. With this synaptic scheme and the spiking waveform is injected into the floating gate by the pre-synaptic current. This mod-
depicted in Fig. 15(b) (middle), the relative spike timing between the ulates the voltage at the floating gate, VFG, which accounts for the inte-
pre- and the post-neurons can be converted into voltage-drop across gration. Over time, the charge decays, introducing a leaky behavior.
the FEFET. The closer the spiking in the time domain, the larger the The leak factor is dependent on the tunneling barrier thickness. The
voltage-drop, which induces a larger conductivity change in the balance between charge injection and charge ejection determines the
FEFET. The corresponding STDP pattern showing the potentiation neuron operation. The rest of the circuit performs the thresholding
and depression is depicted in Fig. 15(b) (rightmost). and resetting operation as required by a LIF neuron.

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(MLC) are possible. Such multi-level storage capability of FG transis-

tors have been heavily used in flash memory technologies.137,138 This
analog memory characteristics along with excellent stability and reli-
ability, especially for multi-level states, make FG devices promising for
emulating analog synaptic behavior. In fact, the earliest proposals of
on-chip synapses with computing and learning abilities were based on
FG transistors.139–141

3. Floating gate crossbars

FIG. 16. (a) Basic floating gate transistor structure showing the control gate and
the floating gate separated by a blocking oxide layer. (b) Increasing charge in the Owing to the integrability with CMOS processes, floating gate
blocking oxide layer lowers the threshold voltage, VT, of the transistor causing transistors have been used to implement large-scale arrays of program-
higher current at a particular voltage. mable synapses to perform synaptic computations between popula-
tions of neurons. The exponential dependence of injection and
tunneling currents on the gate and tunneling voltages can be further
2. Floating gate devices as synapses used to perform STDP based weight update in such “single transistor”
Unlike the neuronal behavior, which depends on the charge synapses.142,143
injection/ejection dynamics of the floating gate, the synaptic behavior FG transistors overcome most of the major challenges encoun-
depends primarily on charge storage and its ability to modulate the tered by the previously discussed non-volatile technologies including
conductance of the device. The charge storage mechanism is governed reliability and stability. Moreover, the retention time can also be mod-
by two phenomena known as the Fowler–Nordheim (FN) tunnel- ulated by varying the tunneling barrier of the gate oxide. However, this
ing135,136 and hot-electron injection (HEI). HEI requires a high posi- comes with a trade-off that FG transistors require high voltage for
tive voltage across the gate and the source such that electrons have writing and reading. Moreover, unlike the high-density storage offered
enough kinetic energy to cross the insulating barrier between the float- by PCM and RRAM technologies, FG transistors consume a larger
ing gate and the channel. Charge gets trapped in the floating gate and area. The power-hungriness and area inefficiency have thus propelled
remains intact even after removal of voltage due to the excellent insu- research toward more energy and area-efficient solutions offered by
beyond-CMOS technologies.

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lating abilities of SiO2 . The other mechanism involves FN tunneling,
which stores and removes charge from the floating gate in a reversible
manner. A sufficiently high positive voltage between the source and F. NVM architecture
control gate causes the electrons to tunnel into the floating gate, So far, we have discussed how NVMs, owing to their intrinsic
whereas an equivalent voltage of opposite polarity removes the charge. physics, can be exploited as neural and synaptic primitives. A compari-
Charge in the floating gate increases the threshold voltage of the tran- son table of the aforementioned NVM technologies is shown in
sistor, thus enabling two stable states in the FG transistor, based on the Fig. 18. Additionally, we have seen that, at a circuit level, the dense
presence and absence of charge. This can be used to emulate binary crossbar arrangement and associated analog computations present a
synapses. In addition, due to the analog nature of charge, by manipu- promising way forward with respect to in-memory computing.
lating the amount of charge stored in the floating gate, multi-level cells Advantageously, beyond devices and circuits, even at an architectural

FIG. 17. Floating gate leaky-integrate-and-fire neuron133 showing (a) the integrating circuit, (b) and (c) feedback amplifier circuits for thresholding operation, and (d) reset
circuit.133

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FIG. 18. Table showing a comparison of different beyond-CMOS NVM technologies and some representative works on demonstrations and design of neuronal and synaptic
elements in a spiking neural network. Note that neurons and synapses can also be designed using non-volatile floating gate transistors (discussed in Sec. III E). However, in
this table, we focus on beyond-CMOS materials due to their non-standard material stack.

(or system) level, NVMs and crossbars provide interesting opportuni- in the right level of memory hierarchy, before it can be processed, lead
ties for energy- and area-efficiency. NVMs provide a radical departure to the memory-wall bottleneck. Since the storage density of NVMs is
from the state-of-the-art von-Neumann machines due to the following much larger [a single static random access memory (SRAM) cell stor-
two factors: (1) NVM based crossbars are being looked upon by the ing one bit of data consumes 150F2 area compared to an NVM that
research community as the holy grail for enabling in-memory mas- can take 4F2 space storing multiple bits], they lend themselves easily
sively parallel dot-product operations, and (2) the high storage density for distributed spatial architectures. This implies that an NVM based
offered by NVMs allows construction of spatial neuromorphic archi- neuromorphic chip can have a crossbar array that stores a subset of
tectures, leading to higher levels of energy, area, and latency improve- the network weights, and such multiple crossbars can be arranged in a
ments.144–147 Spatial architectures differ from conventional processors tiled manner, wherein weights are almost readily available within each
in the sense that the latter rely heavily on various levels of memory tile for processing.
hierarchy, and data have to be shuffled back and forth between various Keeping in view the aforementioned discussion, a generic NVM
memory sub-systems over long distances (between on-chip and off- based distributed spatial architecture is shown in Fig. 19, enable map-
chip memory). As such, the energy and time spent in getting the data ping of neural network applications entirely using on-chip NVM. The

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counterparts, for example, the CMOS based large-scale neuromorphic

chip presented in Refs. 154 and 155, and (2) investigation and estab-
lishment of the limits of crossbar based neuromorphic systems for on-
chip training keeping in mind the constrained writability of NVM
technologies.
IV. PROSPECTS
A. Stochasticity—Opportunities and challenges
We have discussed about the promises of NVM technology for
emulating neuro-synaptic behavior using single devices. These devices
can have inherent variability embedded into their intrinsic physics,
which can lead to stochastic characteristics. This is a major advantage
from CMOS-based implementations where extra circuitry is required
to generate stochastic behavior. Stochastic devices derive inspiration
from the inherent stochasticity in biological synapses. Such synaptic
uncertainty can be used in both learning and inferencing157 in spiking
neural networks. This is especially crucial for binary or ternary synap-
FIG. 19. A representative neuromorphic architecture based on NVM crossbars as ses where arbitrary weight update may result in overwriting previously
basic compute engines.
learned features. Using stochasticity in binary synapses can vastly
improve its feature recognition capabilities. This can be done in both a
various computing cores with their crossbar arrays are interconnected
spatial manner158 where a number of synapses are randomly chosen
through network-on-chip (NOC). A distinct characteristic of SNN
for weight update or a temporal manner116 where learning in a proba-
architecture is event-drivenness. SNNs communicate through spikes,
bilistic manner can follow the footsteps of the STDP based synaptic
i.e., binary information transfer between neurons. As such, for on-chip
weight update algorithm. Stochastic STDP thus enables feature recog-
NOCs, spike-addresses are communicated between various compute
nition with extremely low-precision synaptic efficacy, resulting in
cores rather than energy expensive transfer of actual data.144
compressed networks,152 which has the potential to achieve significant
Furthermore, only those units are active, which have received a spike,
energy efficiency when implemented on hardware.151 Stochastic learn-

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and others remain idle, resulting in added energy-efficiency. Note that
ing is particularly helpful for low-precision synapses because its adds
both spike-based on-chip communication and event-drivenness are
an analog probabilistic dimension, thus ensuring less degradation in
direct consequences of SNN based data processing. Distributed archi-
accuracy in low-precision networks. For higher-precision networks
tectures based on NVM technologies have been explored heavily to
where the classification accuracy does not degrade, stochasticity does
build special-purpose accelerators for both machine learning work-
not make a significant difference.
loads such as convolutional neural networks (CNNs), multi-layer per-
In addition to stochastic learning, we have also discussed how
ceptrons (MLPs), and long short term memories (LSTMs),145–148 as
stochastic devices can be used to mimic the functionality of cortical
well as SNNs.144,149 These works have demonstrated significant
neurons. In PCM devices, stochasticity has been explored in integrate-
improvements over CMOS-based general purpose systems such as
and-fire neurons29 where multiple reset operations lead to different
central processing units (CPU), graphics processing units (GPU), or
initial glass states. Although such stochastic IF characteristics can be
application specific integrated circuits (ASICs),150 which highlight the
exploited for robust computing, the overhead for achieving control
potential of neuromorphic computing based on NVM devices.
over such stochasticity remains to be seen. On the other hand, in spin
Until now, we have talked about inference-only accelerators that
devices, stochastic neurons with sigmoidal characteristics are heavily
require fixed-point arithmetic, which NVM crossbars are well suited
tunable. These kinds of neurons have been explored both using high
for. In addition, on-chip training based on unsupervised learning has
energy-barrier (10–60 kT) magnets102 and low barrier magnets (1
been explored at a primitive level using low-precision devices;151,152
kT).107 While the resultant sigmoidal behavior looks similar, a 1 kT
however, training accelerators for large-scale tasks, which use such
magnet loses its non-volatility and is more susceptible to variations,
primitives, have not been demonstrated yet. Moreover, supervised
leading to more complex peripheral circuit design.156 This results in
learning, on the other hand, requires floating-point arithmetic due to
the peripheral energy dominating the total energy consumption of
small magnitude of weight updates, which is difficult to be captured by
such devices, which, interestingly, often makes them less energy-
fixed-point representation. Architectures, which support training, thus
efficient than high barrier counterparts (Fig. 20).
face a significant challenge of incorporating such small updates to
NVM crossbars. This problem is accentuated especially with limited
endurance and high write latency of some NVM technologies, such as B. Challenges of NVM crossbars
PCMs and RRAMs. Writing into crossbars in parallel using pulse We have also discussed about the promises of NVM technology
width encoding schemes has been proposed although the scalability of for emulating neuro-synaptic behavior using single devices. We have
such a technique still needs to be investigated.153 Based on the discus- shown how these devices can be connected in an integrated crossbar
sion in this section, two important developments that are yet to be network to perform large-scale neural computing. Although the prom-
seen from the neuromorphic community with respect to architectures ise of enabling parallel in-memory computations using crossbar arrays
based on NVMs are (1) experimental demonstration of large-scale is attractive from the energy- and area-efficiency perspective, many
inference-only NVM crossbar systems that can rival their CMOS non-ideal devices and circuit behaviors limit their wide scale

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involving Kirchoff’s laws under certain assumptions,162 or even data-

dependent fitting.163 Considering the minimal effect of IR-drops along
the metal lines, equations of a crossbar under the effect of peripheral
resistances can be simplified as
P
Vi;ni Gij
Ij ¼ P ; (10)
1 þ Rsink Gij

1=Rs
Vi;ni ¼ Vi P : (11)
1
1=Rs þ
Rji þ Rsink
Here, Ij is the current of the j-th column, Vi is the input voltage to the
i-th row of the crossbar, (Rij ¼ 1=Gij Þ is the resistance/conductance of
the synaptic element connecting the i-th row with the j-th column,
Vi;ni is the degraded input voltage due to the effect of peripheral resis-
tances, Rs is the effective source resistance, and Rsink is the effective
sink resistance. These resistances in relation to a crossbar are shown in
FIG. 20. A comparison in energy consumption for stochastic spin neurons for various
energy-barrier heights.156 Reproduced with permission from Liyanagedera et al., Phys. Fig. 21. This modeling gives us an intuition about the behavior of
Rev. Appl. 8(6), 064017 (2017). Copyright 2017 American Physical Society. crossbars, which can help preserve the computation accuracy. For
example, lower synaptic resistances result in higher currents, which
results in larger parasitic drops across the metal line. On the other
applicability. These include the variability in RRAM states, which can
hand, higher operating resistances might lead to low sensing margins,
detrimentally affect the verity of analog computations in synaptic ele-
necessitating the need for expensive peripheral circuitry. The presence
ments. This is primarily due to the uncontrolled nature of the variabil-
of sneak paths in synaptic crossbars can also adversely affect the pro-
ity in filamentary RRAM or CBRAM devices.159 PCM devices on the
gramming process, thus harming the performance of on-chip learning
other hand, in spite of being less prone to variability, suffer from resis-
systems.
tance drifting due to structural relaxations after the melt-quench

28 May 2024 04:41:53

In addition to non-ideal elements in NVM crossbars, the design
amorphization of the material.160 Resistance drifting primarily affects
of peripheral components such as Digital-to-Analog Converters
high resistance states in PCMs and hence adversely impacts the perfor-
mance of neural networks especially for ex situ trained networks.52
Carefully manipulating the highest resistance state of operation using
partial resetting pulses can potentially reduce the impact of resistance
drift.52 Spintronic devices are more robust with respect to variability
and endurance challenges as compared to RRAM and PCM technolo-
gies owing to their stable and controlled switching. However, practical
devices suffer from low contrast in conductivity between the stable
extremities. The low ON–OFF ratio severely affects the mapping of
synaptic weights when implemented in neural networks and is the
major technical roadblock for synaptic implementations using spin
devices. Additionally, all non-volatile devices have energy and latency
expensive write operations in comparison to conventional CMOS
memories. This in turn limits the energy-efficiency of performing on-
chip synaptic plasticity that requires frequent write operations.
Apart from device variations and limitations, building large-scale
crossbars using non-volatile synaptic devices is a major hurdle toward
realizing the goal of neuromorphic accelerators. Crossbar sizes are
severely limited by various factors such as peripheral resistances, para-
sitic drops, and sneak paths. Figure 21 shows a schematic of a realistic
crossbar with source, sink, and line resistances and peripherals. When
training is performed on-chip taking into account the non-ideal cross-
bar behavior, such inaccuracies in crossbar computations can be miti-
gated to a large extent. However, for neuromorphic systems designed
as inference-only engines, it is necessary to perform effective modeling
FIG. 21. A realistic crossbar system showing the peripheral circuits including digi-
of the crossbar array, which can potentially account for the non-
tal-to-analog converters (DACs) at the input to the crossbar and analog-to-digital
idealities during off-line training and take corrective measures for converters (ADCs) at the output. Crossbars can possess non-ideal resistance ele-
accurate crossbar computations. Such modeling can either involve rig- ments such as the source resistance ðRsource ), line resistance (Rline), and sink resis-
orous graph-based techniques for linear circuits,161 simple equations tance (Rsink).

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(DACs) and Analog-to-Digital Converters (ADCs) is essential toward however, does not recover the performance of an ideal neural network
building large-scale neuromorphic systems. As shown in Fig. 21, without any non-idealities. The presence of non-idealities in the for-
DACs are used to convert bit-streamed data to voltages, whereas the ward path of a neural network may require a modified backpropaga-
ADCs convert back the analog voltage outputs from a sample-and- tion algorithm to closely resemble the ideal neural network.162 For
hold array into digital bits. These converters are especially necessary as unsupervised learning algorithms such as STDP, the impact of non-
the sizes of neural network models are much higher than the size of a idealities may be significantly lower due to the ease of enabling on-line
single crossbar. As a result, multiple crossbars are required to represent learning, which can automatically account for the errors. In addition
the entire neural network, which necessitates digital communication to static non-idealities in the crossbars, the effect of non-linearity and
between the outputs of individual crossbars. As the crossbar size asymmetry of programming characteristics of NVM devices can also
increases, the precision requirements for ADCs become higher, lead- be detrimental to the performance of the network. Reliable mitigation
ing to enormous power consumption, which can potentially reduce due to such programming errors can be performed by novel pulsing
the benefits in terms of energy consumption that NVM crossbars schemes.166,167 These pulsing schemes involve modulation of pulse-
inherently offer. However, the inherent robustness of neural networks widths based on the current conductance state, which help restore
toward computation errors may allow us to design approximate linearity.
peripheral circuitry based on ADCs with lower precision require- Beyond re-training, other static compensation techniques can
ments. Moreover, efficient mapping of crossbars and introducing pro- also be used to recover some system level inaccuracies. For example,
grammability in peripheral precision requirements can potentially the limited ON/OFF ratio and precision of NVM synaptic devices can
preserve the benefits offered by NVM technology. In light of these result in computational errors, which can be taken care of by effective
challenges such as device variations, non-ideal resistances, sneak paths, mapping of weight matrices to synaptic conductance.168 Static trans-
and peripheral design, careful design space exploration is required to formations of weight matrices have been explored to alleviate circuit-
identify optimum resistances for operation and crossbar sizes of syn- level non-idealities.169 This methodology performs gradient search to
aptic elements along with efficient device-circuit-algorithm co-design identify weight matrices with non-idealities that resemble ideal weight
for exploring effective mitigation techniques. matrices. Most of the compensation techniques adopted to account for
computation inaccuracies in NVM crossbars address very specific
C. Mitigating crossbar non-idealities problems. A more complete and holistic analysis, modeling, and miti-
NVM provides a massively parallel mode of computations using gation of crossbar non-idealities are necessary to completely under-

28 May 2024 04:41:53

crossbars. However, as we have discussed previously, analog comput- stand the impact and explore appropriate solutions.
ing is error-prone due to the presence of circuit-level non-idealities
and device variations. Various mitigation techniques have been D. Multi-memristive synapses
explored to address these computing inaccuracies. Although some of Multi-memristive synapses are examples, wherein device limita-
these techniques have been demonstrated for artificial neural net- tions have been countered by the use of circuit techniques, albeit at
works, the methodologies still hold true for spike-based neuromorphic additional area overhead. Figure 22 depicts two illustrations, which use
computing. The most commonly used methodology to recover the multiple NVM devices to represent one synaptic weight. In Fig. 22(a),
performance of neural networks due to crossbar-level computing two separate PCM devices were used to implement LTD and LTP sep-
errors is to re-train the network using software models of resistive arately. Incrementing the PCM device corresponding to LTP increased
crossbars. The re-training approach involves updating the weights of the neuronal input, whereas incrementing the device corresponding to
the network based on information of non-idealities in crossbars. This LTP decreased the neuronal input. By this scheme, the authors in Ref.
has been explored for both stuck-at-faults164 and device variations165 35 were able to simply the peripheral write circuits since only incre-
where it has been observed that re-training the network with aware- ments in device resistances were required for representing both LTP
ness about the defect or variation distribution can minimize the effects and LTD plasticity. Note that conventionally using one single device
of these non-idealities on classification performance. Re-training, would have required write circuits for both incrementing and

FIG. 22. (a) Two separate NVM devices used for LTP and LTD, and the resulting output of the synapse is fed to the neuron. (b) Multiple NVM devices connected in parallel to
increase the current range of the synapse. (c) Through the use of an arbitrator, any one of the devices is selected for learning.

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decrementing the PCM device resistance, and given the complex computing still remain a major technical roadblock. In contrast, one
nature of waveforms required to write into PCM devices, this would could use digital in-memory computing for implementing on-chip
have led to additional area overhead. In yet another work, more than robust SNN networks. These implementations can use various digital
one memristors were connected in parallel [Fig. 22(b)]170 to allow the techniques, as in use of read only memory (ROM) embedded RAM in
increased current range of the overall synaptic cell. For learning, an NVM arrays174 or peripheral circuits based on in-memory digital
arbitration scheme was used to select one memristor and program in computations.175 Interestingly, these works do not require heavy re-
accordance with the learning scheme as shown in Fig. 22(c). With ref- engineering of the devices themselves. As such, they can easily benefit
erence to these examples, we believe that such schemes, wherein device from the recent technological and manufacturing advancements
level constraints can be mitigated through the use of clever circuit driven by industry for commercialization of various non-volatile tech-
techniques, can be a key enabler for NVMs in neuromorphic comput- nologies as memory solutions.
ing without solely relying on better material stack and manufacturing Furthermore, in a large neural network, NVM can be used as sig-
processes for improved device characteristics. nificance driven in-memory compute accelerators. For example, layers
of the neural network, which are less susceptible to noise, can be accel-
E. Beyond neuro-synaptic devices and STDP erated using analog in-memory computing, while those layers that
need more accurate computations can be mapped on NVM arrays
As would be apparent by now, the state-of-the-art in neuromor-
rendering digital in-memory computing. Thus, fine-grained heteroge-
phic hardware using non-volatile devices can be characterized in two
neous in-memory computing (both digital and analog) can be used in
broad categories of works—(1) those that tend to mimic the LIF unison to achieve both lower energy consumption and higher applica-
dynamics of a neuron using device characteristics and (2) others that tion accuracy. It is also well known that NVMs that store data digitally
are geared toward synaptic functionalities and associated learning are easier to program as opposed to analog storage, which requires
through STDP in shallow SNNs. On the other hand, the state-of-the- multiple “read-verify” cycles. Thus, on-chip learning, which requires
art on the algorithmic side of neuromorphic computing has taken a frequent weight updates, is more amenable to digital or heterogeneous
step forward beyond LIF dynamics and STDP learning. We have dis- (digital þ analog) computing arrays as opposed to analog storage of
cussed briefly about how supervised learning such as gradient descent data. Additionally, bit errors induced due to digital computing can be
can also be used for spike-based systems. Previously, supervised learn- easily rectified using error correction codes. Thereby, resorting to digi-
ing has been performed in the artificial neural networks (ANN) tal processing for critical or error susceptible computation could help
domain, and trained networks have been converted to SNNs.27 widen the design space for use of NVMs as SNN accelerators.

28 May 2024 04:41:53

Although this method has been scaled to complex image recognition
datasets such as ImageNet, one particular drawback of this scheme is
G. Physical integrability of NVM technology with
high inference latency. To circumvent that, researchers have explored
CMOS
learning schemes, which incorporate such gradient descent algorithms
in the spiking domain itself.28,171,172 Moreover, combining unsuper- There are several works on experimental demonstration of in-
vised and supervised learning techniques have also been widely memory computing primitives based on non-volatile memories, espe-
explored.173 This kind of hybrid learning technique has shown better cially RRAM and PCM technologies.45,84,95 NVM devices in most
scalability (to deeper networks) and improved accuracy. state-of-art RRAM and PCM crossbars are accompanied by a CMOS
We believe that it is important for the hardware community to selector device (like a transistor). Such a 1T-1R crossbar configuration
move beyond mimicking neurons and synapses on shallow SNNs and resolves sneak paths during read and write operations.176 Crossbars
find ways and means of executing more dynamic learning schemes on based on NVM technologies such as RRAM,177 PCM,178 and
hardware for deeper spiking networks. Such improved learning Spintronics179 are fully compatible with the CMOS back end of the
schemes would inevitably require complex compute operations, which line (BEOL) integration process. There are some issues that need to be
could be beyond the intrinsic device characteristics of non-volatile considered. For example, PCM is fabricated in crystalline form, as
devices. As such, there is a need to explore systems, wherein computa- BEOL integration involves high temperature processes. Although there
tions can be segregated between non-volatile sub-arrays and CMOS have been large-scale demonstrations on RRAM and PCM crossbars
based compute engines, allowing the overall system to benefit both with CMOS peripherals, work on CMOS integration of spintronic
from parallelism offered by NVMs and the compute complexity devices has been limited to small scale Boolean logic circuits.179 It is to
offered by CMOS engines. This would also be a key enabler in building be noted that the limited use of spin devices for the crossbar structure
end-to-end deployable neuromorphic systems (wherein a spike-based is a result of the low ON–OFF ratio for spintronic devices and not
sensor is directly interfaced to a neuromorphic processor) that can because of compatibility issues pertaining to integration of spin devices
cater to real life task as in ultra-low energy IoT systems. Such IoT sys- with CMOS technology. In fact, the current advancement in process
tems not only are important from a research perspective but can also integration for spin based devices with CMOS technology has led to
provide a possible commercial niche-application for neuromorphic recent widespread interest for commercial use of spin based read-write
processors based on non-volatile technologies. memories.180 FEFETs, on the other hand, follow the standard Front
End of Line (FEOL) CMOS process. Thus, all the NVM technologies
being explored can be physically integrated with CMOS.
F. NVM for digital in-memory computing
Most of the current works involving neuromorphic computing V. CONCLUSION
and emerging devices have concentrated on analog-mixed-signal com- The growing complexity of deep learning models and the
puting. However, the inherent approximations associated with analog humongous power consumption of standard von-Neumann

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 Applied Physics Reviews REVIEW scitation.org/journal/are

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ACKNOWLEDGMENTS 24
B. Rueckauer, I.-A. Lungu, Y. Hu, M. Pfeiffer, and S.-C. Liu, “Conversion of
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Multidisciplinary University Research Initiative, the U.S. Army Andreopoulos, D. J. Berg, J. L. McKinstry, T. Melano, D. R. Barch, C. di
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