Proceedings of the Sixth International Conference on Trends in Electronics and Informatics (ICOEI 2022)

IEEE Xplore Part Number: CFP22J32-ART; ISBN: 978-1-6654-8328-5

VLSI Implementation of crypto coprocessor using

AES and LFSR
Anantha Krishnan A.K Devika K N Ramesh Bhakthavatchalu
Department of ECE Department of ECE Department of ECE
Amrita Vishwa Vidyapeetham Amrita Vishwa Vidyapeetham Amrita Vishwa Vidyapeetham
Amritapuri, India Amritapuri, India Amritapuri, India
[email protected] [email protected] [email protected]
2022 6th International Conference on Trends in Electronics and Informatics (ICOEI) | 978-1-6654-8328-5/22/$31.00 ©2022 IEEE | DOI: 10.1109/ICOEI53556.2022.9777145

Abstract—Data security has been a major concern as that of hardware implementation of these algorithms require much
the faster processing of data. As the capability of data processing effort and more number of build elements. Currently we can
is being evolved, the attacks on these devices for the extraction of see many cryptograhpic implementations that are mostly done
data also have been increasing day by day. The purpose of this
work is to optimise the security of current crypto coprocessors on software than in hardware. It is because the developments
with the help of Linear Feedback Shift Register (LFSR) as key and updates are linearly happening in the software domain.
generator. The integration of LFSR with Advanced Encryption Hardware tools are having high price compared to software.
Standard (AES) will enhance the security when considering hash Most of the developed VLSI cad tools can only be availed
algorithms that have hardcoded keys which can be extracted or purchased by researchers and high end industries. For
through back tracing. By making the key input of the AES
random, the device will be less prone to hardware attacks and individual projects and in most of the small colleges, it is
back tracing the algorithm to extract the key value and thereby not possible to buy those tools. The applications increasing
the data will be difficult. Here AES with 128-bit block size and demand for computation power, and the power reduction
key size is integrated with the 128-bit LFSR. All the simulations requirements for portable devices, force us to consider that
and implementations are done on Xilinx-Vivado. general-purpose processors are no longer an efficient solution
Index Terms—LFSR, AES, Cryptography, Hardware attacks.
for mobile systems. Most of the applications are consuming
very high power and they requires highly improved com-
I. I NTRODUCTION
putational requirements, therefore general purpose processors
Data security is always a major concern in the progressing are not effective for portable devices . Such approaches are
word. As the world is looking for more innovative ways to [13]Application-Specific Integrated Circuits (ASIC) technol-
make the data processing and transfer more faster, the security ogy and [6]Field Programmable Gate Arrays (FPGAs).
of the data that is transferred also need to be considered. In this project the implementation of a cryptographically
Recent [3]hardware attacks reported shows the significance of secure co-processor with the help of an 128-bit linear feedback
implementing a secure architecture that provides better secu- shift register is taken into account. Advanced Encryption Stan-
rity to the devices. [2]Cryptographic algorithms are considered dard (AES), and [19]Federal Information Processing Standard
to be the most secure and effective algorithms till date since (FIPS), are approved by NIST and are widely used for the
most of the algorithms are hard to break or back trace. The protection of electronic data world wide . It is also referenced
world is currently focusing more into crypto currencies, block as Rijndael (its original name), is a specification for the
chain etc. The possibilities of crypto algorithms are not to encryption of electronic data established by the U.S. National
be bounded only for software security but also for hardware Institute of Standards and Technology (NIST) in 2001. AES
architectures. Implementation of crypto algorithms apart from algorithm can be programmed in software and hardware at
the limits of compatibility with the hardware modeling must the same time. The encrypted output from the AES process
be considered. requires our data input and the key for the encryption. The
Implementing a secure hardware architecture using cryptog- key will always same when considering an AES module, so it
raphy is a gradual process. As the new attacks are reported the will be vulnerable to hardware attacks if the key is somehow
world tends to look for more safer and secure algorithms. As obtained by the attacker. The [21]LFSR is used to provide
far as we know, most of the cryptographic algorithms are not the key input to the AES and that makes the input key also
easy to back trace. The security provided by [1]AES, [19]Se- random. The AES and LFSR used here are both with 128-bit
cure Hash Algorithm (SHA), [7]Message Digest Method 5 security. 128-bit LFSR will be more complex architecture but
(MD5)etc. have implemented or been into discussion over provides better security to the crypto engine.
the past two decades. The most updated versions of these The paper is ordered in the following strcuture: Section II
algorithms not tend to be fragile or able to back trace it describes the architecture of AES and its working. Section
and its been into study always. The area overhead by these III discusses about LFSR and the implementation of 128 Bit
crypto engines have to be taken into account because each modular LFSR. Methodology adopted for implementation of

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 Proceedings of the Sixth International Conference on Trends in Electronics and Informatics (ICOEI 2022)
IEEE Xplore Part Number: CFP22J32-ART; ISBN: 978-1-6654-8328-5

• Rounds
a) SubBytes
b) ShiftRows
c) MixColumns
d) AddRoundKey

• Last Round
a) SubBytes
b) ShiftRows
c) AddRoundKey

Fig. 1. Structural Block Diagram

AES and LFSR combined is discussed in section IV. Section V

emphasizes about the simulation and implementation results of
128 Bit AES and 128 Bit LFSR in Xilinx and RTL compiler.
Section VI conclusion, further research and future scope of
the project.

II. T HE AES A LGORITHM

Advanced encryption standard is the most widely used
cryptographic algorithm that is compatible with hardware and
software at the same time. The data input given is encrypted
by AES using a key provided by the user or the developer.
AES is a block cipher that transform the 128-bit input data
by [19]permutations and combinations using a key of size
128-bit, 192-bit or 256-bit secret key. The National Institute
Fig. 2. Working of AES
of standards and Technology have announced in Jan 1997 to
initiate the development of new AES cipher. In October 2001
they have announced that the new [7]Rijindal algorithm have 1) SUB-BYTES: This non linear byte substitution operation
won the competition between different algorithms developed will operate on each byte independently. The [20]substitution
and proposed that the new Advanced Encryption Standard table or the [4]sbox is invertible and is constructed by the
will be Rijindal algorithm. From there on-wards AES is being combination of two transformations:
widely used as the base of cryptography in terms of hardware i) Multiplicative inverse is taken in the Rijndael’s finite field.
and software. It have replaced the existing [7]DES and Triple ii) Then doing the affline transformations.
DES to provide better security benefits and secure architecture. 2) SHIFT ROW STEP: In this step each columns are
AES is being widely used in the commercial market for shifting row wise. The initial row is not getting shifted, it
different kind of data transactions. It pawed the way to make will be same as previous. The 2nd row is left shifted to left
the cryptographic algorithm widespread in the market. There one time, the 3rd row two times and the 4th row three times.
are several hardware architecture using the benefits of AES 3) MIX COLUMNS: By treating each column as a
to perform better encryption with the help of other hash four-term polynomial the mix column operation makes the
algorithms like SHA, MD5 etc. transformation on the state column by column. The columns
are considered as polynomials over [5]GF 28 and multiplied
A. Steps In AES Algorithm modulo x4 + 1 with a fixed polynomial a(x), given by
• Key Expansions : The input key is expanded for the
number of rounds plus one for the [6]addround key step a(x) = {03}x3 + {01}x2 + {01}x + {02} (1)
in each stage. The keys are obtained by from the cipher
key by the Rijndael’s key schedule. 4) KEY EXPANSION: The initial key we provide as the
input to AES will not be sufficient for the proceeding 10
• Initial Round rounds . The key ex-pander algorithm follows an [10]Key
a) AddRoundKey : Each byte of the state is combined expander (or generator) operation basically follows five steps
with the round key block using bitwise XOR. to generate a unique key for each round in AES. Every key
produced will be same width as that of input key. The input

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 Proceedings of the Sixth International Conference on Trends in Electronics and Informatics (ICOEI 2022)
IEEE Xplore Part Number: CFP22J32-ART; ISBN: 978-1-6654-8328-5

to key expander circuit will be the key from the LFSR here, ments. The [16]polynomial used for the implementation here
thereby making the keys also unpredictable by the attacker. is,
5) ADDROUNDKEY: The main function of the Add X 128 + X 127 + X 126 + X 121 + 1 (2)
Round Key is to associate the keys generated by the key
expander step to XOR with the output got from the mixcolumn
step. The initial 128 bit key is expanded by the key expansion
method to increase the key size for multiple rounds. The round
key length will be matching with the block size length, that
is 16 bytes.
The output of addround key is got by XORing of Key
expansion output and the Mix columns output. The output
given above is encrypted output of output1. The output of the
Add Round Key step is given as input to the next round to
process. The feedback creates a loop and runs for 10 rounds Fig. 3. Modular LFSR
of this stage.

III. L INEAR F EEDBACK S HIFT R EGISTER - LFSR IV. M ETHODOLOGY

Cryptographic algorithms tend to consume more area
A linear feedback shift register is a type of shift register
and power when implemented in hardware. So we need to
whose input is a function of the previous state. A set of points
consider an optimised implementation with lesser power
or taps are selected in the register chain and the [11]feedback
and better security. Coprocesssor itself tend to consume
is provided through these taps. The taps are [4]XORed back
more power and area, so implementing them for better
to the register chain, by providing a feedback mechanism.
security considering area and power is a challenge. Here the
In case of a standard shift register, the register bits are not
randomness of the the key is taken into consideration because
provided with the input tap. The looping of repetitive sequence
of the several back tracing attacks reported over the past
of random numbers is due to this feedback provided. The taps
decade. So implementing an LFSR to provide key to AES
can be made selective as the number of values occurring can
makes it less prone to [19]backtracing and obtaining the key
be increased or decreased before the [17]pattern repeats. The
to decrypt the data. Here an architecture with the integration
structuring of LSFR can be done in two ways, one to may
of LFSR and AES is implemented using verilog. Modular
and many to one structure. For shortest clock to clock delay
architecture tend to give lesser delay to the LFSR output
path, the implementation is in one-to-many structure rather
thereby making the coprocessor more faster.The difference
than many to one structure. The structure of LFSR is designed
between standard and modular LFSR is only in the position
in cost effective and structured manner for the combination
of XOR gates in the feedback.In case of standard LFSR it
with the AES structure and for reducing the hardware area.
can have more than one XOR gate between the two adjacent
Taps are the bits in LFSR that influences the sequence flip flops, but for modular LFSR it can have maximum
generation. A [21]maximum-length LFSR means it will gen- one LFSR in between two adjacent flip flops. This makes
erate all the possible [15]pattern before it start repeating the modular LFSR more faster than standard LFSR. We can
same. There must not have a case such that all the bit turns reduce the higher area overhead also by preferring modular
to be zero and if that happens shift register wont generate LFSR. Compatability of LFSR with the pipeline architecture
any further sequence or it will remain in the same state. The of AES also provides better speed for the system, thereby the
period of random numbers generated by this system is (2n- performance of the coprocessor can be increased.
1), where n denotes the count of shift registers used for the Implementation of AES algorithm has been the initial priority
implementation. for the crypto engine. Further discussions and observations
helped to conclude the optimization features that can be
A. 128 Bit LFSR
selected to maintain the speed when the system is to be
Implementation of 128 bit [12]modular LFSR is taken into enhanced with higher security. Integrating LFSR with an 128
account here. The key size of AES is 128 bit so that the bit crypto algorithm considering optimized area and speed is
integration of LFSR to AES will be more convenient here. a challenge since LFSR bit size must also have to be 128 bits.
Modular LFSR is having lesser delay compared to the standard [22]Modular LFSR tend to have lesser delay thereby speed
LFSR and 128 bit security makes it more random and less can be enhanced upto a limit. Pipeline architecture is selected
prone to more hardware attacks. Here the aim is to increase for implementing AES to increase the speed and compatibility
the [9]randomness of AES key, so the higher bit size of LFSR with working of LFSR. AES algorithm became the winner
and the modular architecture provides better security and faster of the competition for the best cipher algorithm because
performance. Since the AES is of 128 bit size integrating of its simplicity and the reliable performance provided.
the modules with be convenient without introducing structures As the encryption throughput need to be maximum in the
to increase compatibility thereby increasing the area require- implementation, pipeline architecture is more preferred. We

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 Proceedings of the Sixth International Conference on Trends in Electronics and Informatics (ICOEI 2022)
IEEE Xplore Part Number: CFP22J32-ART; ISBN: 978-1-6654-8328-5

need to care about power and area overhead more when it The capability of cyptographic algorithms to be combined
comes to a coprocessor. Here we are trying to implement with different external structures providing better security
a cost effective integrated structure that is having higher and less vulnerability to hardware attacks is analysed here.
security and lesser area overhead. Implementing a crypto algorithm in hardware considering the
Integration of crypto algorithms with external structures is speed and area is always a challenge. Optimized architecture
an efficient way increasing the randomness of the system. have to be considered when incorporating a higer bit LFSR
But the challenge in area and power have to be considered structure with a cryptographic algorithm
when it comes to implementation. As the area constraints The implementation of AES with 128 bit key is done in
are still a challenge, the exceptional performance and lesser the initial stages. Here pipeline architecture is used for the
cost makes designers to think about these crypto algorithms. implementation, so this will tend to give better speed. As we
AES is an encryption standard and when it comes to can see in Fig. 4, a manually given key and a hard coded
pipeline architecture, it will consume more area than normal data input is used for the verification of the various stages
implementations. In case of LFSR, for generating n number of AES encryption. The architecture is designed to consume
of random bits, we need to use n clock cycles and it is a lesser area when we consider cryptographic algorithms that
not a good characteristic to be used in the cryptographic will mostly tend to consume higher area. In the next stage,
implementations. But we have implemented a method in implementation of modular LFSR is done to decrease the
which shifting of n bits can be done in one clock cycle. delay provided by LFSR. AS we know LFSR tend have
It will make the system faster and more convenient to be more delay and it is not desirable for a coprocessor. Modular
used implementations were speed is important as that of LFSR provide lesser delay compared to standard or common
security.The cost of implementation will be very less for LFSR implementation. Apart from the conventional LFSR
cryptographic algorithms and modular LFSR is also cost implementations that uses one-to-many structure, here many-
effective and having lesser area overhead compared to to-one structure is proposed because of the shortest clock to
standard LFSR’s. The seed value provided to the LFSR have clock delay path. In Table 1, the performance of AES with
to be hard coded initially and if its needed, it can also be and without LFSR is shown clearly. The increase in area after
randomised using external structures in the future. [23]As we the integration seems to be not much significant compared to
are selecting a primitive polynomial for implementing LFSR that of the initial AES structure. So the structure will not have
it can generate maximum number of random patterns. Hence higher area requirements with this security enhancement.
the key value of AES will be random for each encryption. In the schematic Fig.6 we can see that the LFSR is provided
We can see a lot of hardware attacks in the past decade that with seed value of 128 bits and the random bits are produced
makes hardware security also into consideration. Most of according to the tap values given. The random output of the
the current systems in terms of software and hardware are LFSR is fed to the input of AES directly. In the initial stage
updating their security measures using updated cryptographic of AES, the data input provided is converted to 128-bit size
algorithms. If the hackers are able to get the crptographic then it is XORed with the key value provided by the LFSR.
key through back tracing or power analysis based attacks, As shown in the schematic the output of the 1st stage of AES
the whole connected systems will be under threat. So it is is fed to the next set of rounds which includes sub-bytes, shift
very important to make the cryptographic algorithms with rows, mix columns and add round key. These steps are looped
higher levels of security. Here we are considering the effects for next 9 rounds and that will make the data highly encrypted.
of algorithm back tracing. Apart from AES being a simple The process works in a pipeline manner so that the processing
crypto algorithm, it’s providing better encryption with lesser of encrypted data will be more faster than the conventional
area overhead and power requirements than other algorithms. implementation. The encrypted output after the 9 rounds of
So if we can protect the algorithm from existing back tracing operation is fed to the last step which does not include the
threats to get the cryptographic key, it will make a safer mixcolumns steps. The data will be heavily encrypted by these
structure that can be implemented with lower cost and efforts. processes and finally can be transmitted through the channel.
LSFR is always the best approach to generate random patterns From the waveform Fig.7 we can observe the random keys
based on a single seed value and the polynomial provided. produced and the output of AES obtained using each key
produced. The pipeline architecture helps to maintain the speed
even after the structures are integrated. Obtaining the key value
V. R ESULTS AND A NALYSIS each time by breaking the randomness of an LFSR will not
Analysis of AES with 128-bit LFSR as the key generator be an easy task, so the transmitted data tend to have more
input shows greater security enhancements as expected. Cryp- security than in the case were key input is hard coded.
tographic algorithms mostly face the problem of lesser pro- Integration of complex structures is always a challenge
cessing speed, but the implementation of AES using pipeline when considering area and power optimisation. Here LFSR
method helps in increase in the processing speed. The imple- with 128 bit security have to be structured to align with the
mentation of 128-bit LFSR provides better security because speed and area requirements of a crypto algorithm and must
of the higher bit length and at the same time it makes it more work with optimum area and power requirements. 128 bit
capable to be combined with the 128 bit key structure of AES. LFSR have higher security in terms of bit strength and modular

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 Proceedings of the Sixth International Conference on Trends in Electronics and Informatics (ICOEI 2022)
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Fig. 4. AES Schematic

Fig. 7. Waveform of Integrated Structure

VI. C ONCLUSION
Implementation of AES with LFSR as key generator shows
to be more secure than the hard coded key provided by the
user. Improvement in performance offered by the pipelined
Fig. 5. 128 Bit LFSR Schematic architecture of AES makes it more reliable to be used in the
coprocessor architecture. When considering the area usage,
most of the cryptographic implementations took higher area.
architecture provides lesser delay. So the overall performance Here it took comparatively lesser area and provides higher
of the crypto engine higher in terms of security and speed.The performance. In terms of security the architecture gives a huge
simulations and implementations are done using Xilinx Vivado impact in the realization of more cost-effective devices with
software. Fig. 7 shows the resulting waveform of AES with secure architecture.
LFSR output as key. The pipeline architecture of AES helps The results provided by the combination of LFSR with AES
in the faster encryption of data. The encrypted output of AES paves the way to merge different kinds of key generators with
using each LFSR key can be observed here. From the Table the existing cryptographic hash functions to make a secure
1 we can seen that the integration of these two structures did and lesser area architecture. As we have focused more on the
not affect the speed of the system to a greater extend. coprocessor crypto engine, it can be implemented inside the
processor architecture itself, thereby reducing the more area
overhead. The recent development in the are of PUF’s can also
be taken into account. PUF’s can be used as a seed generator
TABLE I
P ERFORMANCE OF I NTEGRATED S TRUCTURE to the LFSR thereby we can reduce the further vulnerabilities
of back tracing and hacking the input seed value.
Performance Parameters Without LFSR With LFSR
No of LUT’s 9379 9409
No of flip flops 35 128 R EFERENCES
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