2-1

Digital Component

Computer System Architecture Chap. 2 Digital Components

 2-2

 Plastic Quad Flat Package (PQFP)  Ceramic Leadless Chip Carrier (LCC)

 TO Packages (Transistor single Outline)

Computer System Architecture Chap. 2 Digital Components

 2-3
2-2 Decoder/Encoder

 Decoder
 A combinational circuit that converts binary information from the n
coded inputs to a maximum of 2n unique outputs
 n-to-m line decoder = n x m decoder
 n inputs, m outputs
 If the n-bit coded information has unused bit combinations, the decoder
may have less than 2n outputs Fig. 2-1 3-to-8 Decoder
 m  2n A2
D0
A1
 3-to-8 Decoder A0 D1
 Logic Diagram : Fig. 2-1 Enable Inputs Outputs
E A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D2
 Truth Table : Tab. 2-1 0 x x x 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1 D3
 Commercial decoders 1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0 D4
include one or more 1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0 D5
Enable Input(E) 1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0 D6
1 1 1 1 1 0 0 0 0 0 0 0

Tab. 2-1 Truth table for 3-to-8 Decoder D7

Enable(E)

Computer System Architecture Chap. 2 Digital Components

 2-4

* Active Low Output

 NAND Gate Decoder * Fig. 2-1 3-to-8 Decoder Active High Output

 Constructed with NAND instead of AND gates D0

 Logic Diagram/Truth Table : Fig. 2-2
A0 D1
Enable Input Output
E A1 A0 D3 D2 D1 D0
0 x x 0 0 0 0 D2
Fig. 2-2 2-to-4 Decoder with NAND gates 1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0 A1 D3
1 1 1 1 0 0 0 Enable(E)
 Decoder Expansion (a) Truth Table
 3 X 8 Decoder constructed with two 2 X 4 Decoder (b) Logic Diagram

 Constructed decoder : Fig. 2-3 1

a1
2
0 b1
5

Encoder D0
2
2 6

A2 a2 b2

 2 X4
Decoder
Tab. 2-2 Truth Table for A1
3
a3
E
b3
7

D1
 Inverse Operation of a decoder Encoder A0
b4
8

D2
D3
 2n input, n output Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
1
a1
2
0 b1
5

1
2
a2 2 b2
6

0 0 0 0 0 0 0 1 0 0 0 D4
 Truth Table : Tab. 2-2 0 0 0 0 0 0 1 0 0 0 1 3
a3
E
2 X4
Decoder
b3
7

D5
 3 OR Gates Implementation 0 0 0 0 0 1 0 0 0 1 0 8
b4

D6
0 0 0 0 1 0 0 0 0 1 1
» A0 = D1 + D3 + D5 + D7 0 0 0 1 0 0 0 0 1 0 0
Fig. 2-3 A 3-to-8 Decoder
D7
0 0 1 0 0 0 0 0 1 0 1
» A1 = D2 + D3 + D6 + D7 constructed with two
0 1 0 0 0 0 0 0 1 1 0
» A2 = D4 + D5 + D6 + D7 1 0 0 0 0 0 0 0 1 1 1 with 2-to-4 Decoder
Computer System Architecture Chap. 2 Digital Components
 2-5
2-3 Multiplexers

 Multiplexer(Mux)
 A combinational circuit that receives binary information from one of 2n
input data lines and directs it to a single output line
 A 2n -to 1 multiplexer has 2n input data lines and I0
n input selection lines(Data Selector) I1
Y
 4-to-1 multiplexer Diagram : Fig. 2-4
I2
 4-to-1 multiplexer Function Table : Tab. 2-3
Select Output I3
S1 S0 Y
Tab. 2-3 Function Table for 0 0 I0
0 1 I1
4-to-1 line Multiplexter S0
1 0 I2
1 1 I3 S1
 Quadruple 2-to-1 Multiplexer Fig. 2-4 4-to-1 Line Multiplexer
Enable
 Quadruple 2-to-1 Multiplexer : Fig. 2-5 Select

A0 Y0
Select Output A1 Quadruple Y1
E S Y A2 2x1 Y2
Fig. 2-5 Quadruple 2-to-1 A3 Mux Y3
0 0 All 0's B0
line Multiplexter
1 0 A B1
B2
1 1 B B3
(a) Function Table (b) Block Diagram

Computer System Architecture Chap. 2 Digital Components

 2-6
2-4 Registers

 Register
 A group of flip-flops with each flip-flop capable of storing one bit of
information
 An n-bit register has a group of n flip-flops and is capable of storing any
binary information of n bits
 The simplest register consists only of flip-flops, with no external gate :
Fig. 2-6
 A clock input C will load all four inputs in parallel
 The clock must be inhibited if the content of the register must be left SET
D Q
unchanged I0 A0
Clock Q

Register with Parallel Load

CLR

 SET
D Q
I1
 A 4-bit register with a load control input : Fig. 2-7 A1
CLR
Q

 The clock inputs receive clock pulses at all times I2 D

SET
Q
A2
 The buffer gate in the clock input will increase “fan-out” CLR
Q

 Load Input I3 SET

D Q
A3
 1 : Four input transfer Clear CLR
Q

 0 : Input inhibited, Feedback from output to input(no change) Fig. 2-6 4-bit register

Computer System Architecture Chap. 2 Digital Components

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2-5 Shift Registers

 Shift Register
 A register capable of shifting its binary D Q

information in one or both directions

Q
 The logical configuration of a shift
register consists of a chain of flip-flops
in cascade D Q

 The simplest possible shift register uses

Q
only flip-flops : Fig. 2-8
 The serial input determines what goes
into the leftmost position during the shift D Q

 The serial output is taken from the

Q
output of the rightmost flip-flop

D Q

Fig. 2-8 4-bit shift register Fig. 2-7 4-bit register with parallel load

Computer System Architecture Chap. 2 Digital Components

 2-8

 Bidirectional Shift Register with Parallel Load

 A register capable of shifting in one direction only is called a
unidirectional shift register
 A register that can shift in both directions is called a bidirectional shift
register
 The most general shift register has all the
capabilities listed below:
 An input clock pulse to synchronize all operations
 A shift-right /left (serial output/input)
 A parallel load, n parallel output lines
 The register unchanged even though clock pulses
are applied continuously
 4-bit bidirectional shift register with parallel load :
Fig. 2-9
Mode Operation
 4 X 1 Mux = 4 , D F/F = 4 S1 S0
0 0 No chage
0 1 Shift right(down)
Tab. 2-4 Function Table for Register 1 0 shift left(up)
of Fig. 2-9 1 1 Parallel load Fig. 2-9 Bidirectional shift register

Computer System Architecture Chap. 2 Digital Components

 2-9
2-6 Binary Counter

 Counter
 A register goes through a predetermined sequence of state(Upon the
application of input pulses)
 Used for counting the number of occurrences of an event and useful for
generating timing signals to control the sequence of operations in
digital computers
 An n-bit binary counter is a register of n flip-flop(count from 0 to 2n -1)
 4 bit Synchronous Binary Counter
J KQ(t+1)
0 0 Q(t)  A counter circuit will usually employ F/F with complementing
1 1 Q(t)'
capabilities(T and J-K F/F)
 4 bit Synchronous Binary Counter :
Fig. 2-10
Carry = Q3• Q2’
Count
Enable
J Q J Q J Q J Q
Q0 Q0’ Q1 Q1’ Q2 Q2’ Q3
K Q K Q K Q K Q

Clock

Fig. 2-10 4-bit Synchronous binary counter

Computer System Architecture Chap. 2 Digital Components

 2-10

 Binary Counter with Parallel Load

 Counters employed in digital
systems(CPU Register) require a J Q

parallel load capability for transferring K Q

an initial binary number prior to the
count operation
J Q
 4-bit binary counter with Clear, Parallel
Load, and Increment(Counter) : K Q

Fig. 2-11
 Function Table : Tab. 2-5 J Q

J K Q(t+1)  Clear : 1 K=X, J=0 Clear(Q=0) K Q

0 0 Q(t)
0 1 0 (Clear, Load=X)
1 0 1
1 1 Q(t)'

J Q
 Load : 1 I=1 J=1, K=0
(Clear=0) I=0 J=0, K=1 K Q

 Increment : 1 J=K=1(Toggle)
(Clear, Load=0) Fig. 2-11 4-bit binary counter with parallel load

Computer System Architecture Chap. 2 Digital Components

 2-11
2-7 Memory Unit

 Memory Unit
 A collection of storage cells together with associated circuits needed to
transfer information in and out of storage
 The memory stores binary information in groups of bits called words
 Word
 A group of binary information that is processed in one simultaneous
operation
 Byte
 A group of eight bits (nibble : four bits)

 The number of address line = k

 Address(Identification number) : 0, 1, 2, 3, … up to 2k -1
 The selection of specific word inside memory : k bit binary address
Dec Hex
 1 Kilo= 210, 1 Mega= 220, 1 Giga= 230
0 0000
16
 16 bit address line : 2 = 64 K 1 0001
2 0010
 Solid State Memory(IC Memory) 3 0011 Memory
. . Word
 RAM(Volatile Memory)
. .
 ROM(Non-volatile Memory) . .
65535 FFFF

Computer System Architecture Chap. 2 Digital Components

 2-12

 Random Access Memory

 The memory cells can be accessed for information transfer from any
desired random location
 Communication between a memory and its environment is achieved
through data input and output lines, address selection lines, and
control lines : Fig. 2-12
 The two operations that a random-access memory can perform are the
write and read operations
 Memory Write
1) Apply the binary address data input lines n
2) Apply the data bits
3) Activate the write input
address lines k Memory Unit
 Memory Read Read 2k words
n bits per word
1) Apply the binary address Write
2) Activate the read input
data output lines n
» The content of the selected word does
not change after reading
Fig. 2-12 Block diagram of RAM
 NV-RAM : battery back-up CMOS RAM

Computer System Architecture Chap. 2 Digital Components

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 Read-Only Memory
 A memory unit that performs the read operation only; it does not have a
write capability address input lines k

 ROM comes with special internal electronic fuses that can be m x n ROM
“programmed” for a specific configuration (m = 2k)

 m x n ROM : Fig. 2-13 data input lines n

 k address input lines to select one of 2k = m words of memory, and n output

lines(n bits word)
 ROM is classified as a combinational circuit, because the outputs are
a function of only the present inputs(address lines)
 There is no need for providing storage capabilities as in a RAM
 ROM is also employed in the design of control units for digital
computers
 A Control Unit that utilizes a ROM to store binary control information is called
a micro-programmed control
 Types of ROMs
 UVEPROM(Chip level erase), EEPROM(Byte level erase), Flash ROM(Page
or block level erase), OTPROM, Mask ROM

Computer System Architecture Chap. 2 Digital Components