Digital Electronics Laboratory Second Year Computer Engineering (2019 Pattern)

A Laboratory Manual for

Digital Electronics
Laboratory

(210249)
Semester– III
(Computer Engineering)
Bachelor Degree in Engineering

SAVITRIBAI PHULE PUNE UNIVERSITY,

GANESHKHIND

PIMPRI CHINCHWAD EDUCATION TRUST’S

PIMPRI CHINCHWAD COLLEGE OF ENGINEERING AND RESEARCH
RAVET, PUNE – 412101
Digital Electronics Laboratory Second Year Computer Engineering (2019 Pattern)

PIMPRI CHINCHWAD EDUCATION TRUST’S

PIMPRI CHINCHWAD COLLEGE OF ENGINEERING AND RESEARCH
RAVET, PUNE – 412101

INDEX
Sr. No. Assignment Statement Page No.
Group A
1 To Realize Full Adder/Subtractor using: 1
a) Basic Gates and
b) Universal Gates.
2 Design and implement Code Converters-Binary to Gray and BCD to 5
Excess-3.
3 Design and Realization of BCD Adder using 4-bit Binary Adder (IC 10
7483).
4 Realization of Boolean Expression for suitable combination logic 12
using MUX 74151/74153, DMUX 74154/74138.
5 To Verify the truth table of two bit comparators using logic gates. 17
6 Design and Implement Parity Generator and checker using EX-OR. 22
Group B
7 Design and Realization: Flip Flop conversion. 26
8 Design of 2 bit and 3 bit Ripple Counter using MS JK flip-flop. 30
9 Design of Synchronous 3 bit Up and Down Counter using MSJK Flip 33
Flop / D Flip Flop.
10 Realization of Mod - N counter using (Decade Counter IC 7490). 36
11 Design and implement Sequence generator (for Prime Number/odd 39
and even) using MS JK flip-flop.
Group C
12 Study of Shift Registers (SISO, SIPO, PISO, PIPO). 42
 Digital Electronics Laboratory Manual (2019 Pattern)
Group-A

EXPERIMENT No: 1

TITLE: To Realize Full Adder/ Subtractor using a) Basic Gates and b) Universal Gates

APPARATUS:

1. Digital Trainer kit

2. Connecting wires
3. IC 7486, 7408, 7432, 7400, 7410, 7404.

ONLINE TOOL: DELDSIM

THEORY:

ADDER:

1. Full Adder: Full adder is a digital circuit used to calculate the sum of three
binary bits which is the main difference between this and half adder. Full adders
are complex and difficult to implement when compared to half adders. Two of the
three bits are same as before which are A, the augend bit and B, the addend bit.
The additional third bit is carry bit from the previous stage and is called Carry – in
generally represented by CIN. It calculates the sum of three bits along with the
carry. The output carry is called Carry – out and is represented by COUT.
The block diagram of a full adder with A, B and CIN as inputs and S, COUT as
outputs is shown below.

Schematic Representation of Full Adder

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Full Adder Truth Table

Based on the truth table, the Boolean functions for Sum (S) and Carry – out (Cout) can be
derived using K – Map.

For Sum S For Carry – out COUT

The simplified equation for sum is

S = A ̅ B ̅ Cin + A ̅ BC ̅ in + A B ̅ C ̅ in + AB Cin

The simplified equation for Cout is

Cout =AB + ACin + BCin

In order to implement a combinational circuit for Full Adder, it is clear from the
equations derived above, that we need 4 three input AND gates and 1 four input OR gate
for Sum and 3 two input AND gates and 1 three input OR gate for Carry – out. The logic
circuit for full adder using basic gates is shown below.

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Full Adder using NAND Gates:

Simplify the equations of sum and carry:

S = A ̅ B ̅ Cin + A ̅ BC ̅in + A B ̅ C ̅in + ABCin

= A ̅(B ̅Cin+BC ̅in) + A(B ̅ C i̅ n +BCin)

= A ̅(B⊕C) + A(B⊕C)

= A⊕B⊕C

Cout= A ̅ BCin+ A B ̅ C in + ABC ̅in + ABCin

= Cin(A ̅ B+ A B ̅) + AB(C ̅in + Cin)

=Cin(A⊕B) + AB(1)

= Cin(A⊕B) + AB

Full Adder Using NAND Gate

TESTING:

1. Make connection for full adder and full Subtractor using basic gates and NAND
gate as shown in fig.
2. Check the output for all cases mentioned in truth table of full adder and full
subtractor.

CONCLUSION: Full Adder successfully implemented using basic gates as well as

NAND gates.

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EXPERIMENT No: 2

AIM: Study of Code Converters

TITLE: Design and implement Code converters:

1. Binary to Gray
2. BCD to Excess-3

APPARATUS:

1. Digital Trainer kit

2. Connecting wires
3. IC 7404,7486,7408,7432

ONLINE TOOL: DELDSIM

THEORY:

A) Binary to Gray:

Any Binary no. converted into Gray code using following method.

For example: - Binary ---- 1 0 0 1

(add)

1 1 0 1

B) BCD to Excess 3 :

Add 3 to each digit of BCD no. which is to be converted into Excess 3.

For Example :- BCD ---- 0 1 1 0

+ 0 0 1 1

1 0 0 1

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DESIGN:
1. Convert 4 bit Binary code into Gray code

Binary Gray
Inputs Outputs
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-MAPS for All Outputs G3, G2, G1, G0:

For G3 For G2

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For G1 For G0

Equations for All Outputs G3, G2, G1, G0:

G3= B3

G2= B3’ B2 + B3 B2’= B3 XOR B2 =B3 ⊕ B2

G1= B1’ B2 + B1 B2’= B1 XOR B2 = B1 ⊕ B2

G0= B1’ B0 + B1 B0’= B1 XOR B0 = B1 ⊕ B0

Fig 2.1 Circuit Diagram for Binary to Gray

2. Convert 4 bit BCD into Excess-3 Code

Truth Table to convert BCD to Excess 3 Code

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K- Maps for all outputs W, X, Y, Z:

Fig 2.2 Circuit Diagram of BCD into Excess-3 Code

TESTING:

1. Make the connections as shown in Fig 2.1 and 2.2.

2. Switch ON the supply and verify the truth table.

CONCLUSION: Code converters studied successfully.

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EXPERIMENT No: 3

AIM: Study of BCD Adder

TITLE: Design and Realization of BCD Adder using 4-bit Binary Adder (IC 7483).

APPARATUS:

1. Digital Trainer kit

2. Connecting wires
3. IC 7483, 7408, 7432

ONLINE TOOL: DELDSIM

THEORY:

A BCD adder adds two BCD digits and produces output as a BCD digit. A BCD or Binary
Coded Decimal digit cannot be greater than 9.

The two BCD digits are to be added using the rules of binary addition. If sum is less than or
equal to 9 and carry is 0, then no correction is needed. The sum is correct and in true BCD form.

But if sum is greater than 9 or carry =1, the result is wrong and correction must be done. The
wrong result can be corrected adding six (0110) to it.

For implementing a BCD adder using a binary adder circuit IC 7483, additional combinational
circuit will be required, where the Sum output S3-S0 is checked for invalid values from 10 to 15.
The truth table and K-map for the same is as shown:

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The Boolean expression is, Y=S3S2+S3S1

The BCD adder is shown below. The output of the combinational circuit should be 1 if C out of
adder-1 is high. Therefore Y is ORed with Cout of adder-1.

The output of combinational circuit is connected to B1B2 inputs of adder-2 and B3 B1 are 0, as
they are connected to ground permanently. This makes B3B2B1B0 = 0110 if Y' = 1.

The sum outputs of adder-1 are applied to A3A2A1A0 of adder-2. The output of combinational
circuit is to be used as final output-carry and the carry output of adder-2 is to be ignored.

TESTING:
1. Make the connections as shown in above figure
2. Switch ON the supply and verify the truth table.

CONCLUSION: BCD Adder using IC7483 studied and implemented successfully.

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EXPERIMENT No: 4
AIM: Study MUX/DMUX

TITLE: Realization of Boolean Expression for suitable combination logic using MUX
74151 / DMUX 74154

APPARATUS:
1. Digital Trainer kit
2. Connecting wires
3. IC 74151, 74154

ONLINE TOOL: DELDSIM

THEORY:

1. Multiplexer

Multiplexer is a combinational logic circuit with multiple input, single output and select
lines to select particular input and applied it at output. For N input mux M select inputs
M
are required where N = 2

N input Multiplexer Block diagram

When E (Enable) input is active low. Depending upon digital code applied at the select
inputs, one out of N data inputs is get selected at output. Enable input is also used for
cascading of Mux.

MUX 74151 IC: 8:1 MUX which accepts 8 inputs and according to value of select line it
will select one of input at output. Block diagram of 8:1 Mux and truth table are shown
below.

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8:1 Multiplexer Block diagram

Select Inputs
Enable(active
S2 S1 S0 low) Y(output)
0 0 0 0 I0
0 0 1 0 I1
0 1 0 0 I2
0 1 1 0 I3
1 0 0 0 I4
1 0 1 0 I5
1 1 0 0 I6
1 1 1 0 I7

Table 3.1: Truth Table for 8:1 Multiplexer

74151: 8:1 MUX Pin Diagram

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Implement the following Boolean function Y(A,B,C,D)= ∑ m(1,3,4,11,12,13,14,15)
using MUX

Types of Designing Boolean Expression using Mux:

1) LSB Method
2) MSB Method
Using LSB Method

INPUT OUTPUT
I/P OF
A B C D Y MUX
0 0 0 0 0
0 0 0 1 1 D
0 0 1 0 0
0 0 1 1 1 D
0 1 0 0 1
0 1 0 1 0 D
0 1 1 0 0
0 1 1 1 0 0
1 0 0 0 0
1 0 0 1 0 0
1 0 1 0 0
1 0 1 1 1 D
1 1 0 0 1
1 0 1 1 1
1 1 1 0 1
1 1 1 1 1 1
Realization of 4 variable truth table using 8:1 multiplexer

Representation of input line in terms of variable D

Select Inputs
S2 S1 S0 Y
0 0 0 D
0 0 1 D
0 1 0 D
0 1 1 0
1 0 0 0
1 0 1 D
1 1 0 1
1 1 1 1
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IC 74151 Logic Diagram

2. Demultiplexer

The action or operation of a demultiplexer is opposite to that of the multiplexer. As

inverse to the MUX, demux is a one-to-many circuit. With the use of a demultiplexer, the
binary data can be bypassed to one of its many output data lines.

Demultiplexers are mainly used in Boolean function generators and decoder circuits.
Different input/output configuration demultiplexers are available in the form of single
integrated circuits (ICs).
Demultiplexers are also called as data distributors, since they transmit the same data
which is received at the input to different destinations.

Thus, a demultiplexer is a 1-to-N device whereas the multiplexer is an N-to-1 device. The
figure below shows the block diagram of a demultiplexer or simply a DEMUX.

It consists of 1 input line, n output lines and m select lines.

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74154 IC: 1:16 Demultiplexer

Circuit and pin Diagram of 1:16 Demux is shown below

Testing:
1. Make the connection of MUX and DMUX according to circuit diagram and Pin
Diagram
2. Connect Vcc & GND to IC.
3. Verify the functionality of given function according to truth table.

Conclusion: Multiplexer and Demultiplexer are successfully implemented

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EXPERIMENT No: 5

AIM: Study Digital/Magnitude Comparator

TITLE: To Verify the truth table of one bit and two bit comparators using logic gates
and comparator IC

APPARATUS:
1. Digital Trainer kit
2. Connecting wires
3. IC 7404,7486,7408,7432,7485

ONLINE TOOL: DELDSIM

THEORY:

Digital Comparator: A magnitude digital comparator is a combinational circuit that

compares two digital or binary numbers (consider A and B) and determines their relative
magnitudes in order to find out whether one number is equal, less than or greater than the
other digital number.

Three binary variables are used to indicate the outcome of the comparison as A>B, A<B,
or A=B. The below figure shows the block diagram of a n-bit comparator which
compares the two numbers of n-bit length and generates their relation between
themselves. These comparators can compare 2-bit, 4-bit and 8-bit numbers depending on
the application requirement. Block diagram is shown in fig. below

Block Diagram of n-bit Comparator

1. One Bit Magnitude Comparator

A comparator used to compare two bits, i.e., two numbers each of single bit is
called a single bit comparator. It consists of two inputs for allowing two single bit
numbers and three outputs to generate less than, equal and greater than
comparison outputs.

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The figure below shows the block diagram of a single bit magnitude comparator.
This comparator compares the two bits and produces one of the 3 outputs as L
(A<B), E (A=B) and G (A>B).

The truth table for the 1 bit comparator is given below. When A0 B0 = 00 & 11,
both inputs are equal, therefore A=B output will be high. When A0 B0 = 01, B is
more than A and hence AB is active.

From the truth table logical expressions for each output can be expressed as

In the figure, one AND gate has inputs of A0 (B0) ̅ and another has inputs (A0) ̅
B0. Therefore, one AND gate output is 1 if A0 > B0 (i.e., A0 =1 and B0 =0) and
is zero if A0 < B0 (i.e., A0 =0 and B0 =1). Similarly, other AND gate output is
one if A0 < B0 (i.e., A0 =0 and B0 =1) and is zero if A0 > B0 (i.e., A0 =1and B0
=0).

The Ex-NOR gate has inputs A0 B0, hence the output of the Ex-NOR gate will be
1 if A0 = B0 and the output will be 0 if A0 is not equal to B0.

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2. Two-Bit Comparator

A 2-bit comparator compares two binary numbers, each of two bits and produces their
relation such as one number is equal or greater than or less than the other. The figure
below shows the block diagram of a two-bit comparator which has four inputs and
three outputs.

The first number A is designated as A = A1A0 and the second number is designated
as B = B1B0. This comparator produces three outputs as G (G = 1 if A>B), E (E = 1,
if A = B) and L (L = 1 if A<B).

The truth table of this comparator is shown below which depicting various input and
output states.

The k-map simplification for the above truth table is as follows.

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From the above k-map simplification, each output can be expressed as

By using above obtained Boolean equation for each output, the logic diagram can be
implemented by using four NOT gates, seven AND gates, two OR gates and two Ex-
NOR gates.

The figure below shows the circuit diagram of a 2-bit comparator using basic logic
gates. It is also possible to construct this comparator by cascading of two 1-bit
comparators.

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TESTING:

1. Make the connections for 1-Bit Comparator, 2-bit Comparator using gates as
shown in Fig.
2. Switch ON the supply and verify the truth table.

CONCLUSION: Digital/Magnitude Comparators are studied successfully.

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EXPERIMENT No: 6

AIM: Study of Parity Generator

TITLE: Design & Implement Parity Generator using EX-OR.

APPARATUS:
1. Digital Trainer kit
2. Connecting wires
3. IC 7404,7486,7408,7432,7485

ONLINE TOOL: DELDSIM

THEORY:

Parity bit

The parity generating technique is one of the most widely used error detection techniques
for the data transmission. In digital systems, when binary data is transmitted and
processed, data may be subjected to noise so that such noise can alter 0s (of data bits) to
1s and 1s to 0s.

Hence, parity bit is added to the word containing data in order to make number of 1s
either even or odd. Thus it is used to detect errors, during the transmission of binary data
.The message containing the data bits along with parity bit is transmitted from transmitter
node to receiver node.

Parity Generator

It is combinational circuit that accepts an n-1 bit stream data and generates the additional
bit that is to be transmitted with the bit stream. This additional or extra bit is termed as a
parity bit.

In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data
stream and the parity bit is ‘1’ if there are odd number of 1s in the data stream.

In odd parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the data
stream and the parity bit is ‘0’ if there are odd number of 1s in the data stream. Let us
discuss both even and odd parity generators.

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Even Parity Generator

Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the
three inputs A, B and C are applied to the circuits and output bit is the parity bit P. The
total number of 1s must be even, to generate the even parity bit P.

The figure below shows the truth table of even parity generator in which 1 is placed as
parity bit in order to make all 1s as even when the number of 1s in the truth table is odd.

The K-map simplification for 3-bit message even parity generator is

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The above expression can be implemented by using two Ex-OR gates. The circuit
diagram of even parity generator with two Ex – OR gates is shown below. The three bit
message along with the parity generated by this circuit which is transmitted to the
receiving end where parity checker circuit checks whether any error is present or not.

To generate the even parity bit for a 4-bit data, three Ex-OR gates are required to add the
4-bits and their sum will be the parity bit.

Circuit Diagram for Even Parity Generator

Odd Parity Generator

Let us consider that the 3-bit data is to be transmitted with an odd parity bit. The three
inputs are A, B and C and P is the output parity bit. The total number of bits must be odd
in order to generate the odd parity bit.

In the given truth table below, 1 is placed in the parity bit in order to make the total
number of bits odd when the total number of 1s in the truth table is even.

The truth table of the odd parity generator can be simplified by using K-map as

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Circuit Diagram for odd Parity Generator

TESTING:

1. Make the connections for 3-bit even and odd parity generator using gates as
shown in Fig.
2. Switch ON the supply and verify the truth table.

CONCLUSION: 3-Bit Parity Generator is studied successfully.

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Group-B

EXPERIMENT No: 7
AIM: Implementation of SR, T and D flip-flop using JK flip-flop and its conversion.
TITLE: To Filp-Flop Conversion: Design and Realization

APPARATUS:

1. Digital Trainer kit

2. Connecting wires
3. IC7476, 7404, 7408, 7400s

ONLINE TOOL: DELDSIM

THEORY:

Fundamental building block of sequential circuits is flip-flop. Flip-flop is a 1-bit storage

element. It is edge triggered device.

(a) +ve edge triggered (b) -ve edge triggered

Types of flip-flops:

FLIP-FLOPS

Asynchronous Synchronous
Output change as soon as Output change in
input applied changes the synchronism with the
state clock pulses

1. SR FLIP-FLOP
2. JK FLIP-FLOP
3. M/S JK FLIP-FLOP
4. T FLIP-FLOP
5. D FLIP-FLOP

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Flip Flop Conversion

1) JK Flip Flop to SR Flip Flop

S and R will be the external inputs to J and K. As shown in the logic diagram below, J
and K will be the outputs of the combinational circuit. Thus, the values of J and K
have to be obtained in terms of S, R and Qp. The logic diagram is shown below.

A conversion table is to be written using S, R, Qp, Qp+1, J and K. For two inputs, S
and R, eight combinations are made. For each combination, the corresponding Qp+1
outputs are found. The outputs for the combinations of S=1 and R=1 are not permitted
for an SR flip flop. Thus the outputs are considered invalid and the J and K values are
taken as “don’t cares”.

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2) JK Flip Flop to D Flip Flop

D is the external input and J and K are the actual inputs of the flip flop. D and Qp
make four combinations. J and K are expressed in terms of D and Qp. The four
combination conversion table, the K-maps for J and K in terms of D and Qp, and
the logic diagram showing the conversion from JK to D are given below.

3) JK Flip Flop to T Flip Flop

J and K are the actual inputs of the flip flop and T is taken as the external input
for conversion. Four combinations are produced with T and Qp. J and K are
expressed in terms of T and Qp. The conversion table, K-maps, and the logic
diagram are given below.

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IC 7476 (Dual- JK Flip Flop) Pin Diagram

TESTING:

1. Make the connections for conversion of JK to SR, JK to D, JK to T using circuit

diagram and pin diagram as shown above.
2. Switch ON the supply and verify the truth tables of all conversion.

CONCLUSION: Flip-Flop conversion and its design and realization are studied
successfully.

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EXPERIMENT No: 8

AIM: Study of 3- bit Ripple/Asynchronous Counter

TITLE: Design of 2 bit and 3 bit Ripple Counter using MS JK flip-flop.

APPARATUS:

1. Digital Trainer kit

2. Connecting wires
3. IC 7476

ONLINE TOOL: DELDSIM

THEORY:

Counter is a sequential circuit. A digital circuit which is used for counting pulses is
known counter. Counter is the widest application of flip-flops. It is a group of flip-flops
with a clock signal applied. Counters are of two types.

1. Asynchronous or ripple counters.

2. Synchronous counters.

Synchronous Counter

In a synchronous counter, the input pulses are applied to all clock pulse inputs of all flip
flops simultaneously (directly). Synchronous counter is also known as parallel sequential
circuit. Examples of Synchronous Counters are as below:

1. Ring Counter
2. Johnson Counter (Switch Tail or Twisted Ring Counter)

Asynchronous or ripple counters

In an asynchronous counter, the flip flop output transition serves as a source for
triggering other flip flops. In other words, the clock pulse inputs of all flip flops, except
the first, are triggered not by the incoming pulses, but rather by the transition that occurs
in previous flip flop’s output.. Asynchronous counter is also known as serial sequential
circuit. Examples of Asynchronous Counters are as below:

Binary Ripple Counter

Up Down Counter

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2 bit Ripple Counter using MS JK flip-flop.

3 bit Ripple Counter using MS JK flip-flop.

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Circuit Diagram and Timing Diagram of 3-Bit Ripple UP Counter

TESTING:

1. Make the connections for 3-bit Ripple UpCounter as well as down counter using
circuit diagram and pin diagram of 7476.
2. Switch ON the supply and verify the truth table of UP counter.

CONCLUSION: Ripple counter studied successfully.

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 Digital Electronics Laboratory Manual (2019 Pattern)
EXPERIMENT No: 9
AIM: Study Up/Down synchronous Counter

TITLE: A. Realization of 3 bit Up/Down Counter using MS JK Flip Flop / D FlipFlop

APPARATUS:

1. Digital Trainer kit

2. Connecting wires
3. IC 7476, 7408, 7432, 7404.

ONLINE TOOL: DELDSIM

THEORY:

Realization of 3 bit synchronous Up/Down Counter using MS JK Flip Flop

Bidirectional Counter or UP/DOWN Counter

Both Synchronous and Asynchronous counters are capable of counting “Up” or

counting “Down”, but there is another more “Universal” type of counter that can
count in both directions either Up or Down depending on the state of their input
control pin and these are known as Bidirectional Counters.

Bidirectional counters, also known as Up/Down counters, are capable of counting

in either direction through any given count sequence and they can be reversed at
any point within their count sequence by using an additional control input as
shown below.

For 3-bit Counter, 3 flip flops are required label it as 0, 1, 2

Here we are using 3 JK flip flop with inputs J0, K0, J1, K1, J2, K2 and outputs
are Q0, Q1 and Q2 respectively. Using Excitation table of JK flip flop excitation
table of whole circuit is shown below which contains present state, input (control
input M).
K-map and Circuit Diagram are also shown below.

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K-Map for all Flip Flop Inputs:

J0 = K0 = 1
J1 = K1 = Q0̅M + ̅Q0M
J2 = K2 = ̅M Q1Q0 + M ̅Q1 ̅Q0

3 bit synchronous Up/Down Counter

TESTING:

1. Make the connections for 3-bit synchronous Up/Down Counter according to

circuit diagram
2. Switch ON the supply and verify the truth table of UP/Down counter.

CONCLUSION: 3 bit Synchronous UP/DOWN counter using JK flip flop studied

successfully.

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 Digital Electronics Laboratory Manual (2019 Pattern)
EXPERIMENT No: 10
AIM: Study Decade Counter

TITLE: Realization of Mod -N counter using (Decade Counter IC 7490).

APPARATUS:

1. Digital Trainer kit

2. Connecting wires
3. IC 7490, 7408.

ONLINE TOOL: DELDSIM

THEORY:

Realization of Mod -20 counter using (7490)

7490 IC:
A BCD counter is a special type of a digital counter which can count to ten on the
application of a clock signal. To make a digital counter which counts from 1 to
10, we need to have the counter count only the binary numbers 0000 to 1001.
That is from 0 to 9 in decimal and fortunately for us, counting circuits are readily
available as integrated circuits with one such circuit being the Asynchronous
74LS90 Decade Counter.

The sequence of the decade counter is shown in the table below:

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Truth Table of Decade Counter

Mod – 20 Counter Using 7490 IC

Mod-20 counter counts total 20 states from 0 to 19 for each clock pulse. When 20th state
reach counter will reset its value to 0 and again start counting. To design mod-20 counter
we should connect two 7490Ics that will count states from 0 to 99.
At 20 th state counter will reset its value to 0000. To reset it QB of tens digit is connected
to reset pin as shown below.

Mod-20 Counter using two 7490IC

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TESTING:

1. Make the connections for decade Counter according to pin diagram as well as
Mod-20 counter using circuit diagram and pin diagram.
2. Switch ON the supply and verify the truth table of decade counter and Mod-20
counter.

CONCLUSION: Mod- N counter using 7490IC studied successfully.

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EXPERIMENT No: 11

AIM: Study of Sequence Generator

TITLE: Design and implement Sequence generator for Prime Number using MS JK flip-flop.

APPARATUS:

1. Digital Trainer kit

2. Connecting wires
3. IC 7476, 7408

ONLINE TOOL: DELDSIM

THEORY:

Definition: A sequential circuit which generates a prescribed sequence of bits in synchronism

with a clock is referred to as a sequence generator.

These pulse trains or sequence of bits can be used to open valves, close gates, turn-on lights,
turn-off machines and other variety of jobs.

Some of the applications of the sequence generator are as follows:

1. Random bit generator

2. Counters

3. Code generators

4. Period generator

Excitation Table: - The tabular representation of the operation of flip flop (i.e.: Operational
Characteristic)

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TESTING:

1. Make the connections of sequence generator according to circuit diagram and pin
diagram of JK flip flop
2. Switch ON the supply and verify the given sequence.

CONCLUSION: Sequence Generator for given sequence is studied successfully.

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Group C

EXPERIMENT No: 12
AIM: Shift Registers

TITLE: Study of Shift Registers (SISO, SIPO, PISO,PIPO)

THEORY:

The Shift Register

 The Shift Register is another type of sequential logic circuit that can be used for the
storage or the transfer of data in the form of binary numbers.

 This sequential device loads the data present on its inputs and then moves or “shifts” it to
its output once every clock cycle, hence the name Shift Register.
 A shift register basically consists of several single bit “D-Type Data Latches”, one for
each data bit, either a logic “0” or a “1”, connected together in a serial type daisy-chain
arrangement so that the output from one data latch becomes the input of the next latch
and so on.
 Data bits may be fed in or out of a shift register serially, that is one after the other from
either the left or the right direction, or all together at the same time in a parallel
configuration.
 Shift Registers are used for data storage or for the movement of data and are therefore
commonly used inside calculators or computers to store data such as two binary numbers
before they are added together, or to convert the data from either a serial to parallel or
parallel to serial format. The individual data latches that make up a single shift register
are all driven by a common clock ( Clk ) signal making them synchronous devices.
 Generally, shift registers operate in one of four different modes with the basic movement
of data through a shift register being:
o Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit
at a time, with the stored data being available at the output in parallel form.
o Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of
the register, one bit at a time in either a left or right direction under clock control.

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o Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under
clock control.
o Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously
into the register, and transferred together to their respective outputs by the same
clock pulse.

1. Serial-in to Parallel-out (SIPO) Shift Register

4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Let’s assume that all the flip-flops ( FFA to FFD ) have just been
RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level “0” ie, no parallel
data output.
If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output
of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other outputs
still remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has returned
LOW again to logic “0” giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the output of FFB
and QB HIGH to logic “1” as its input D has the logic “1” level on it from QA. The logic “1” has
now moved or been “shifted” one place along the register to the right as it is now at QA.
When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and so
on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic
level “0” because the input to FFA has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one place to the right,
and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the
register. This data value can now be read directly from the outputs of QA toQD.
Then the data has been converted from a serial data input signal to a parallel data output. The
truth table and following waveforms show the propagation of the logic “1” through the register
from left to right as follows.

2. Serial-in to Serial-out (SISO) Shift Register

This shift register is very similar to the SIPO above, except were before the data was read
directly in a parallel form from the outputs QA to QD, this time the data is allowed to flow

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straight through the register and out of the other end. Since there is only one output,
the DATA leaves the shift register one bit at a time in a serial pattern, hence the name Serial-in
to Serial-Out Shift Register or SISO.
The SISO shift register is one of the simplest of the four configurations as it has only three
connections, the serial input (SI) which determines what enters the left hand flip-flop, the serial
output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock
signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift
register.

4-bit Serial-in to Serial-out Shift Register

3. Parallel-in to Serial-out (PISO) Shift Register

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out
one above. The data is loaded into the register in a parallel format in which all the data bits enter
their inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then
read out sequentially in the normal shift-right mode from the register at Q representing the data
present at PA to PD.
This data is outputted one bit at a time on each clock cycle in a serial format. It is important to
note that with this type of data register a clock pulse is not required to parallel load the register as
it is already present, but four clock pulses are required to unload the data.

4-bit Parallel-in to Serial-out Shift Register

As this type of shift register converts parallel data, such as an 8-bit data word into serial format,
it can be used to multiplex many different input lines into a single serial DATA stream which
can be sent directly to a computer or transmitted over a communications line. Commonly
available IC’s include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.

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4. Parallel-in to Parallel-out (PIPO) Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of shift
register also acts as a temporary storage device or as a time delay device similar to the SISO
configuration above. The data is presented in a parallel format to the parallel input
pins PA to PD and then transferred together directly to their respective output pinsQA to QA by the
same clock pulse. Then one clock pulse loads and unloads the register. This arrangement for
parallel loading and unloading is shown below.

4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four configurations as it has only three connections,
the parallel input (PI) which determines what enters the flip-flop, the parallel output (PO) and the
sequencing clock signal (Clk).
Similar to the Serial-in to Serial-out shift register, this type of register also acts as a temporary
storage device or as a time delay device, with the amount of time delay being varied by the
frequency of the clock pulses. Also, in this type of register there are no interconnections between
the individual flip-flops since no serial shifting of the data is required.

CONCLUSION: Thus we have studied Shift Registers successfully.

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