5.

Control Unit
MICRO-OPERATIONS :-

The Fetch Cycle :- which occurs at the beginning of each instruction cycle and causes an
instruction to be fetched from memory.
■ Memory address register (MAR): Is connected to the address lines of the system bus. It
specifies the address in memory for a read or write operation.
■ Memory buffer register (MBR): Is connected to the data lines of the system bus. It contains
the value to be stored in memory or the last value read from memory.
■ Program counter (PC): Holds the address of the next instruction to be fetched.
■ Instruction register (IR): Holds the last instruction fetched.

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■ First time unit: Move contents of PC to MAR.
■ Second time unit: Move contents of memory location specified by MAR to MBR. Increment
by I the contents of the PC.
■ Third time unit: Move contents of MBR to IR.

The Indirect Cycle :- If the instruction specifies an indirect address, then an indirect cycle
must precede the execute cycle. The data flow differs somewhat from that indicated in
Figure 14.7 (Data Flow, Indirect Cycle) and includes the following micro-operations:

In t3 address field of the IR is updated from the MBR, so that it now contains a direct rather
than an indirect address.

The Interrupt Cycle:- At the completion of the execute cycle, a test is made to determine
whether any enabled interrupts have occurred. If so, the interrupt cycle occurs. The nature of
this cycle varies greatly from one machine to another

 Save the PC: The computer records where it was (the PC) before the interrupt happened.
 Set the Destination: The computer figures out where to store the saved PC.
 Jump to the Interrupt Handler: The computer jumps to a special routine (the interrupt
handler) that knows how to deal with the interrupt.

The Execute Cycle :-

 Variable sequence: The sequence of micro-operations depends on the opcode.
 Instruction decoding: The control unit examines the opcode to determine the appropriate
sequence.

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First, consider an add instruction:
ADD R1, X
which adds the contents of the location X to register R1. T
he following sequence of micro-operations might occur:

t1: Load the memory address from the instruction into the MAR.
t2: Fetch the data at that address and store it in the MBR.
t3: Add the value in MBR to the value in R1, and store the result in R1.

Flowchart for Instruction Cycle :-

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Instruction Cycle Code (ICC):-
00  Fetch Cycle
01  Indirect cycle

1. Setup Interrupt:

 This is the initial state where the CPU is ready to handle an interrupt.
 The Interrupt Control Code (ICC) is set to 00 to indicate that no interrupt is currently
being processed.

2. Fetch Instruction:

 The PC is used to fetch the next instruction from memory.

 The fetched instruction is stored in the Instruction Register (IR).

3. Decode Opcode:

 The control unit analyzes the opcode of the fetched instruction to determine the operation
to be performed.

4. Execute Instruction:

 If the instruction is not an interrupt or an indirect addressing instruction, the CPU

executes the instruction directly.
 The ICC remains at 10 during the execution phase.

5. Check for Interrupt:

 After executing the instruction, the CPU checks if an interrupt is pending.

 If an interrupt is pending and enabled, the ICC is set to 11, indicating that an interrupt is
being processed.

6. Indirect Addressing:

 If the instruction involves indirect addressing (i.e., the operand address is stored in
another memory location), the CPU fetches the effective address from the specified
memory location.
 The ICC is set to 01 during the indirect addressing phase.

7. Return to Fetch:

 Once the current instruction is completed (either directly or indirectly), the CPU returns
to the fetch stage to fetch the next instruction.
 The ICC is reset to 00 to indicate that no interrupt is currently being processed.

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CONTROL OF THE PROCESSOR :-
The following three-step process leads to a characterization of the control unit:
1. Define the basic elements of the processor.
2. Describe the micro-operations that the processor performs.
3. Determine the functions that the control unit must perform to cause the micro-operations to be
performed
Basic functional elements of the processor:-
■ ALU
■ Registers
■ Internal data paths
■ External data paths
■ Control unit

All micro-operations fall into one of the following categories:

■ Transfer data from one register to another.
■ Transfer data from a register to an external interface (e.g., system bus).
■ Transfer data from an external interface to a register.
■ Perform an arithmetic or logic operation, using registers for input and output.

The control unit performs two basic tasks:

■ Sequencing: The control unit causes the processor to step through a series of micro-
operations in the proper sequence, based on the program being executed.
■ Execution: The control unit causes each micro-operation to be performed.

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Control Signals :-

The inputs are:

■ Clock: This is how the control unit “keeps time.” The control unit causes one micro-operation
(or a set of simultaneous micro-operations) to be performed for each clock pulse. This is
sometimes referred to as the processor cycle time, or the clock cycle time.
■ Instruction register: The opcode and addressing mode of the current instruction are used to
determine which micro-operations to perform during the execute cycle.
■ Flags: These are needed by the control unit to determine the status of the processor and the
outcome of previous ALU operations. For example, for the increment- and- skip- if- zero (ISZ)
instruction, the control unit will increment the PC if the zero flag is set.
■ Control signals from control bus: The control bus portion of the system bus provides signals
to the control unit

The outputs are as follows:

■ Control signals within the processor: These are two types: those that cause data to be moved
from one register to another, and those that activate specific ALU functions.
■ Control signals to control bus: These are also of two types: control signals to memory, and
control signals to the I/O modules.

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A Control Signals Example :-

Control signals go to three separate destinations:

■ Data paths: The control unit controls the internal flow of data. For example, on instruction
fetch, the contents of the memory buffer register are transferred to the IR. For each path to be
controlled, there is a switch (indicated by a circle in the figure). A control signal from the control
unit temporarily opens the gate to let data pass.
■ ALU: The control unit controls the operation of the ALU by a set of control signals. These
signals activate various logic circuits and gates within the ALU.
■ System bus: The control unit sends control signals out onto the control lines of the system bus
(e.g., memory READ)

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Internal Processor Organization :-

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Control Unit:

 Controls the overall operation of the CPU.

 Coordinates the activities of other components.

Instruction Register (IR):

 Stores the current instruction being executed.

 Provides the opcode and operands to the control unit for decoding and execution.

Program Counter (PC):

 Holds the address of the next instruction to be fetched.

 Increments after each instruction is fetched to point to the next one.

Memory Address Register (MAR):

 Stores the address of the memory location to be accessed.

 Connects to the address lines of the internal bus.

Memory Buffer Register (MBR):

 Temporarily stores data fetched from or written to memory.

 Connects to the data lines of the internal bus.

Accumulator (AC):

 A general-purpose register used for arithmetic and logical operations.

 Stores intermediate results and final results.

Y and Z:

 Additional registers that can be used for various purposes, such as storing operands or
temporary results.

Arithmetic Logic Unit (ALU):

 Performs arithmetic operations (addition, subtraction, multiplication, division) and

logical operations (AND, OR, NOT).

Internal CPU Bus:

 A communication channel within the CPU that connects the various components.
 Allows data and control signals to be transferred between components.

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Control unit implementation Techniques :-
■ Hardwired implementation
■ Microprogrammed implementation

Let us consider a single control signal, C5

P and Q, that have the following interpretation:

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Instruction Register (IR):

 Stores the current instruction being executed.

 Provides the opcode to the decoder for interpretation.

Decoder:

 Analyzes the opcode of the instruction.

 Generates a sequence of control signals (C0, C1, ..., Cm) based on the decoded opcode.

Timing Generator:

 Produces a sequence of timing signals (T1, T2, ..., Tn) to control the timing of operations
within the CPU.

Control Unit:

 Receives the decoded control signals and timing signals.

 Generates control signals to activate various components of the CPU at the appropriate
time.

Flags:

 Stores status flags that indicate the results of operations, such as carry, zero, overflow,
and sign.
 These flags can be used for conditional branching and other control flow decisions.

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Disadvantages:-The task of implementing a combinatorial circuit that satisfies all of these
equations becomes extremely difficult.

Microprogrammed control unit:- . In fact it is a language, known as a

microprogramming language. Each line describes a set of micro-operations occurring at one time
and is known as a microinstruction. A sequence of instructions is known as a microprogram, or
firmware.

Microinstruction
1) horizontal
2) vertical

Horizontal Microinstruction Format:

 Microinstruction Address: Specifies the address of the next microinstruction to be

executed.

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  Jump Condition: Determines whether the next microinstruction will be fetched
unconditionally or based on certain conditions (e.g., zero, overflow, indirect bit).
 System Bus Control Signals: Control the behavior of the system bus, such as data
transfers between the CPU and memory or I/O devices.
 Internal CPU Control Signals: Control the operation of various internal components of
the CPU, such as the ALU, registers, and control unit.

Vertical Microinstruction Format:

 Microinstruction Address: Similar to the horizontal format, specifies the address of the
next microinstruction.
 Jump Condition: Also similar, determines the branching condition.
 Function Codes: A field that encodes the specific operation to be performed by the
microinstruction. This allows for more compact microcode and potentially faster
execution.

Organization of Control Memory :-

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Control Memory:

 Stores microinstructions that define the sequence of microoperations to be executed by

the CPU.
 Each microinstruction contains a set of control signals that control the operation of
various internal components of the CPU.

Microinstruction Format:

 The format of microinstructions is not explicitly shown in the image, but it typically
includes a field for the microinstruction address and a field for the control signals.

Control Memory Organization:

 The control memory is organized into a sequence of routines, each representing a specific
task or operation that the CPU can perform.
 The routines are linked together by jump instructions, which specify the next
microinstruction to be executed.

Routines:

 Fetch cycle routine: Responsible for fetching the next instruction from memory.
 Indirect cycle routine: Handles indirect addressing, where the effective address of the
operand is determined by the value in a register.
 Interrupt cycle routine: Processes interrupts, suspending the current execution and
transferring control to an interrupt service routine.
 Execute cycle beginning routine: Initializes the execution of an instruction.
 Opcode routine: Contains microinstructions for executing specific opcodes
(instructions).
 AND routine: Performs the AND operation on two operands.
 ADD routine: Performs the addition operation on two operands.
 IOF routine: Handles input/output operations.

Control Flow:

 The control flow through the control memory is determined by the jump instructions in
each microinstruction.
 The CPU starts by executing the fetch cycle routine, which fetches the next instruction.
 Based on the opcode of the fetched instruction, the CPU jumps to the corresponding
opcode routine to execute the instruction.
 After executing the instruction, the CPU jumps back to the fetch cycle routine to fetch the
next instruction.
 If an interrupt occurs, the CPU jumps to the interrupt cycle routine to handle the
interrupt.

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Microprogrammed Control Unit :-

The control unit functions as follows:

1. To execute an instruction, the sequencing logic unit issues a READ command to the control
memory.
2. The word whose address is specified in the control address register is read into the control
buffer register.
3. The content of the control buffer register generates control signals and next-address
information for the sequencing logic unit.
4. The sequencing logic unit loads a new address into the control address register based on the
next-address information from the control buffer register and the ALU flags.

The last step just listed needs elaboration. At the conclusion of each microinstruction, the
sequencing logic unit loads a new address into the control address register. Depending on the
value of the ALU flags and the control buffer register, one of three decisions is made:
■ Get the next instruction: Add 1 to the control address register.
■ Jump to a new routine based on a jump microinstruction: Load the address field of the
control buffer register into the control address register.
■ Jump to a machine instruction routine: Load the control address register based on the
opcode in the IR.

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Functioning of Microprogrammed Control Unit:-

 The instruction register is loaded with the current instruction.

 The decoder decodes the instruction opcode to determine the corresponding microinstruction
address.
 The sequencing logic generates the control address and loads it into the CAR.
 The read signal is asserted, causing the microinstruction at the specified address to be fetched
from the control memory and stored in the CBR.
 The control signals in the CBR are decoded to generate the actual control signals that drive the
CPU's internal components.
 The next address control determines the address of the next microinstruction to be fetched, and
the process repeats.

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The two basic tasks performed by a microprogrammed control unit are as follows:
■ Microinstruction sequencing: Get the next microinstruction from the control memory.
■ Microinstruction execution: Generate the control signals needed to execute the
microinstruction.

Design Considerations
1) The size of the microinstruction :- The first concern is obvious; minimizing the size of the
control memory reduces the cost of that component
2) The address-generation time:- The second concern is simply a desire to execute
microinstructions as fast as possible.

In executing a microprogram, the address of the next microinstruction to be executed is in one of

these categories:
■ Determined by instruction register
■ Next sequential address
■ Branch

Sequencing Techniques
■ Two address fields
■ Single address field
■ Variable format

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Two address fields :-

 The control address register stores the current microinstruction address.

 The address decoder identifies the microinstruction to be fetched.
 The control memory stores the microinstructions.
 The branch control logic determines the need for branching based on flags and selects the
appropriate address.
 The address selection logic chooses the correct address based on the branch condition.
 The multiplexer selects the next address for the control address register.

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Branch Control Logic: Single Address Field:-

 The address decoder identifies the microinstruction to be fetched.

 The control memory stores the microinstructions.
 The control buffer register holds the current microinstruction.
 The branch logic determines the need for branching based on flags.
 The address selection logic chooses the next address based on the branch condition.
 The multiplexer selects the next address for the control address register.
 The +1 block increments the address for sequential execution.

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Branch Control Logic: Variable Format :-

 The address decoder identifies the microinstruction to be fetched.

 The control memory stores the microinstructions.
 The control buffer register holds the current microinstruction.
 The branch control field specifies the branch condition and target address.
 The gate and function logic decodes the branch control field.
 The branch logic determines the need for branching based on flags and the decoded branch
condition.
 The address selection logic chooses the next address based on the branch condition.
 The multiplexer selects the next address for the control address register.
 The +1 block increments the address for sequential execution.

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MICROINSTRUCTION EXECUTION :-
A Taxonomy of Microinstructions
Microinstructions can be classified in a variety of ways. Distinctions that are commonly made
in the literature include the following:
■ Vertical/horizontal
■ Packed/unpacked
■ Hard/soft microprogramming
■ Direct/indirect encoding

The design of an encoded microinstruction format can now be stated in simple terms:
■ Organize the format into independent fields. That is, each field depicts a set of actions (pattern
of control signals) such that actions from different fields can occur simultaneously.

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■ Define each field such that the alternative actions that can be specified by the field are
mutually exclusive. That is, only one of the actions specified for a given field could occur at a
time.

 The vertical format uses multiple microinstructions to control each operation, while the
horizontal format uses a single microinstruction with multiple fields to control multiple
operations simultaneously.
 The choice of format depends on factors like the complexity of the instruction set, the desired
speed of execution, and the available hardware resources.
 The horizontal format can potentially achieve higher performance due to its ability to execute
multiple operations in parallel.
 However, the horizontal format can be more complex to design and implement.

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Control Unit Organization :-

1. Instruction Register:

 This register holds the current instruction being executed.

2. Sequencing Logic:

 This logic analyzes the instruction in the instruction register and generates the appropriate
control signals to sequence the execution of the instruction.
 It also receives status signals (flags) from the ALU and other components to determine
the next steps in the execution process.

3. Control Address Register:

 This register stores the address of the current microinstruction to be executed. It acts as a
pointer to the control memory.

4. Control Memory:

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  This memory stores the microinstructions, which are the basic control signals that
sequence the operation of the processor. Each microinstruction contains control signals
for various processor components like the ALU, registers, and memory units.

5. Control Buffer Register:

 This register holds the current microinstruction being executed. It receives the
microinstruction from the control memory and provides the control signals to the various
processor components.

6. Control Logic:

 This logic decodes the microinstruction and generates the necessary control signals for
the ALU, registers, and other components.
 It also receives external control signals from other components, such as the interrupt
controller, to modify the execution flow.

7. Internal Control Signals:

 These signals are generated by the control logic and are used to control the operation of
the processor's internal components, such as the ALU, registers, and memory units.

8. External Control Signals:

 These signals are generated by the control logic and are used to control the operation of
external devices, such as I/O devices and memory modules.

The Microinstruction Spectrum :-

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