4.

PROCESSOR ORGANIZATION
The CPU with the System Bus :

 The control unit fetches an instruction from memory and decodes it to determine the operation
to be performed and the operands involved.
 The control unit sends control signals to the ALU and registers to perform the required
operation.
 The ALU processes the data and stores the result in a register.
 The control unit sends the result to memory or an input/output device using the data bus.
 The control unit fetches the next instruction and repeats the process until the program is
completed.

The organization of the processor, let us consider the requirements placed on the processor,
the things that it must do:
■ Fetch instruction: The processor reads an instruction from memory (register, cache, main
memory).
■ Interpret instruction: The instruction is decoded to determine what action is required.
■ Fetch data: The execution of an instruction may require reading data from memory or an I/O
module.

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 ■ Process data: The execution of an instruction may require performing some arithmetic or
logical operation on data.
■ Write data: The results of an execution may require writing data to memory or an I/O
module.

Internal Structure of the CPU :-

 The control unit sends an instruction to the ALU, specifying the operation to be performed and
the operands involved.
 The ALU uses its components (shifter, complementer, arithmetic and Boolean logic) to
perform the operation.
 The result of the operation is stored in a register.
 The ALU also sets the status flags to indicate the result of the operation.
 The control unit uses the status flags to determine the next steps in the execution of the
instruction.

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REGISTER ORGANIZATION :
The registers in the processor perform two roles:
■ User-visible registers: Enable the machine- or assembly language programmer to minimize
main memory references by optimizing use of registers.
■ Control and status registers: Used by the control unit to control the operation of the
processor and by privileged, operating system programs to control the execution of programs.

User-Visible Registers :
A user-visible register is one that may be referenced by means of the machine
language that the processor executes. We can characterize these in the following categories:
■ General purpose :- General-purpose registers can be assigned to a variety of functions by the
programmer. Sometimes their use within the instruction set is orthogonal to the operation.
■ Data :- Data registers may be used only to hold data and cannot be employed in the
calculation of an operand address.
■ Address :- Address registers may themselves be somewhat general purpose, or they may be
devoted to a particular addressing mode
■ Condition codes :- Condition codes are bits set by the processor hardware as the result of
operations.

Control and Status Registers :-

There are a variety of processor registers that are employed to control the
operation of the processor. Most of these, on most machines, are not visible to the user. Some
of them may be visible to machine instructions executed in a control or operating system mode.

Four registers are essential to instruction execution:

■ Program counter (PC): Contains the address of an instruction to be fetched.
■ Instruction register (IR): Contains the instruction most recently fetched.
■ Memory address register (MAR): Contains the address of a location in memory.
■ Memory buffer register (MBR): Contains a word of data to be written to memory or the word
most recently read.

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Common fields or flags include the following:
■ Sign: Contains the sign bit of the result of the last arithmetic operation.
■ Zero: Set when the result is 0.
■ Carry: Set if an operation resulted in a carry (addition) into or borrow (subtraction) out of a
high-order bit. Used for multiword arithmetic operations.
■ Equal: Set if a logical compare result is equality.
■ Overflow: Used to indicate arithmetic overflow.
■ Interrupt Enable/Disable: Used to enable or disable interrupts.
■ Supervisor: Indicates whether the processor is executing in supervisor or user mode.

The Instruction Cycle : refer unit 1

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1. Fetch:

 The CPU fetches the next instruction from memory.

 The address of the instruction is stored in the program counter (PC).
 The instruction is loaded into the instruction register (IR).

2. Execute:

 The CPU decodes the instruction to determine the operation to be performed and the
operands involved.
 The CPU executes the instruction using its arithmetic and logic unit (ALU) and registers.

3. Indirect:

 If the instruction requires indirect addressing, the CPU fetches the effective address of the
operand from memory.
 The effective address is used to access the actual data.

4. Interrupt:

 If an interrupt occurs during the execution of an instruction, the CPU suspends the
current instruction and jumps to an interrupt service routine (ISR).
 The ISR handles the interrupt and then returns control to the interrupted instruction.

1 ] Data Flow, Fetch Cycle :-

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 PC: The PC holds the address of the next instruction.
 MAR: The PC's value is transferred to the MAR.
 Memory: The MAR's address is used to access memory, and the instruction is fetched.
 MBR: The fetched instruction is stored in the MBR.
 IR: The instruction from the MBR is transferred to the IR for decoding and execution

2 ] Data Flow, Indirect Cycle:-

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Indirect Cycle Steps:

1. PC: The PC holds the address of the instruction.

2. MAR: The PC's value is transferred to the MAR.
3. Memory: The MAR's address is used to access memory, and the address of the operand
is fetched.
4. MBR: The fetched operand address is stored in the MBR.
5. MAR: The MBR's value (operand address) is transferred to the MAR.
6. Memory: The MAR's address is used to access memory, and the actual data is fetched.
7. MBR: The fetched data is stored in the MBR.
8. Instruction Execution: The CPU uses the fetched data to execute the instruction.

3 ] Data Flow, Interrupt Cycle :-

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Interrupt Cycle Steps:

1. Interrupt Request: An external device or event generates an interrupt request.

2. Interrupt Handling: The CPU suspends its current instruction and saves its state (e.g.,
PC, registers).
3. Interrupt Vector: The CPU determines the appropriate interrupt service routine (ISR)
based on the interrupt vector table.
4. ISR Execution: The CPU jumps to the ISR's address.
5. ISR Processing: The ISR handles the interrupt, which might involve reading or writing
data to/from devices or performing other tasks.
6. Return from Interrupt: The ISR returns control to the interrupted instruction, restoring
the saved state.
7. Instruction Resumption: The CPU resumes execution of the interrupted instruction.

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INSTRUCTION PIPELINING :-
Two-Stage Instruction Pipeline

Simplified View (a):

 Instruction: An instruction is fetched from memory.

 Fetch: The next instruction is fetched from memory while the current instruction is being
executed.
 Execute: The fetched instruction is executed.
 Result: The result of the execution is produced.

Expanded View (b):

 Instruction: An instruction is fetched from memory.

 Fetch: The next instruction is fetched from memory.
 Wait: If the current instruction requires data from memory, the pipeline stalls while the
data is fetched.
 New address: If the current instruction is a branch instruction, a new address is
calculated for the next instruction.
 Wait: If the branch is taken, the pipeline stalls while the new instruction is fetched.
 Execute: The fetched instruction is executed.
 Result: The result of the execution is produced.

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The following decomposition of the instruction processing.
■ Fetch instruction (FI): Read the next expected instruction into a buffer.

■ Decode instruction (DI): Determine the opcode and the operand specifiers.

■ Calculate operands (CO): Calculate the effective address of each source operand. This may involve
displacement, register indirect, indirect, or other forms of address calculation.

■ Fetch operands (FO): Fetch each operand from memory. Operands in registers need not be fetched.

■ Execute instruction (EI): Perform the indicated operation and store the result, if any, in the specified
destination operand location.

■ Write operand (WO): Store the result in memory.

Timing Diagram for Instruction Pipeline Operation / Six stage of Pipelining :-

 Instruction 1: In cycle 1, Instruction 1 enters the Fetch Instruction stage (FI).

 Instruction 2: In cycle 2, Instruction 1 moves to the Decode Instruction stage (DI), and
Instruction 2 enters the FI stage.
 Subsequent Instructions: This pattern continues, with each instruction moving through the
pipeline stages in successive cycles.

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 Overlapping Stages: The pipeline allows multiple instructions to be in different stages
simultaneously, improving efficiency.
 Stalls: If an instruction requires data that is not available, or if a branch is taken, the pipeline
may stall, causing a delay in the execution of subsequent instructions.

Conditional Branch on Instruction Pipeline Operation :-

 Conditional Branch: A branch instruction that changes the program flow based on a
condition.
 Pipeline Stalls: When a conditional branch is encountered, the pipeline may stall while the
branch condition is evaluated and the target address is determined.
 Branch Penalty: The number of cycles lost due to a pipeline stall caused by a branch.
 Instruction 4: In this example, Instruction 4 is a conditional branch.
 Pipeline Stall: After Instruction 4, the pipeline stalls for three cycles (cycles 5, 6, and 7) while
the branch condition is evaluated and the target address is determined.
 Instruction 15: If the branch is taken, Instruction 15 is fetched and executed. If the branch is
not taken, Instructions 5, 6, and 7 are discarded.
 Branch Prediction: Modern CPUs often use branch prediction techniques to try to predict
whether a branch will be taken or not, which can help reduce the impact of branch penalties.

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An Alternative Pipeline Depiction:-

Part (a): No branches

 This diagram shows the ideal operation of the pipeline without any branches.
 Each instruction moves through the pipeline stages (FI, DI, CO, FO, EI, WO) in
consecutive cycles.
 The pipeline is fully utilized, with instructions being executed in every cycle.

Part (b): With conditional branch

 This diagram shows the impact of a conditional branch on the pipeline.

 The branch is assumed to occur after Instruction 4.
 The pipeline stalls for three cycles (cycles 5, 6, and 7) while the branch condition is
evaluated and the target address is determined.
 If the branch is taken, Instruction 15 is fetched and executed. If the branch is not taken,
Instructions 5, 6, and 7 are discarded.

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Six-Stage CPU Instruction Pipeline :-

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 Fetch (FI):

 The processor fetches the next instruction from memory.

 This instruction is placed into a dedicated register.

 Decode (DI):

 The fetched instruction is decoded to determine its operation and the operands involved.
 The processor identifies the type of instruction (e.g., arithmetic, logical, load, store) and
locates the necessary data.

 Calculate Operands (CO):

 If the instruction requires operands from memory, their addresses are calculated.
 This involves determining the base address and offset based on the instruction's
addressing mode.

 Fetch Operands (FO):

 The operands are fetched from memory and stored in registers.

 These registers hold the data that the instruction will operate on.

 Execute (EI):

 The actual operation specified by the instruction is performed.

 The processor executes the arithmetic, logical, or other operation using the operands in
the registers.

 Write Operands (WO):

 If the instruction modifies data, the result is written back to memory.

 The updated value is stored in the designated memory location.

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Superscalar Organization Compared to Ordinary Scalar Organization :-

Scalar Organization:

 A single instruction is issued and executed per cycle.

 It has a single set of registers and functional units for both integer and floating-point
operations.
 The pipeline is typically designed for a single instruction stream.

Superscalar Organization:

 Multiple instructions can be issued and executed in parallel per cycle.

 It has multiple sets of registers and functional units for both integer and floating-point
operations.
 The pipeline is designed to handle multiple instruction streams.

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Superscalar Vs Super pipelined :-

Comparison of Pipeline Architectures

Simple 4-stage pipeline:

 Basic pipeline with four stages: Fetch, Decode, Execute, Write.

 Each instruction must pass through each stage sequentially.
 No overlap between stages.

Superpipelined:

 Divides each stage into multiple substages.

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  Allows multiple instructions to be in different stages of execution simultaneously.
 Improves performance but can be more complex to implement.

Superscalar:

 Allows multiple instructions to be executed in parallel, even if they are not consecutive.
 Uses multiple execution units to perform different operations simultaneously.
 More complex and expensive to design and build than superpipelined processors.

Comparison:

 Performance: Superscalar generally offers the highest performance, followed by

Superpipelined and Simple 4-stage pipeline.
 Complexity: Superscalar is the most complex, followed by Superpipelined and Simple 4-
stage pipeline.
 Cost: Superscalar is the most expensive, followed by Superpipelined and Simple 4-stage
pipeline.

Limitations
 True Data Dependency: One instruction needs the result of a previous instruction.
 Procedural Dependency: Execution depends on the outcome of a previous instruction
(e.g., branch).
 Resource Conflicts: Multiple instructions compete for the same resource.
 Output Dependency: Two instructions write to the same location.
 Antidependency: An instruction reads before a previous instruction writes.

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 No Dependency: When instructions can be executed without waiting for the results of
previous instructions, they can proceed through the pipeline without any stalls. This is the ideal
scenario.
 Data Dependency: When an instruction (e.g., i1) needs the result of a previous instruction
(e.g., i0) before it can complete, a data dependency occurs. This causes a stall in the pipeline
until i0 finishes and its result is available to i1.
 Procedural Dependency: This arises when the execution of an instruction (e.g., il/branch)
depends on the outcome of a previous instruction (e.g., i0). If the branch is taken, the pipeline
may need to discard instructions that were fetched based on the wrong assumption. This can lead
to a pipeline flush and a delay in instruction execution.
 Resource Conflict: When multiple instructions (e.g., i0 and i1) require the same resource
(e.g., a functional unit), a resource conflict occurs. This can cause a stall as the instructions
compete for the resource.

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DESIGN ISSUES :-
Instruction-Level Parallelism and Machine Parallelism

Instruction-level parallelism exists when instructions in a sequence are independent and thus can be
executed in parallel by overlapping.

1 2
ILP is achieved in Ex1
Machine parallelism is a measure of the ability of the processor to take advantage of instruction-level
parallelism. Machine parallelism is determined by the number of instructions that can be fetched and
executed at the same time (the number of parallel pipelines) and by the speed and sophistication of the
mechanisms that the processor uses to find independent instructions.

Questions of Unit 4

1 ) Explain & brief processer Organization.

2 ) Explain & brief internal Structure.
3 ) Explain register organization & its Types.
4 ) List & Explain user visible register.
5 ) Draw & explain fetch cycle.
6 ) Explain pipeline 6 stages.
7 ) Explain instruction pipeline with conditional branch

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