TDA8954

2 × 210 W class-D power amplifier

1. General description
The TDA8954 is a stereo or mono high-efficiency Class D audio power amplifier in a
single IC featuring low power dissipation. It is designed to deliver up to 2 × 210 W into a
4 Ω load in a stereo Single-Ended (SE) application, or 1 × 420 W into an 8 Ω load in a
mono Bridge-Tied Load (BTL) application.

It combines the benefits of Class D efficiency (≈93 % into a 4 Ω load) with audiophile
sound quality comparable to that associated with Class AB amplification.

The amplifier operates over a wide supply voltage range from ±12.5 V to ±42.5 V and
features low quiescent current consumption.

The TDA8954 is supplied with two diagnostic pins for monitoring the status of Thermal
Fold Back (TFB), Over Current Protection (OCP) and other protection circuits.

2. Features
„ High output power in typical applications:
‹ SE 2 × 210 W, RL = 4 Ω (VDD = 41 V; VSS = −41 V)
‹ SE 2 × 235 W, RL = 3 Ω (VDD = 39 V; VSS = −39 V)
‹ SE 2 × 150 W, RL = 6 Ω (VDD = 41 V; VSS = −41 V)
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‹ BTL 1 × 420 W, RL = 8 Ω (VDD = 41 V; VSS = −41 V)

„ Symmetrical operating supply voltage range from ±12.5 V to ±42.5 V
„ Stereo full differential inputs, can be used as stereo SE or mono BTL amplifier
„ Low noise
„ Smooth pop noise-free start-up and switch off
„ 2-pin diagnostics for protection circuits
„ Fixed frequency internal or external clock
„ High efficiency ≈93 %
„ Zero dead time switching
„ Low quiescent current
„ Advanced protection strategy: voltage protection and output current limiting
„ Thermal FoldBack (TFB) with disable functionality
„ Fixed gain of 30 dB in SE and 36 dB in BTL applications
„ Fully short-circuit proof across load
„ BD modulation in BTL configuration
„ Clock protection
 TDA8954
2 × 210 W class-D power amplifier

3. Applications

„ DVD „ Home Theater In A Box (HTIAB) system

„ Mini and micro receiver „ High-power speaker system
„ Subwoofers „ Public Address (PA) system

4. Quick reference data

Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
General
VDD positive supply voltage Operating mode [1] 12.5 41 42.5 V
VSS negative supply voltage Operating mode [2] −12.5 −41 −42.5 V
Vth(ovp) overvoltage protection Standby, Mute modes; VDD − VSS 85 - 90 V
threshold voltage
IDD(tot) total positive supply current the sum of the currents through pins VDDA, - 50 60 mA
VDDP1 and VDDP2
Operating mode; no load; no filter; no RC-snubber
network connected;
ISS(tot) total negative supply current the sum of the currents through pins VSSA, VSSP1 - 65 75 mA
and VSSP2
Operating mode; no load; no filter; no RC-snubber
network connected; www.DataSheet.net/

Stereo single-ended configuration

Po output power Tj = 85 °C; LLC = 15 μH; CLC = 680 nF (see
Figure 13)
THD + N = 10 %; RL = 4 Ω; VDD = 41 V; [3] - 210 - W
VSS = −41 V
THD + N = 10 %; RL = 4 Ω; VDD = 35 V; - 150 - W
VSS = −35 V
Mono bridge-tied load configuration
Po output power Tj = 85 °C; LLC = 22 μH; CLC = 680 nF (see [3] - 420 - W
Figure 13); RL = 8 Ω; THD + N = 10 %; VDD = 41 V;
VSS = −41 V

[1] VDD is the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] VSS is the supply voltage on pins VSSP1, VSSP2 and VSSA.
[3] Output power is measured indirectly; based on RDSon measurement; see Section 14.3.

5. Ordering information
Table 2. Ordering information
Type number Package
Name Description Version
TDA8954J DBS23P plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1
TDA8954TH HSOP24 plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3

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 TDA8954
2 × 210 W class-D power amplifier

6. Block diagram

VDDA DIAG1 STABI PROT VDDP2 VDDP1

3 (20) 10 (4) 18 (12) 13 (7) 23 (16) 14 (8)

15 (9)
BOOT1
9 (3)
IN1M DRIVER
INPUT PWM
SWITCH1 HIGH
8 (2) STAGE MODULATOR CONTROL 16 (10)
IN1P AND OUT1
HANDSHAKE
DRIVER
mute
11 (5) LOW
OSCREF
STABI
VSSP1
7 (1)
OSC
TEMPERATURE SENSOR TDA8954TH
6 (23) OSCILLATOR MANAGER (TDA8954J) VDDP2
CURRENT PROTECTION
MODE MODE
VOLTAGE PROTECTION
22 (15)
BOOT2
2 (19)
SGND
mute DRIVER
CONTROL HIGH
5 (22) SWITCH2 21 (14)
AND OUT2
IN2P
INPUT PWM HANDSHAKE
DRIVER
4 (21) STAGE MODULATOR
IN2M LOW

1 (18) 12 (6) 24 (-) 19 (17) 17 (11) 20 (13)

VSSA DIAG2 VSSA n.c. VSSP1 VSSP2 010aaa556

Pin numbers in brackets refer to type number TDA8954J. www.DataSheet.net/

Fig 1. Block diagram

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2 × 210 W class-D power amplifier

7. Pinning information

7.1 Pinning

OSC 1
IN1P 2
IN1M 3
DIAG1 4
OSCREF 5
DIAG2 6
PROT 7
VDDP1 8
BOOT1 9
OUT1 10
VSSP1 11
VSSA 24 1 VSSA STABI 12 TDA8954J
VDDP2 23 2 SGND VSSP2 13
BOOT2 22 3 VDDA OUT2 14
OUT2 21 4 IN2M BOOT2 15
VSSP2 20 5 IN2P VDDP2 16
n.c. 19 6 MODE n.c. 17
TDA8954TH
STABI 18 7 OSC VSSA 18
VSSP1 17 8 IN1P SGND 19
OUT1 16 9 IN1M www.DataSheet.net/
VDDA 20
BOOT1 15 10 DIAG1 IN2M 21
VDDP1 14 11 OSCREF IN2P 22
PROT 13 12 DIAG2 MODE 23

010aaa557 010aaa558

Fig 2. Pin configuration TDA8954TH Fig 3. Pin configuration TDA8954J

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 TDA8954
2 × 210 W class-D power amplifier

7.2 Pin description

Table 3. Pin description
Symbol Pin Description
TDA8954TH TDA8954J
VSSA 1 18 negative analog supply voltage
SGND 2 19 signal ground
VDDA 3 20 positive analog supply voltage
IN2M 4 21 channel 2 negative audio input
IN2P 5 22 channel 2 positive audio input
MODE 6 23 mode selection input: Standby, Mute or Operating
mode
OSC 7 1 oscillator frequency adjustment or tracking input
IN1P 8 2 channel 1 positive audio input
IN1M 9 3 channel 1 negative audio input
DIAG1 10 4 diagnostic output 1 (open drain; TFB)
OSCREF 11 5 reference for OSC pin
DIAG2 12 6 diagnostic output 2 (open drain; protection functions)
PROT 13 7 decoupling capacitor for protection (OCP)
VDDP1 14 8 channel 1 positive power supply voltage
BOOT1 15 9 channel 1 bootstrap capacitor
OUT1 16 10 channel 1 PWM output
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VSSP1 17 11 channel 1 negative power supply voltage

STABI 18 12 decoupling of internal stabilizer for logic supply
n.c. 19 17 not connected
VSSP2 20 13 channel 2 negative power supply voltage
OUT2 21 14 channel 2 PWM output
BOOT2 22 15 channel 2 bootstrap capacitor
VDDP2 23 16 channel 2 positive power supply voltage
VSSA 24 - negative analog supply voltage

8. Functional description

8.1 General
The TDA8954 is a two-channel audio power amplifier that uses Class D technology.

For each channel, the audio input signal is converted into a digital Pulse Width Modulation
(PWM) signal using an analog input stage and a PWM modulator; see Figure 1. To drive
the output power transistors, the digital PWM signal is fed to a control and handshake
block and to high- and low-side driver circuits. This level-shifts the low-power digital PWM
signal from a logic level to a high-power PWM signal switching between the main supply
lines.

A second-order low-pass filter converts the PWM signal to an analog audio signal that can
be used to drive a loudspeaker.

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 TDA8954
2 × 210 W class-D power amplifier

The TDA8954 single-chip Class D amplifier contains high-power switches, drivers, timing
and handshaking between the power switches, along with some control logic. To ensure
maximum system robustness, an advanced protection strategy has been implemented to
provide overvoltage, overtemperature and overcurrent protection.

Each of the two audio channels contains a PWM modulator, an analog feedback loop and
a differential input stage. The TDA8954 also contains circuits common to both channels
such as the oscillator, all reference sources, the mode interface and a digital timing
manager.

The two independent amplifier channels feature high output power, high efficiency, low
distortion and low quiescent currents. They can be connected in the following
configurations:

• Stereo Single-Ended (SE)

• Mono Bridge-Tied Load (BTL)
The amplifier system can be switched to one of three operating modes using pin MODE:

• Standby mode: featuring very low quiescent current

• Mute mode: the amplifier is operational but the audio signal at the output is
suppressed by disabling the voltage-to-current (VI) converter input stages
• Operating mode: the amplifier is fully operational, de-muted and can deliver an output
signal

A slowly rising voltage should be applied (e.g. via an RC network) to pin MODE to ensure
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pop noise-free start-up. The bias-current setting of the (VI converter) input stages is
related to the voltage on the MODE pin.

In Mute mode, the bias-current setting of the VI converters is zero (VI converters are
disabled). In Operating mode, the bias current is at a maximum. The time constant
required to apply the DC output offset voltage gradually between Mute and Operating
mode levels can be generated using an RC network connected to pin MODE. An example
of a circuit for driving the MODE pin, optimized for optimal pop noise performance, is
shown in Figure 4. If the capacitor was omitted, the very short switching time constant
could result in audible pop noises being generated at start-up (depending on the DC
output offset voltage and loudspeaker used).

+5 V

5.6 kΩ
470 Ω MODE

TDA8954
5.6 kΩ
10 μF

mute/ S1 standby/ S2
operating operating
SGND

010aaa588

Fig 4. Example of mode selection circuit

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2 × 210 W class-D power amplifier

The smooth transition between Mute and Operating modes causes a gradual increase in
the DC offset output voltage, which becomes inaudible (no pop noise because the DC
offset voltage rises smoothly). An overview of the start-up timing is provided in Figure 5.
For proper switch-off, the MODE pin should be forced LOW at least 100 ms before the
supply lines (VDD and VSS) drop below 12.5 V.

audio output

(1)
modulated PWM
VMODE
50 %
duty cycle

operating
> 4.2 V

mute
2.2 V < VMODE < 3 V

standby
0 V (SGND)
100 ms > 350 ms time
50 ms

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audio output

(1)
modulated PWM
VMODE
50 %
duty cycle

operating
> 4.2 V

mute
2.2 V < VMODE < 3 V

standby
0 V (SGND)
100 ms > 350 ms time
50 ms 001aah657

(1) First 1⁄4 pulse down.

Upper diagram: When switching from Standby to Mute, there is a delay of approximately 100 ms
before the output starts switching. The audio signal will become available once VMODE reaches the
Operating mode level (see Table 9), but not earlier than 150 ms after switching to Mute. To start-up
pop noise-free, it is recommended that the time constant applied to pin MODE be at least 350 ms
for the transition between Mute and Operating modes.
Lower diagram: When switching directly from Standby to Operating mode, there is a delay of
100 ms before the outputs start switching. The audio signal becomes available after a second
delay of 50 ms. To start-up pop noise-free, it is recommended that the time-constant applied to pin
MODE be at least 500 ms for the transition between Standby and Operating modes.
Fig 5. Timing on mode selection input pin MODE

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 TDA8954
2 × 210 W class-D power amplifier

8.2 Diagnostics
The TDA8954 provides two diagnostic signals on pins DIAG1 and DIAG2. Both are
open-drain outputs that can be pulled up via a resistor (10 kΩ recommended) to a
maximum of 5 V relative to the GND pin. The maximum input current on these pins is
1 mA.

Pin DIAG1 provides a TFB warning signal. Pin DIAG2 can be used to monitor the OCP
status and the protection status (whether one of the protection circuits has switched off the
amplifier).

Details of the timing of these signals can be found in Section 8.4.1.1 and Section 8.4.2;
see also Table 5.

8.3 Pulse-width modulation frequency

The amplifier output signal is a PWM signal with a typical carrier frequency of between
250 kHz and 450 kHz. A second-order LC demodulation filter on the output converts the
PWM signal into an analog audio signal. The carrier frequency, fOSC, is determined by an
external resistor, ROSC, connected between pins OSC and OSCREF. The optimal carrier
frequency setting is between 250 kHz and 450 kHz.

The carrier frequency is set to 335 kHz by connecting an external 30 kΩ resistor between
pins OSC and OSCREF (see Figure 6).

010aaa596
500
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fOSC
(kHz)

400

300

200
20 25 30 35 40 45
ROSC (kΩ)

Fig 6. Carrier frequency as a function of ROSC

If two or more Class D amplifiers are used in the same audio application, an external clock
circuit must be used to synchronize all amplifiers (see Section 14.4). This will ensure that
they operate at the same switching frequency, thus avoiding beat tones (if the switching
frequencies are different, audible interference known as ‘beat tones’ can be generated).

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 TDA8954
2 × 210 W class-D power amplifier

8.4 Protection
The following protection circuits are incorporated into the TDA8954:

• Thermal protection:
– Thermal FoldBack (TFB)
– OverTemperature Protection (OTP)
• OverCurrent Protection (OCP)
• Window Protection (WP)
• Supply voltage protection:
– UnderVoltage Protection (UVP)
– OverVoltage Protection (OVP)
– UnBalance Protection (UBP)
• Clock Protection (CP)
How the device reacts to a fault condition depends on which protection circuit has been
activated.

8.4.1 Thermal protection

The TDA8954 employes an advanced thermal protection strategy. A TFB function
gradually reduces the output power within a defined temperature range. If the temperature
continues to rise, OTP is activated to shut the device down completely.

8.4.1.1 Thermal FoldBack (TFB) www.DataSheet.net/

If the junction temperature (Tj) exceeds the thermal foldback activation threshold
(Tact(th_fold)), the gain is gradually reduced. This reduces the output signal amplitude and
the power dissipation, eventually stabilizing the temperature.

When Tj reaches Tact(warn)th_fold, the TFB warning signal is activated (pin DIAG1 goes
LOW). Thermal foldback is activated if the temperature rises to Tact(th_fold) (see Figure 7).

The TFB warning signal is reset when the temperature drops below Trst(warn)th_fold again
(see Figure 8).

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 TDA8954
2 × 210 W class-D power amplifier

VLOAD

Thermal foldback activated

VDIAG1

T
Tact(th_fold)
Tact(warn)th_fold

t 010aaa561

Fig 7. TFB and TFB warning

Thermal foldback is active when:

Tact(th_fold) < Tj < Tact(th_prot)

The value of Tact(th_fold) for the TDA8954 is approximately 145 °C; see Table 9 for more
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details. The gain will be reduced by at least 6 dB (to Thg(th_fold)) before the temperature
reaches Tact(th_prot) (see Figure 8).

TFB can be disabled by applying the appropriate voltage on pin MODE (see Table 9), in
which case the dissipation will not be limited by TFB. The junction temperature may then
rise as high as the OTP threshold, when the amplifier will be shut down (see
Section 8.4.1.2). The amplifier will start up again once it has cooled down. This introduces
audio holes.

The TFB warning signal is not disabled when the TFB is disabled via the MODE pin. This
allows a temperature control function in the application to monitor the junction
temperature and, if necessary, to reduce the level of the audio signal transmitted to the
amplifier.

8.4.1.2 OverTemperature Protection (OTP)

If TFB fails to stabilize the temperature and the junction temperature continues to rise, the
amplifier will shut down as soon as the temperature reaches the thermal protection
activation threshold, Tact(th_prot). The amplifier will resume switching approximately 100 ms
after the temperature drops below Tact(th_prot).

The thermal behavior is illustrated in Figure 8.

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2 × 210 W class-D power amplifier

VPULL-UP

VDIAG1

30

Gain 24
[dB]

Trst(warn)th_fold
Tact(warn)th_fold
Tact(th_fold)

Thg(th_fold)
Tact(th_prot)
T

1 2 3
010aaa562

(1) Duty cycle of PWM output modulated according to the audio input signal.
(2) Duty cycle of PWM output reduced due to TFB.
(3) Amplifier is switched off due to OTP.
Fig 8. Behavior of TFB, OTP and signal on pin DIAG1
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8.4.2 OverCurrent Protection (OCP)

In order to guarantee the robustness of the TDA8954, the maximum output current
delivered at the output stages is limited. OCP is built in for each output power switch.

OCP is activated when the current in one of the power transistors exceeds the OCP
threshold (IORM = 12 A) due, for example, to a short-circuit to a supply line or across the
load.

The TDA8954 amplifier distinguishes between low-ohmic short-circuit conditions and

other overcurrent conditions such as a dynamic impedance drop at the loudspeaker. The
impedance threshold (Zth) depends on the supply voltage.

How the amplifier reacts to a short circuit depends on the short-circuit impedance:

• Short-circuit impedance > Zth: the amplifier limits the maximum output current to IORM
but the amplifier does not shut down the PWM outputs. Effectively, this results in a
clipped output signal across the load (behavior very similar to voltage clipping).
• Short-circuit impedance < Zth: the amplifier limits the maximum output current to IORM
and at the same time discharges the capacitor on pin PROT. When CPROT is fully
discharged, the amplifier shuts down completely and an internal timer is started.

The value of the protection capacitor (CPROT) connected to pin PROT can be between
10 pF and 220 pF (typically 47 pF). While OCP is activated, an internal current source is
enabled that will discharge CPROT.

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 TDA8954
2 × 210 W class-D power amplifier

When OCP is activated, the active power transistor is turned off and the other power
transistor is turned on to reduce the current (CPROT is partially discharged). Normal
operation is resumed at the next switching cycle (CPROT is recharged). CPROT is partially
discharge each time OCP is activated during a switching cycle. If the fault condition that
caused OCP to be activated persists long enough to fully discharge CPROT, the amplifier
will switch off completely and a restart sequence will be initiated.

After a fixed period of 100 ms, the amplifier will attempt to switch on again, but will fail if
the output current still exceeds the OCP threshold. The amplifier will continue trying to
switch on every 100 ms. The average power dissipation will be low in this situation
because the duty cycle is short.

Switching the amplifier on and off in this way will generate unwanted ‘audio holes’. This
can be avoided by increasing the value of CPROT (up to 220 pF) to delay amplifier
switch-off. CPROT will also prevent the amplifier switching off due to transient
frequency-dependent impedance drops at the speakers.

The amplifier will switch on, and remain in Operating mode, once the overcurrent
condition has been removed. OCP ensures the TDA8954 amplifier is fully protected
against short-circuit conditions while avoiding audio holes.

Table 4. Current limiting behavior during low output impedance conditions at different
values of CPROT
Type VDD/VSS (V) VI (mV, p-p) f (Hz) CPROT PWM output stops
(pF) Short Short Short
(Zth = 0 Ω) (Zth = 0.5 Ω) (Zth = 1 Ω)
TDA8954 +41/−41 500 20 10 yes[1] yes[1] yes[1]
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1000 10 yes no no
20 15 yes[1] yes[1] yes[1]
1000 15 yes no no
1000 220 no no no

[1] OVP can be triggered by supply pumping; see Section 14.6.

Pin DIAG2 pin can be used to:

1. Monitor the OCP status - a pulsed signal at the switching frequency is generated on
DIAG2 when current limiting has been enabled.
2. Monitor the protection status - a pulsed signal with a minimum width of typically
100 ms will be generated on pin DIAG2 to indicate that the amplifier has been
switched off by one of the protection circuits (see Table 5). This signal is also
generated at start-up before the amplifier output starts switching.

When a short circuit occurs between the load and the supply voltage, the current will
increase rapidly to IORM, when current limiting will be activated. A pulsed signal at the
switching frequency will be transmitted on pin DIAG2 to indicate that OCP is active. If the
short circuit condition persists long enough to cause the OCP circuit to shut down the
amplifier, the DIAG2 signal will be transmitted continuously until the amplifier has started
up again and has commenced switching (see Figure 9).

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 TDA8954
2 × 210 W class-D power amplifier

switch off amplifier

VDIAG2

IMAX

current short
limiting circuit
protection

IOUT
short to VDDP applied

t 010aaa563

Fig 9. Current limiting

8.4.3 Window Protection (WP)

Window Protection (WP) checks the conditions at the output terminals of the power stage
and is activated:

• During the start-up sequence, when the TDA8954 is switching from Standby to Mute.
Start-up will be interrupted if a short-circuit is detected between one of the output
terminals and one of the supply pins. The TDA8954 will wait until the short-circuit to
the supply lines has been removed before resuming start-up. The short circuit will not
generate large currents because the short-circuit check is carried out before the
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power stages are enabled.

• When the amplifier is shut down completely because the OCP circuit has detected a
short circuit to one of the supply lines.
WP will be activated when the amplifier attempts to restart after 100 ms (see
Section 8.4.2). The amplifier will not start-up again until the short circuit to the supply
lines has been removed.

8.4.4 Supply voltage protection

If the supply voltage drops below the minimum supply voltage threshold, Vth(uvp), the UVP
circuit will be activated and the system will shut down. Once the supply voltage rises
above Vth(uvp) again, the system will restart after a delay of 100 ms.

If the supply voltage exceeds the maximum supply voltage threshold, Vth(ovp), the OVP
circuit will be activated and the power stages will be shut down. When the supply voltage
drops below Vth(ovp) again, the system will restart after a delay of 100 ms.

An additional UnBalance Protection (UBP) circuit compares the positive analog supply
voltage (on pin VDDA) with the negative analog supply voltage (on pin VSSA) and is
triggered if the voltage difference exceeds a factor of two (VDDA > 2 × |VSSA| OR |VSSA| >
2 × VDDA). When the supply voltage difference drops below the unbalance threshold,
Vth(ubp), the system restarts after 100 ms.

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 TDA8954
2 × 210 W class-D power amplifier

8.4.5 Clock protection (CP)

The clock signal can be provided by an external oscillator connected to pin OSC (see
Section 14.4). When this signal is lost, or the clock frequency is too low, the amplifier will
be switched off and will remain off until the clock signal has been restored.

8.4.6 Overview of protection functions

An overview of all protection circuits and their respective effects on the output signal is
provided in Table 5.

Table 5. Overview of TDA8954 protection circuits

Protection Complete Restart Restart PROT pin DIAG1 pin DIAG2 pin
name shutdown directly after active active active
100 ms
TFB[1] N N N N Y[2] N
OTP Y N Y N N Y
OCP Y[3] N[3] Y[3] Y N Y
WP N[4] Y N N N Y
UVP Y N Y N N Y
OVP Y N Y N N Y
UBP Y N Y N N Y
CP Y N Y[5] N N Y

[1] Amplifier gain depends on the junction temperature.

[2] TFB warning signal on pin DIAG1 is activated before TFB is enabled.
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[3] The amplifier shuts down completely only if the short-circuit impedance is below the impedance threshold
(Zth; see Section 8.4.2). In all other cases, current limiting results in a clipped output signal.
[4] Fault condition detected during any Standby-to-Mute transition or during a restart after OCP has been
activated (short-circuit to one of the supply lines).
[5] As soon as the clock is present.

8.5 Differential audio inputs

The audio inputs are fully differential ensuring a high common mode rejection ratio and
maximum flexibility in the application.

• Stereo operation: to avoid supply pumping effects and to minimize peak currents in
the power supply, the output stages should be configured in anti-phase. To avoid
acoustical phase differences, the speakers should also be connected in anti-phase.
• Mono BTL operation: the inputs must be connected in anti-parallel. The output of one
channel is inverted and the speaker load is connected between the two outputs of the
TDA8954. In practice (because of the OCP threshold) the maximum output power in
the BTL configuration can be boosted to twice the maximum output power available in
the single-ended configuration.
The input configuration for a mono BTL application is illustrated in Figure 10.

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2 × 210 W class-D power amplifier

OUT1
IN1P
IN1M

Vin SGND
IN2P
IN2M OUT2

power stage
mbl466

Fig 10. Input configuration for mono BTL application

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2 × 210 W class-D power amplifier

9. Internal circuitry
Table 6. Internal circuitry
Pin Symbol Equivalent circuit[1]
TDA8954TH TDA8954J
7 1 OSC
VDD
150 μA

open: external clock

closed: internal clock

7 (1)

VSS 010aaa589

11 5 OSCREF
2Ω
11 (5) VSS
010aaa590

10 4 DIAG1
10, 12
12 6 DIAG2 (4, 6)
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SGND
010aaa591

13 7 PROT
50 μA

current limiting

13 (7)

OCP

28 μA 1.5 mA

VSS
010aaa592

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2 × 210 W class-D power amplifier

Table 6. Internal circuitry …continued

Pin Symbol Equivalent circuit[1]
TDA8954TH TDA8954J
4 21 IN2M
5, 8 2 kΩ
5 22 IN2P (22, 2)
8 2 IN1P
50 kΩ
9 3 IN1M

SGND SGND

50 kΩ

4, 9 2 kΩ
(21, 3)
010aaa593

6 23 MODE
6 (23)

50 kΩ

SGND

standby

gain (mute on)

TFB on
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VSS
010aaa594

1 18 VSSA
14, 23
2 19 SGND (8, 16)
3 20 VDDA 3 (20) 15, 22
(9, 15)
14 8 VDDP1
15 9 BOOT1
16, 21
16 10 OUT1 (10, 14)
2 (19)
17 11 VSSP1 18 (12)

18 12 STABI
10 V
20 13 VSSP2
17, 20
1 (18)
21 14 OUT2 (11, 13)
010aaa595
22 15 BOOT2
23 16 VDDP2

[1] Pin numbers in brackets are for the TDA8954J

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2 × 210 W class-D power amplifier

10. Limiting values

Table 7. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
ΔV voltage difference VDD − VSS; Standby, Mute modes - 90 V
IORM repetitive peak output current maximum output current limiting; one 12 - A
channel driven
Tstg storage temperature −55 +150 °C
Tamb ambient temperature −40 +85 °C
Tj junction temperature - 150 °C
VOSC voltage on pin OSC relative to VSSA 0 SGND + 6 V
Vpu pull-up voltage on pins DIAG1 and DIAG2; see Figure 13 0 5 V
VI input voltage referenced to SGND; on pins IN1P, IN1M, −5 +5 V
IN2P and IN2M
VPROT voltage on pin PROT referenced to voltage on pin VSSA 0 12 V
VMODE voltage on pin MODE referenced to SGND 0 8 V
II input current on pins DIAG1 and DIAG2 0 1 mA
VESD electrostatic discharge voltage Human Body Model (HBM) −2000 +2000 V
Charged Device Model (CDM) −500 +500 V
VPWM(p-p) peak-to-peak PWM voltage on pins OUT1 and OUT2 - 120 V

11. Thermal characteristics

www.DataSheet.net/

Table 8. Thermal characteristics

Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient in free air 40 K/W
Rth(j-c) thermal resistance from junction to case 0.9 K/W

12. Static characteristics

Table 9. Static characteristics
VDD = 41 V; VSS = −41 V; fosc = 335 kHz; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supply
VDD positive supply voltage Operating mode [1] 12.5 41 42.5 V
VSS negative supply voltage Operating mode [2] −12.5 −41 −42.5 V
Vth(ovp) overvoltage protection Standby, Mute modes; VDD − VSS 85 - 90 V
threshold voltage
Vth(uvp) undervoltage protection VDD − VSS 20 - 25 V
threshold voltage
Vth(ubp) unbalance protection threshold [3] - 33 - %
voltage

18
 TDA8954
2 × 210 W class-D power amplifier

Table 9. Static characteristics …continued

VDD = 41 V; VSS = −41 V; fosc = 335 kHz; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
IDD(tot) total positive supply current the sum of the currents through pins - 50 60 mA
VDDA, VDDP1 and VDDP2
Operating mode; no load; no filter;
no RC-snubber network connected;
ISS(tot) total negative supply current the sum of the currents through pins - 65 75 mA
VSSA, VSSP1 and VSSP2
Operating mode; no load; no filter;
no RC-snubber network connected;
Istb standby current - 490 650 μA
Mode select input; pin MODE
VMODE voltage on pin MODE referenced to SGND [4] 0 - 8 V
Standby mode [4][5] 0 - 0.8 V
Mute mode [4][5] 2.2 - 3.0 V
Operating mode [4][5] 4.2 - 5.5 V
Operating mode without TFB [4][5] 6.6 - 8
II input current VI = 5.5 V - 110 150 μA
Audio inputs; pins IN1M, IN1P, IN2P and IN2M
VI input voltage DC input [4] - 0 - V
Amplifier outputs; pins OUT1 and OUT2
VO(offset) output offset voltage SE; Mute mode www.DataSheet.net/
−37 - +37 mV
SE; Operating mode [6] −150 - +150 mV
BTL; Mute mode −30 - +30 mV
BTL; Operating mode [6] −210 - +210 mV
Stabilizer output; pin STABI
VO(STABI) output voltage on pin STABI Mute and Operating modes; with 9.5 10 10.5 V
respect to VSSA
Temperature protection
Trst(warn)th_fold thermal foldback warning - 138 - °C
reset temperature
Tact(warn)th_fold thermal foldback warning - 139 - °C
activation temperature
Tact(th_fold) thermal foldback activation VMODE < 5.5 V - 145 - °C
temperature
Thg(th_fold) thermal foldback half gain VMODE < 5.5 V; gain = 24 dB - 153 - °C
temperature
Tact(th_prot) thermal protection activation - 154 - °C
temperature

[1] VDD is the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] VSS is the supply voltage on pins VSSP1, VSSP2 and VSSA.
[3] Unbalance protection activated when VDDA > 2 × |VSSA| OR |VSSA| > 2 × VDDA.
[4] With respect to SGND (0 V).
[5] The transition between Standby and Mute modes has hysteresis, while the slope of the transition between Mute and Operating modes is
determined by the time-constant of the RC network on pin MODE; see Figure 11.

19
 TDA8954
2 × 210 W class-D power amplifier

[6] DC output offset voltage is gradually applied to the output during the transition between Mute and Operating modes. The slope caused
by any DC output offset is determined by the time-constant of the RC network on pin MODE.

Slope is directly related to the time constant

of the RC network on the MODE pin
VO(offset)(on)

Standby

no TFB
Mute

On

On
VO[V]
VO(offset)(mute)

0 0.8 2.2 3.0 4.2 5.5 6.6 8

VMODE[V] 010aaa564

Fig 11. Behavior of mode selection pin MODE

13. Dynamic characteristics

13.1 Switching characteristics

Table 10. Dynamic characteristics
VDD = 41 V; VSS = −41 V; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Internal oscillator
www.DataSheet.net/

fosc(typ) typical oscillator frequency ROSC = 30.0 kΩ 290 335 365 kHz
fosc oscillator frequency 250 - 450 kHz
External oscillator input or frequency tracking; pin OSC
VOSC voltage on pin OSC HIGH-level SGND + 4.5 SGND + 5 SGND + 6 V
Vtrip trip voltage - SGND + 2.5 - V
ftrack tracking frequency [1] 500 - 1000 kHz
Zi input impedance 1 - - MΩ
Ci input capacitance - - 15 pF
tr(i) input rise time from SGND + 0 V to [2] - - 100 ns
SGND + 5 V

[1] When using an external oscillator, the frequency ftrack (500 kHz minimum, 1000 kHz maximum) will result in a PWM frequency fosc
(250 kHz minimum, 500 kHz maximum) due to the internal clock divider; see Section 8.3.
[2] When tr(i) > 100 ns, the output noise floor will increase.

20
 TDA8954
2 × 210 W class-D power amplifier

13.2 Stereo SE configuration characteristics

Table 11. Dynamic characteristics
VDD = 41 V; VSS = −41 V; RL = 4 Ω; fi = 1 kHz; fosc = 335 kHz; RsL < 0.1 Ω[1]; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Po output power L = 15 μH; CLC = 680 nF; Tj = 85 °C [2]

THD = 0.5 %; RL = 4 Ω - 160 - W

THD = 10 %; RL = 4 Ω - 210 - W
THD = 10 %; RL = 3 Ω; VP = ±39 V [3] - 235 - W
THD total harmonic distortion Po = 1 W; fi = 1 kHz [4] - 0.03 0.1 %
Po = 1 W; fi = 6 kHz [4] - 0.05 - %
Gv(cl) closed-loop voltage gain 29 30 31 dB
SVRR supply voltage ripple rejection between pins VDDPn and SGND
Operating mode; fi = 100 Hz [5] - 90 - dB
Operating mode; fi = 1 kHz [5] - 70 - dB
Mute mode; fi = 100 Hz [5] - 75 - dB
Standby mode; fi = 100 Hz [5] - 120 - dB
between pins VSSPn and SGND
Operating mode; fi = 100 Hz [5] - 80 - dB
Operating mode; fi = 1 kHz [5] - 60 - dB
Mute mode; fi = 100 Hz [5] - 80 - dB
Standby mode; fi = 100 Hz [5] - 115 - dB
www.DataSheet.net/

Zi input impedance between an input pin and SGND 45 56 - kΩ

Vn(o) output noise voltage Operating mode; inputs shorted [6] - 160 - μV
Mute mode [7] - 85 - μV
αcs channel separation [8] - 70 - dB
|ΔGv| voltage gain difference - - 1 dB
αmute mute attenuation fi = 1 kHz; Vi = 2 V (RMS) [9] - 75 - dB
CMRR common mode rejection ratio Vi(CM) = 1 V (RMS) - 75 - dB
ηpo output power efficiency SE, RL = 4 Ω - 93 - %
SE, RL = 3 Ω - 90 - %
BTL, RL = 8 Ω - 93 - %
RDSon(hs) high-side drain-source on-state resistance [10] - 110 - mΩ
RDSon(ls) low-side drain-source on-state resistance [10] - 105 - mΩ

[1] RsL is the series resistance of the low-pass LC filter inductor used in the application.
[2] Output power is measured indirectly; based on RDSon measurement; see Section 14.3.
[3] One channel driven at maximum output power; the other channel driven at one eight maximum output power.
[4] THD measured between 22 Hz and 20 kHz, using AES17 20 kHz brick wall filter.
[5] Vripple = Vripple(max) = 2 V (p-p); measured independently between VDDPn and SGND and between VSSPn and SGND.
[6] 22 Hz to 20 kHz, using AES17 20 kHz brick wall filter.
[7] 22 Hz to 20 kHz, using AES17 20 kHz brick wall filter.
[8] Po = 1 W; fi = 1 kHz.
[9] Vi = Vi(max) = 1 V (RMS); fi = 1 kHz.
[10] Leads and bond wires included.

21
 TDA8954
2 × 210 W class-D power amplifier

13.3 Mono BTL application characteristics

Table 12. Dynamic characteristics
VDD = 41 V; VSS = −41 V; RL = 8 Ω; fi = 1 kHz; fosc = 335 kHz; RsL < 0.1 Ω [1]; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Po output power Tj = 85 °C; LLC = 15 μH; CLC = 680 nF [2]

(see Figure 13)

THD = 0.5 %; RL = 8 Ω - 330 - W
THD = 10 %; RL = 8 Ω - 420 - W
THD total harmonic distortion Po = 1 W; fi = 1 kHz [3] - 0.03 0.1 %
Po = 1 W; fi = 6 kHz [3] - 0.05 - %
Gv(cl) closed-loop voltage gain - 36 - dB
SVRR supply voltage ripple rejection between pin VDDPn and SGND
Operating mode; fi = 100 Hz [5] - 80 - dB
Operating mode; fi = 1 kHz [5] - 80 - dB
Mute mode; fi = 100 Hz [5] - 95 - dB
Standby mode; fi = 100 Hz [5] - 120 - dB
between pin VSSPn and SGND
Operating mode; fi = 100 Hz [5] - 75 - dB
Operating mode; fi = 1 kHz [5] - 75 - dB
Mute mode; fi = 100 Hz [5] - 90 - dB
Standby mode; fi = 100 Hz [5] - 130 - dB
Zi input impedance measured between one of the input 45 56 - kΩ
www.DataSheet.net/

pins and SGND

Vn(o) output noise voltage Operating mode; inputs shorted [5] - 190 - μV
Mute mode [6] - 45 - μV
αmute mute attenuation fi = 1 kHz; Vi = 2 V (RMS) [7] - 75 - dB
CMRR common mode rejection ratio Vi(CM) = 1 V (RMS) - 75 - dB

[1] RsL is the series resistance of the low-pass LC filter inductor used in the application.
[2] Output power is measured indirectly; based on RDSon measurement; see Section 14.3.
[3] THD measured between 22 Hz and 20 kHz, using AES17 20 kHz brick wall filter.
[4] Vripple = Vripple(max) = 2 V (p-p).
[5] 22 Hz to 20 kHz, using an AES17 20 kHz brick wall filter; low noise due to BD modulation.
[6] 22 Hz to 20 kHz, using an AES17 20 kHz brick wall filter.
[7] Vi = Vi(max) = 1 V (RMS); fi = 1 kHz.

22
 TDA8954
2 × 210 W class-D power amplifier

14. Application information

14.1 Mono BTL application

When using the power amplifier in a mono BTL application, the inputs of the two channels
must be connected in anti-parallel and the phase of one of the inputs must be inverted;
see Figure 10. In principle, the loudspeaker can be connected between the outputs of the
two single-ended demodulation filters.

14.2 Pin MODE

To ensure a pop noise-free start-up, an RC time-constant must be applied to pin MODE.
The bias-current setting of the VI converter input is directly related to the voltage on pin
MODE. In turn the bias-current setting of the VI converters is directly related to the DC
output offset voltage. A slow dV/dt on pin MODE results in a slow dV/dt for the DC output
offset voltage, ensuring a pop noise-free transition between Mute and Operating modes. A
time-constant of 500 ms is sufficient to guarantee pop noise-free start-up; see Figure 4,
Figure 5 and Figure 11 for more information.

14.3 Estimating the output power

14.3.1 Single-Ended (SE)

Maximum output power:

RL 2
- × 0.5 ( V DD – V SS ) × ( 1 – t w ( min ) × 0.5 f osc )
------------------------------------------------------- www.DataSheet.net/

R L + R DSon ( hs ) + R s ( L )
P o ( 0.5% ) = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- (1)
2R L

Maximum output current is internally limited to 12 A:

0.5 ( V DD – V SS ) × ( 1 – t w ( min ) × 0.5f osc )

I o ( peak ) = --------------------------------------------------------------------------------------------------- (2)
R L + R DSon ( hs ) + R s ( L )

Where:

• Po(0.5 %): output power at the onset of clipping

• RL: load impedance
• RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent)
• Rs(L): series impedance of the filter coil
• tw(min): minimum pulse width (typical 150 ns; temperature dependent)
• fosc: oscillator frequency

Remark: Note that Io(peak) should be less than 12 A (Section 8.4.2). Io(peak) is the sum of
the current through the load and the ripple current. The value of the ripple current is
dependent on the coil inductance and the voltage drop across the coil.

23
 TDA8954
2 × 210 W class-D power amplifier

14.3.2 Bridge-Tied Load (BTL)

Maximum output power:

RL 2
- × ( V DD – V SS ) × ( 1 – t w ( min ) × 0.5f osc )
------------------------------------------------------------------
R L + R DSon ( hs ) + R DSon ( ls )
P o ( 0.5% ) = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- (3)
2R L

Maximum output current internally limited to 12 A:

( V DD – V SS ) × ( 1 – t w ( min ) × 0.5f osc )

I o ( peak ) = ---------------------------------------------------------------------------------------------- (4)
R L + ( R DSon ( hs ) + R DSon ( ls ) ) + 2R s ( L )

Where:

• Po(0.5 %): output power at the onset of clipping

• RL: load impedance
• RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent)
• RDSon(ls): low-side RDSon of power stage output DMOS (temperature dependent)
• Rs(L): series impedance of the filter coil
• tw(min): minimum pulse width (typical 150 ns, temperature dependent)
• fosc: oscillator frequency

Remark: Note that Io(peak) should be less than 12 A; see Section 8.4.2. Io(peak) is the sum
of the current through the load and the ripple current. The value of the ripple current is
www.DataSheet.net/

dependent on the coil inductance and the voltage drop across the coil.

14.4 External clock

To ensure duty cycle-independent operation, the external clock frequency is divided by
two internally. The external clock frequency is therefore twice the internal clock frequency
(typically 2 × 335 kHz = 670 kHz).

If several Class D amplifiers are used in a single application, it is recommended that all
the devices run at the same switching frequency. This can be achieved by connecting the
OSC pins together and feeding them from an external oscillator. When using an external
oscillator, it is necessary to force pin OSC to a DC level above SGND. This disables the
internal oscillator and causes the PWM to switch at half the external clock frequency.

The internal oscillator requires an external resistor ROSC, connected between pin OSC
and pin OSCREF. ROSC must be removed when using an external oscillator.

The noise generated by the internal oscillator is supply voltage dependent. An external
low-noise oscillator is recommended for low-noise applications running at high supply
voltages.

14.5 Heatsink requirements

An external heatsink must be connected to the TDA8954.

Equation 5 defines the relationship between maximum power dissipation before activation
of TFB and total thermal resistance from junction to ambient.

24
 TDA8954
2 × 210 W class-D power amplifier

T j – T amb
Rth (j – a ) = ---------------------- (5)
P

Power dissipation (P) is determined by the efficiency of the TDA8954.

mbl469
30

P
(W)
(1)

20

(2)

10
(3)
(4)

(5)

0
0 20 40 60 80 100
Tamb (°C)

(1) Rth(j-a) = 5 K/W.

(2) Rth(j-a) = 10 K/W.
(3) Rth(j-a) = 15 K/W.
(4) Rth(j-a) = 20 K/W. www.DataSheet.net/

(5) Rth(j-a) = 35 K/W.

Fig 12. Derating curves for power dissipation as a function of maximum ambient
temperature

In the following example, a heatsink calculation is made for an 4 Ω SE application with a

±30 V supply:

The audio signal has a crest factor of 10 (the ratio between peak power and average
power (20 dB); this means that the average output power is 1⁄10 of the peak power.
Thus, the peak RMS output power level is the 0.5 % THD level, i.e. 92.5 W per channel.
The average power is then 1⁄10 × 92.5 W = 9.25 W per channel.
The dissipated power at an output power of 9.25 W is approximately 9.5 W.

When the maximum expected ambient temperature is 50 °C, the total Rth(j-a) becomes
( 148 – 50 )
------------------------- = 10.3 K/W
9.5

Rth(j-a) = Rth(j-c) + Rth(c-h) + Rth(h-a)

Rth(j-c) (thermal resistance from junction to case) = 0.9 K/W

Rth(c-h) (thermal resistance from case to heatsink) = 0.5 K/W to 1 K/W (dependent on
mounting)

So the thermal resistance between heatsink and ambient temperature is:

25
 TDA8954
2 × 210 W class-D power amplifier

Rth(h-a) (thermal resistance from heatsink to ambient) = 10.3 − (0.9 + 1) = 8.4 K/W

The derating curves for power dissipation (for several Rth(j-a) values) are illustrated in
Figure 12. A maximum junction temperature Tj = 150 °C is taken into account. The
maximum allowable power dissipation for a given heatsink size can be derived, or the
required heatsink size can be determined, at a required power dissipation level; see
Figure 12.

14.6 Pumping effects

In a typical stereo single-ended configuration, the TDA8954 is supplied by a symmetrical
supply voltage (e.g. VDD = +41 V and VSS = −41 V). When the amplifier is used in an SE
configuration, a ‘pumping effect’ can occur. During one switching interval, energy is taken
from one supply (e.g. VDD), while a part of that energy is returned to the other supply line
(e.g. VSS) and vice versa. When the voltage supply source cannot sink energy, the voltage
across the output capacitors of that voltage supply source increases and the supply
voltage is pumped to higher levels. The voltage increase caused by the pumping effect
depends on:

• Speaker impedance
• Supply voltage
• Audio signal frequency
• Value of supply line decoupling capacitors
• Source and sink currents of other channels

Pumping effects should be minimized to prevent the malfunctioning of the audio amplifier
www.DataSheet.net/

and/or the voltage supply source. Amplifier malfunction due to the pumping effect can
trigger UVP, OVP or UBP.

The most effective way to avoid pumping effects is to connect the TDA8954 in a mono
full-bridge configuration. In the case of stereo single-ended applications, it is advised to
connect the inputs in anti-phase (see Section 8.5 on page 14). The power supply can also
be adapted; for example, by increasing the values of the supply line decoupling
capacitors.

14.7 Application schematic

Notes on the application schematic:

• Connect a solid ground plane around the switching amplifier to avoid emissions
• Place 100 nF capacitors as close as possible to the TDA8954 power supply pins
• Connect the heatsink to the ground plane or to VSSPn using a 100 nF capacitor
• Use a thermally conductive, electrically non-conductive, Sil-Pad between the
TDA8954 heat spreader and the external heatsink
• The heat spreader of the TDA8954 is internally connected to VSSA
• Use differential inputs for the most effective system level audio performance with
unbalanced signal sources. In case of hum due to floating inputs, connect the
shielding or source ground to the amplifier ground.

26
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+5 V

RVDDA
VDD 5.6 kΩ
10 Ω 470 Ω
VDD VDD mode control
CVDDP3 SINGLE-ENDED
470 μF
+5 V OUTPUT FILTER VALUES
CVP LOAD LLC CLC
SGND 22 μF
470 kΩ 5.6 kΩ 10 μF 470 kΩ
CVSSP3 3 Ω to 6 Ω 15 μH 680 nF
470 μF
4 Ω to 8 Ω 22 μH 470 nF
VSS VSS
10 kΩ 10 kΩ
RVSSA mute/ T1 standby/ T2
VSS operating HFE > 80 operating HFE > 80
10 Ω
SGND

VPU VPU mode VDD VSS

control
CVDDP1 CVP1 CVSSP1
RPU1 RPU2 ROSC VDD
10 kΩ 10 kΩ 30 kΩ CSN1
100 nF 100 nF 100 nF
OSCREF

RSN1 220 pF

VDDP1

VSSP1
DIAG1

DIAG2

MODE
OSC
10 Ω CSN2
220 pF
CIN1 4 5 6 1 23 8 11
+ IN1P
2 VSS
LLC1
470 nF OUT1
IN1 10

www.DataSheet.net/
CIN2
− IN1M CBO1 RZO1
+
3 BOOT1 22 Ω
470 nF 9 CLC1
15 nF CZO1 −
SGND 100 nF
19 TDA8954J
CBO2
CIN3
BOOT2
15
− IN2P
22 15 nF
470 nF LLC2

2 × 210 W class-D power amplifier

IN2 OUT2
14
CIN4
+ IN2M
21 VDD RZO2
470 nF 22 Ω −
CSN3 CLC2
20 18 12 7 17 16 13 RSN2 220 pF CZO2 +
VDDA

VSSA

STABI

PROT

n.c.

VDDP2

VSSP2

100 nF
10 Ω CSN4
220 pF
CVDDA CVSSA CVDDP2 CVP2 CVSSP2

TDA8954
CPROT(1) VSS
CSTAB
220 nF 220 nF 100 nF 100 nF 100 nF
470 nF

VDD VSS VSS VSS VDD VSS 010aaa559

(1) The value of CPROT can be in the range 10 pF to 220 pF (see Section 8.4.2)
27

Fig 13. Typical application diagram

 TDA8954
2 × 210 W class-D power amplifier

14.8 Curves measured in reference design (demo board TDA8954J)

010aaa598
10

THD+N
(%)

(1)
(2)
10−1

(3)
10−2
10−2 10−1 1 10 102 103
Po (W)

VDD = 41 V, VSS = −41 V, fosc = 325 kHz (external 650 kHz oscillator), 2 × 4 Ω SE configuration.
(1) fi = 1 kHz.
(2) fi = 6 kHz.
(3) fi = 100 Hz.
Fig 14. THD + N as a function of output power, SE configuration with 2 × 4 Ω load

www.DataSheet.net/

010aaa599
10

THD+N
(%)

(1)
(2)
10−1

(3)
10−2
10−2 10−1 1 10 102 103
Po (W)

VDD = 39 V, VSS = −39, fosc = 325 kHz (external 650 kHz oscillator), 2 × 3 Ω SE configuration.
(1) fi = 1 kHz.
(2) fi = 6 kHz.
(3) fi = 100 Hz.
Fig 15. THD + N as a function of output power, SE configuration with 2 × 3 Ω load

28
 TDA8954
2 × 210 W class-D power amplifier

010aaa600
10

THD+N
(%)

(1) (2)
10−1

(3)
10−2
10−2 10−1 1 10 102 103
Po (W)

VDD = 41 V, VSS = −41, fosc = 325 kHz (external 650 kHz oscillator), 1 × 8 Ω BTL configuration.
(1) fi = 1 kHz.
(2) fi = 6 kHz.
(3) fi = 100 Hz.
Fig 16. THD + N as a function of output power, BTL configuration with 1 × 8 Ω load

010aaa655
1 www.DataSheet.net/

THD+N
(%)

10−1 (3)

(1)

(2)

10−2
10 102 103 104 105
fi (Hz)

VDD = 41 V, VSS = −41, fosc = 325 kHz (external 650 kHz oscillator), 2 × 4 Ω SE configuration.
(1) Po = 1 W.
(2) Po = 10 W.
(3) Po = 100 W.
Fig 17. THD + N as a function of frequency, SE configuration with 2 × 4 Ω load

29
 TDA8954
2 × 210 W class-D power amplifier

010aaa656
1

THD+N
(%)

(3)
10−1
(1)

(2)

10−2
10 102 103 104 105
fi (Hz)

VDD = 39 V, VSS = −39, fosc = 325 kHz (external 650 kHz oscillator), 2 × 3 Ω SE configuration.
(1) Po = 1 W.
(2) Po = 10 W.
(3) Po = 100 W.
Fig 18. THD + N as a function of frequency, SE configuration with 2 × 3 Ω load

010aaa629
1 www.DataSheet.net/

THD+N
(%)

(3)
10−1

(1)

(2)

10−2
10 102 103 104 105
fi (Hz)

VDD = 41 V, VSS = −41, fosc = 325 kHz (external 650 kHz oscillator), 1 × 8 Ω BTL configuration.
(1) Po = 1 W.
(2) Po = 10 W.
(3) Po = 100 W.
Fig 19. THD + N as a function of frequency, BTL configuration with 1 × 8 Ω load

30
 TDA8954
2 × 210 W class-D power amplifier

010aaa604
0
Chan sep
(dB)
−20

−40

−60

−80

−100
10 102 103 104 105
fi (Hz

VDD = 41 V, VSS = −41, fosc = 325 kHz (external 650 kHz oscillator), 2 × 4 Ω SE configuration.
Channel B S/N (dB).
Fig 20. Channel separation as a function of frequency, SE configuration with 2 × 4 Ω load

010aaa605
0
Chan sep
(dB) www.DataSheet.net/

−20

−40

−60

−80

−100
10 102 103 104 105
fi (Hz)

VDD = 39 V, VSS = −39, fosc = 325 kHz (external 650 kHz oscillator), 2 × 3 Ω SE configuration.
Channel B S/N (dB).
Fig 21. Channel separation as a function of frequency, SE configuration with 2 × 3 Ω load

31
 TDA8954
2 × 210 W class-D power amplifier

010aaa606
60

PD
(W)

(1)
40

(2)

20
(3)

0
10−2 10−1 1 10 102 103
Po (W/channel)

fi = 1 kHz; fosc = 325 kHz (external 650 kHz oscillator).

(1) 2 × 3 Ω SE configuration; VDD = 39 V; VSS = −39 V.
(2) 2 × 4 Ω SE configuration; VDD = 41 V; VSS = −41 V.
(3) 2 × 6 Ω SE configuration; VDD = 41 V; VSS = −41 V.
Fig 22. Power dissipation as a function of output power per channel, SE configuration

010aaa607
100 www.DataSheet.net/

(1) (2)
Efficiency
(%) (3)
80

60

40

20

0
0 50 100 150 200 250
Po (W/channel)

fi = 1 kHz, fosc = 325 kHz (external 650 kHz oscillator).

(1) 2 × 6 Ω SE configuration; VDD = 41 V; VSS = −41 V.
(2) 2 × 4 Ω SE configuration; VDD = 41 V; VSS = −41 V.
(3) 2 × 3 Ω SE configuration; VDD = 39 V; VSS = −39 V.
Fig 23. Efficiency as a function of output power per channel, SE configuration

32
 TDA8954
2 × 210 W class-D power amplifier

010aaa608
250
(1)
Po
(W)
(2)
200
(3)

(4)
150

100

50

0
12.5 17.5 22.5 27.5 32.5 37.5 42.5
Vp ±(V)

Infinite heat sink used.

fi = 1 kHz, fosc = 325 kHz (external 650 kHz oscillator).
(1) THD + N = 10 %, 2 × 3 Ω.
(2) THD + N = 10 %, 2 × 4 Ω
(1) THD + N = 0.5 %, 2 × 3 Ω
(2) THD + N = 0.5 %, 2 × 4 Ω.
Fig 24. Output power as a function of supply voltage, SE configuration
www.DataSheet.net/

010aaa609
500
Po
(W)
400 (1)

300
(2)

200

100

0
12.5 17.5 22.5 27.5 32.5 37.5 42.5
Vp ±(V)

Infinite heat sink used.

fi = 1 kHz, fosc = 325 kHz (external 650 kHz oscillator).
(1) THD + N = 10 %, 8 Ω.
(2) THD + N = 0.5 %, 8 Ω.
Fig 25. Output power as a function of supply voltage, BTL configuration

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 TDA8954
2 × 210 W class-D power amplifier

010aaa610
40

Gain (1)
(dB)
(2)
30
(3)

20

10

0
10 102 103 104 105
Fi (Hz)

VDD = 30 V, VSS = −30 V, fosc = 325 kHz (external 650 kHz oscillator), Vi = 100 mV, Ci = 330 pF.
(1) 1 × 8 Ω configuration; LLC = 15 μH, CLC = 680 nF, VDD = 41 V, VSS = −41 V.
(2) 2 × 4 Ω configuration; LLC = 15 μH, CLC = 680 nF, VDD = 41 V, VSS = −41 V.
(3) 2 × 3 Ω configuration; LLC = 15 μH, CLC = 680 nF, VDD = 39 V; VSS = −39 V.
Fig 26. Frequency response

010aaa611
0 www.DataSheet.net/

SVRR
(dB)
−20

−40

−60

(1)
−80
(2)

−100
10 102 103 104 105
Fi (Hz)

Ripple on VDD, short on input pins.

VDD = 41 V, VSS = −41 V, Vripple = 2 V (p-p), 2 × 4 Ω SE configuration.
(1) Operating mode.
(2) Mute mode.
Fig 27. SVRR as a function of ripple frequency, ripple on VDD

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 TDA8954
2 × 210 W class-D power amplifier

010aaa612
0
SVRR
(dB)
−20

−40

−60

(1)
−80
(2)

−100
10 102 103 104 105
Fi (Hz)

Ripple on VSS, short on input pins.

VDD = 41 V, VSS = −41 V, Vripple = 2 V (p-p), 2 × 4 Ω SE configuration.
(1) Mute mode.
(2) Operating mode.
Fig 28. SVRR as a function of ripple frequency, ripple on VSS

010aaa657
10 www.DataSheet.net/

VOut
(V)
1

10−1

10−2

10−3

10−4

10−5
0 2 4 6 8
VMODE (V)

VDD = 41 V, VSS = −41 V, Vi = 100 mV, fosc = 325 kHz (external 650 kHz oscillator), fi = 1 kHz
(1) Mode voltage down.
(2) Mode voltage up.
Fig 29. Output voltage as a function of mode voltage

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 TDA8954
2 × 210 W class-D power amplifier

010aaa614
0
Mute
Suppression
(dB)
−20

−40

−60

−80

−100
10 102 103 104 105
Fi (Hz)

VDD = 39 V, VSS = −39 V, fosc = 325 kHz (external 650 kHz oscillator), Vi = 2 V (RMS).
2 × 3 Ω SE configuration; channel A suppression (dB)
Fig 30. Mute attenuation as a function of frequency

010aaa615
0
Mute
Suppression
(dB) www.DataSheet.net/

−20

−40

−60

−80

−100
10 102 103 104 105
Fi (Hz)

VDD = 41 V, VSS = −41 V, fosc = 325 kHz (external 650 kHz oscillator), Vi = 2 V (RMS).
2 × 4 Ω SE configuration; channel A suppression (dB)
Fig 31. Mute attenuation as a function of frequency

36
 TDA8954
2 × 210 W class-D power amplifier

010aaa630
300

Po
(W) (3)

200

(1)

100
OTP activated

(2)

(4)
0
0 100 200 300 400 500 600
T (sec)

VDD = 39 V, VSS = −39 V, fosc = 325 kHz (external 650 kHz oscillator), 2 × 3 Ω SE configuration.
Heat sink: Fisher SK495/50; Sil-Pad: 1500ST. Condition: 30 minutes pre-heated in Mute
(1) Maximum output power; TFB on.
(2) Maximum output power / 8; TFB on.
(3) Maximum output power; TFB off.
(4) Maximum output power / 8; TFB off.
Fig 32. Output power as a function of time, 2 × 3 Ω
www.DataSheet.net/

010aaa631
250
Po
(W) (3)
200
(1)

150

100

50
(4)

(2)

0
0 100 200 300 400 500 600
T (sec)

VDD = 41 V, VSS = −41 V, fosc = 325 kHz (external 650 kHz oscillator), 2 × 4 Ω SE configuration
Heat sink: Fisher SK495/50; Sil-Pad: 1500ST. Condition: 30 minutes pre-heated in Mute
(1) Maximum output power; TFB on.
(2) Maximum output power / 8; TFB on.
(3) Maximum output power; TFB off.
(4) Maximum output power / 8; TFB off.
Fig 33. Output power as a function of time, 2 × 4 Ω

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 TDA8954
2 × 210 W class-D power amplifier

15. Package outline

DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1

non-concave
x Dh

Eh

view B: mounting base side

A2
d A5
β A4

B E2

j
E
www.DataSheet.net/
E1

L2
L1 L3

L Q c v M
1 23

e1 m e2
Z w M
bp
e

0 5 10 mm
scale

DIMENSIONS (mm are the original dimensions)

UNIT A 2 A4 A5 bp c D (1) d D h E (1) e e1 e2 Eh E1 E2 j L L1 L2 L3 m Q v w x β Z (1)

4.6 1.15 1.65 0.75 0.55 30.4 28.0 12.2 6 10.15 6.2 1.85 3.6 14 10.7 2.4 2.1 1.43
mm 12 2.54 1.27 5.08 4.3 0.6 0.25 0.03 45°
4.3 0.85 1.35 0.60 0.35 29.9 27.5 11.8 9.85 5.8 1.65 2.8 13 9.9 1.6 1.8 0.78

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

98-02-20
SOT411-1
02-04-24

Fig 34. Package outline SOT411-1 (DBS23P)

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 TDA8954
2 × 210 W class-D power amplifier

HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3

E A
D
x X

y E2

HE v M A

D1
D2

1 12

pin 1 index

A2 A
E1 (A3)
A4
www.DataSheet.net/

θ
Lp

detail X

24 13

Z w M
e bp

0 5 10 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A2 A3 A4(1) bp c D(2) D1 D2 E(2) E1 E2 e HE Lp Q v w x y Z θ
max.
3.5 +0.08 0.53 0.32 16.0 13.0 1.1 11.1 6.2 2.9 14.5 1.1 1.7 2.7 8°
mm 3.5 0.35 1 0.25 0.25 0.03 0.07
3.2 −0.04 0.40 0.23 15.8 12.6 0.9 10.9 5.8 2.5 13.9 0.8 1.5 2.2 0°

Notes
1. Limits per individual lead.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

03-02-18
SOT566-3
03-07-23

Fig 35. Package outline SOT566-3 (HSOP24)

39
 TDA8954
2 × 210 W class-D power amplifier

16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.

16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
www.DataSheet.net/

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities

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 TDA8954
2 × 210 W class-D power amplifier

16.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 36) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 13 and 14

Table 13. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 ≥ 350
< 2.5 235 220
≥ 2.5 220 220

Table 14. Lead-free process (from J-STD-020C)

www.DataSheet.net/

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)
< 350 350 to 2 000 > 2 000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 36.

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 TDA8954
2 × 210 W class-D power amplifier

maximum peak temperature

temperature = MSL limit, damage level

minimum peak temperature

= minimum soldering temperature

peak
temperature

time
001aac844

MSL: Moisture Sensitivity Level

Fig 36. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

17. Soldering of through-hole mount packages

www.DataSheet.net/

17.1 Introduction to soldering through-hole mount packages

This text gives a very brief insight into wave, dip and manual soldering.

Wave soldering is the preferred method for mounting of through-hole mount IC packages
on a printed-circuit board.

17.2 Soldering by dipping or by solder wave

Driven by legislation and environmental forces the worldwide use of lead-free solder
pastes is increasing. Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb
or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.

17.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.

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2 × 210 W class-D power amplifier

17.4 Package related soldering information

Table 15. Suitability of through-hole mount IC packages for dipping and wave soldering
Package Soldering method
Dipping Wave
CPGA, HCPGA - suitable
DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable[1]
PMFP[2] - not suitable

[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit
board.
[2] For PMFP packages hot bar soldering or manual soldering is suitable.

43