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Indira College of Engineering

and Management

LAB MANUAL
SECOND YEAR

DIGITAL
ELECTRONICS
LABORATORY

Subject Code: 210248

2024 - 25
DEL Lab Manual 2019 Course
INDIRA COLLEGE OF ENGINEERING AND MANAGEMENT

INDEX Batch : -
Page Date of Signature of
Sr.No Title
No Conduction Staff
To Realize Full Adder/ Subtractor using a)
1 Basic Gates and b) Universal Gates
Design and implement Code Converters-
Binary to Gray and BCD to Excess-3
2
Design and Realization of BCD Adder using
3
4-bit Binary Adder (IC 7483).
Realization of Boolean Expression for suitable
combination logic using MUX 74151 /74153,
4
DMUX 74154/74138

To Verify the truth table of two bit


5
comparators using logic gates.
Design and Implement Parity Generator and
6 checker using EX-OR.
Design and Realization: Flip Flop
7 conversion
Design of 2 bit and 3 bit Ripple Counter using
8 MS JK flip-flop
Design of Synchronous 3 bit Up and Down
9 Counter using MSJK Flip Flop / D Flip Flop
Realization of Mod -N counter using (Decade
10 Counter IC 7490 ) .
Design and implement Sequence detector using
11 MS JK flip-flop.
12 Study of Shift Registers ( SISO,SIPO, PISO,
PIPO)
Digital Electronics Lab (Pattern 2019)

EXPERIMENT NO.1
TITLE: FULL ADDER & FULL SUBTRACTOR

 Title: To Realize Full Adder/ Subtractor using a) Basic Gates and b) Universal Gates
 Objective:

1. To study combinational circuit like full adder and full substractor.

2. To know about basic gates.


3. To know about universal gates.

 Problem Statement:
To realize full adder and full substractor using

a) Basic gates
b) Universal gates

 Hardware & software requirements:


Digital Trainer Kit, IC7432, IC 7408, IC 7404, IC 7400 Patch Cord, + 5V Power
Supply

Theory:
1. Combinational circuit.
2. Half Adder.
3. Half Substractor.
4. Full Adder.
5. Full substracter.

` 1. Combinational Circuit:- Realization steps for combinational circuit

a) Truth Table
b) K-Map.
c) MSI Circuits.
Digital Electronics Lab (Pattern 2019)

2. Half Adder:-

 Truth Table:-

Input Output
X Y Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

 K-Map:-

 Logic Diagram:-
Digital Electronics Lab (Pattern 2019)

3. Half Substractor :-

 Truth Table:-

Input Output
A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

 K-Map:-

 Logic Gates:-
Digital Electronics Lab (Pattern 2019)

4. Full Adder:-

 Truth Table:-

X Y Z Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

 K-Map:-

 Logic Gates:-
Digital Electronics Lab (Pattern 2019)

5. Full Substractor:-

 Truth Table:-

X Y Z Difference Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

 K-Map:-
Digital Electronics Lab (Pattern 2019)

 Logic Gates:-

Implement Full adder using NAND gates.

Outcomes:-

Successfully designed and implemented Adder and Subtractor.


Digital Electronics Lab (Pattern 2019)

EXPERIMENT NO. 2
TITLE: CODE CONVERTER

 Title: Code Converter


 Objective: To learn various code & its conversion
 Problem Statement: Design and implement Code Converters-
i) Binary to Gray
ii) BCD to Excess-3

 Hardware & software requirements:


Digital Trainer Kit, IC 7404, IC 7432, IC 7408, IC 7486, Patch Cord, + 5V Power Supply

Theory:
There is a wide variety of binary codes used in digital systems. Some of these codes are binary- coded-
decimal (BCD), Excess-3, Gray, octal, hexadecimal, etc. Often it is required to convert from one code to
another. For example the input to a digital system may be in natural BCD and output may be 7-segment
LEDs. The digital system used may be capable of processing the data in straight binary format. Therefore,
the data has to be converted from one type of code to another type for different purpose. The various code
converters can be designed using gates.

1) Binary Code:

It is straight binary code. The binary number system (with base 2) represents values using two symbols,
typically 0 and 1.Computers call these bits as either off (0) or on (1). The binary code are made up of only
zeros and ones, and used in computers to stand for letters and digits. It is used to represent numbers using
natural or straight binary form.

It is a weighted code since a weight is assigned to every position. Various arithmetic operations can be
performed in this form. Binary code is weighted and sequential code.

2) Gray Code:

It is a modified binary code in which a decimal number is represented in binary form in such a way that
each Gray- Code number differs from the preceding and the succeeding number by a single bit. (E.g. for
decimal number 5 the equivalent Gray code is 0111 and for 6 it is 0101. These two codes differ by only one
bit position i. e. third from the left.) Whereas by using binary code there is a possibility of change of
Digital Electronics Lab (Pattern 2019)

all bits if we move from one number to other in sequence (e.g. binary code for 7 is 0111 and for 8 it is
1000). Therefore it is more useful to use Gray code in some applications than binary code.

The Gray code is a nonweighted code i.e. there are no specific weights assigned to the bit positions.

Like binary numbers, the Gray code can have any no. of bits. It is also known as reflected code.

Applications:

1. Important feature of Gray code is it exhibits only a single bit change from one code word to the next in
sequence. This property is important in many applications such as Shaft encoders where error susceptibility
increases with number of bit changes between adjacent numbers in sequence.

2. It is sometimes convenient to use the Gray code to represent the digital data converted from the analog
data (Outputs of ADC).

3. Gray codes are used in angle-measuring devices in preference to straight forward binary encoding.

4. Gray codes are widely used in K-map

The disadvantage of Gray code is that it is not good for arithmetic operation

Binary to Gray Conversion

In this conversion, the input straight binary number can easily be converted to its Gray code equivalent.

1. Record the most significant bit as it is.


2. EX-OR this bit to the next position bit, record the resultant bit.
3. Record successive EX-ORed bits until completed.
4. Convert 0011 binary to Gray.

0 0 1 1 Binary code

+ + +

0 0 1 0 Gray code
(MSB) (LSB)

Fig. 1 Binary to Gray Conversion


Digital Electronics Lab (Pattern 2019)

Gray to Binary Conversion

1. The Gray code can be converted to binary by a reverse process.


2. Record the most significant bit as it is.
3. EX-OR binary MSB to the next bit of Gray code and record the resultant bit.
4. Continue the process until the LSB is recorded.
5. Convert 1011 Gray to Binary code.

1 0 1 1 Gray code

+ + +

1 1 0 1 Binary code
(MSB) (LSB)
Fig. 2 Gray to Binary Conversion

3) BCD Code:

Binary Coded Decimal (BCD) is used to represent each of decimal digits (0 to 9) with a 4-bit binary code.
For example (23)10 is represented by 0010 0011 using BCD code rather than(10111)2 This code is also
known as 8-4-2-1 code as 8421 indicates the binary weights of four bits(23, 22, 21, 20). It is easy to convert
between BCD code numbers and the familiar decimal numbers. It is the main advantage of this code. With
four bits, sixteen numbers (0000 to 1111) can be represented, but in BCD code only 10 of these are used.
The six code combinations (1010 to 1111) are not used and are invalid.

Applications: Some early computers processed BCD numbers. Arithmetic operations can be performed
using this code. Input to a digital system may be in natural BCD and output may be 7-segment LEDs.

It is observed that more number of bits are required to code a decimal number using BCD code than using
the straight binary code. However in spite of this disadvantage it is very convenient and useful code for
input and output operations in digital systems.
Digital Electronics Lab (Pattern 2019)

4) EXCESS-3 Code:

Excess-3, also called XS3, is a non weighted code used to express decimal numbers. It can be used for the
representation of multi-digit decimal numbers as can BCD.The code for each decimal number is obtained
by adding decimal 3 and then converting it to a 4-bit binary number. For e.g. decimal 2 is coded as 0010
+ 0011 = 0101 in Excess-3 code.

This is self complementing code which means 1‘s complement of the coded number yields 9‘s
complement of the number itself. Self complementing property of this helps considerably in
performing subtraction operation in digital systems, so this code is used for certain arithmetic
operations.

BCD To Excess – 3 Code Conversions:

Convert BCD 2 i. e. 0010 to Excess – 3 codes

For converting 4 bit BCD code to Excess – 3, add 0011 i. e. decimal 3 to the respective code using rules of
binary addition.

0010 + 0011 = 0101 – Excess – 3 code for BCD 2

Excess – 3 Code To BCD Conversion:

The 4 bit Excess-3 coded digit can be converted into BCD code by subtracting decimal value 3 i.e. 0011
from 4 bit Excess-3 digit.

e.g. Convert 4-bit Excess-3 value 0101 to equivalent BCD code.

0101-0011= 0010- BCD for 2


Digital Electronics Lab (Pattern 2019)
Design:

A) Binary to Gray Code Conversion:

1) Truth Table:

Table 1 Binary to Gray Code Conversion

INPUT (BINARY CODE) OUTPUT (GRAY CODE)

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0
Digital Electronics Lab (Pattern 2019)

2) K-Map for Reduced Boolean Expressions of Each Output:

Fig. 4 K-Map for Reduced Boolean Expressions of Each Output (Gray Code)

3) Circuit Diagram:

Fig. 5 Logical Circuit Diagram for Binary to Gray Code Conversion


Digital Electronics Lab (Pattern 2019)

B) BCD to Excess-3 Code Conversion:

1) Truth Table:

Table 3 BCD to Excess-3 Code Conversion

INPUT (BCD CODE) OUTPUT (EXCESS-3 CODE)

B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x

1 1 0 0 x x x x

1 1 0 1 x x x x

1 1 1 0 x x x x

1 1 1 1 x x x x
Digital Electronics Lab (Pattern 2019)

2) K-Map for Reduced Boolean Expressions of Each Output:

Fig. 8 K-Map for Reduced Boolean Expressions Of Each Output (Excess-3 Code)
Digital Electronics Lab (Pattern 2019)
3) Circuit Diagram:

BCD TO EXCESS-3 CONVERTER

Fig.9 Logical Circuit Diagram for BCD to Excess-3 Code Conversion


Digital Electronics Lab (Pattern 2019)

Outcome:

Thus, we studied different codes and their conversions including applications.

The truth tables have been verified using IC 7486, 7432, 7408, and 7404.
Digital Electronics Lab (Pattern 2019)

EXPERIMENT NO.3
TITLE: BCD ADDER

 Title: BCD Adder


 Objective: To learn different types of adder
 Problem Statement: Design and Realization of BCD Adder using 4-bit Binary Adder (IC
7483).
 Hardware and software requirement:

Digital Trainer Kit, IC 7483,7432 7408, Patch Cord ,+ 5V Power Supply

Theory:

 BCD Adder: It is a circuit that adds two BCD digits & produces a sum of digits also in BCD.

 Rules for BCD addition:

1. Add two numbers using rules of Binary addition.

2. If the 4 bit sum is greater than 9 or if carry is generated then the sum is invalid. To correct the sum
add 0110 i.e. (6)10 to sum. If carry is generated from this addition add it to next higher order BCD
digit.

3. If the 4 bit sum is less than 9 or equal to 9 then sum is in proper form.

 The BCD addition can be explained with the help of following 3 cases -

CASE I: Sum <= 9 & carry = 0.

Add BCD digits 3 & 4

1. 0011

+ 0100

0111

Answer is valid BCD number = (7) BCD & so 0110 is not added.
Digital Electronics Lab (Pattern 2019)
CASE II: Sum > 9 & carry = 0.

Add BCD digits 6 & 5


1. 0110

+ 0101

1011
Invalid BCD (since sum > 9) so 0110 is to be added

2. 1011

+ 0110

1 0001

(1 1)BCD

Valid BCD result = (11) BCD

CASE III: Sum < = 9 & carry = 1.


Add BCD digits 9 & 9
1. 1001

+1001

10010

Invalid BCD (since Carry = 1) so 0110 is to be added


2. 1 0010
+0110

11000
(1 8)BCD
Valid BCD result = (18) BCD
Digital Electronics Lab (Pattern 2019)

Design of BCD adder :


1. 4 bit binary adder is used for initial addition. i.e. binary addition of two 4 bit numbers.(
with Cin = 0 ),
2. Logic circuit to sense if sum exceeds 9 or carry = 1, this digital circuit will produce high
output otherwise its output will be zero.
3. One more 4-bit adder to add (0110)2 in the sum is greater than 9 or carry is 1.
Digital Electronics Lab (Pattern 2019)

Truth Table:-
For design of combinational circuit for BCD adder to check invalid BCD

INPUT OUTPUT

S3 S2 S1 S0 Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1
Digital Electronics Lab (Pattern 2019)

K-map:-

For reduced Boolean expressions of output

Y= S3S2+S3S1

Circuit diagram:

For invalid BCD detection


Digital Electronics Lab (Pattern 2019)

iv) Circuit diagram for BCD adder :

Outcome:
Thus, we studied single bit BCD adder using 4 bit parallel binary adder / 4 bit full adder the observation
table has been verified have been verified using IC 7483 & some logic gates.
Digital Electronics Lab (Pattern 2019)

EXPERIMENT NO.4
TITLE: MULTIPLEXER

TITLE:
 Title: Study of IC-74LS85
Realization of Booleanasexpression
a magnitude comparator.
using 8:1 Multiplexer 74151
 Objective: To learn different techniques of designing multiplexer
 Problem Statement:
1. Verification of Functional table.
2. Verification of Sum of Product (SOP) and Product of Sum (POS) with the help of
given Boolean expression.
3. Verify the functional table using cascading of two multiplexers
4. Realization of Boolean expression using hardware reduction method for the given
equation.

 Hardware & software requirements:


Digital trainer board, IC 74151, IC 7404, IC 7432, patch cords, + 5V Power supply

Theory:
1 .What is multiplexer?
 Multiplexer is a digital switch which allows digital information from
several sources to be routed onto a single output line. Basic
multiplexer has several data inputs and a single output line.
 The selection of a particular input line is controlled by a set of
selection line.
 There are 2n input lines & n is the number of selection line whose bit
combinations determines which input is selected .It is ―Many into
One‖.
 Strobe: - It is used to enable/ disable the logic circuit OR ‗E‘ iscalled
as enable I/P which is generally active LOW. It is used for cascading
 MUX is a single pole multiple way switch.
2. Necessity of multiplexer
o In most of the electronic systems, digital data is available on more than
one lines. It is necessary to route this data over a single line.
o It select one of the many I/P at a time.
o Multiplexer improves the reliability of digital system because it
reduces the number of external wire connection.
Digital Electronics Lab (Pattern 2019)

3. Enlist significance and advantages of Multiplexer

 It doesn‘t need K-map & logic simplification.


 The IC package count is minimized.
 It simplifies the logic design.
 In designing the combinational circuit
 It reduces the complexity & cost.
 To minimize number of connections in communication system were
we need to handle thousands of connections. Ex. Telephone exchange.

4. Applications of MUX
 Data selector to select one out of many data I/P.
 In Data Acquisition system.
 In the D/A converter.

Multiplexer Tree
 It is nothing but construction of more number of line using less
number of lines.
 It is possible to expand the range of inputs for multiplexers beyond the
available Range in the integrated circuits. This can be accomplished by
interconnecting several multiplexers.

8:1 MUX:
The block diagram of 8:1 MUX & its TT is shown. It has eight data
I/P & one enable input, three select lines and one O/P.

Operating principle:
When the Strobe or Enable input is active low, we can select any one
of eight data I/P and connect to O/P.
Digital Electronics Lab (Pattern 2019)

Design:

Draw the connection diagram of multiplexer to verify the functional table.

SELECTION STROBE
LINES OUTPUTS

C B A E Y Y
X X X 1 0 1
0 0 0 0 D0 D0
0 0 1 0 D1 D1
0 1 0 0 D2 D2
0 1 1 0 D3 D3
1 0 0 0 D4 D4
1 0 1 0 D5 D5
1 1 0 0 D6 D6
1 1 1 0 D7 D7

X = don’t care condition.

Part 1: MUX as a function generator.

Convert the given Boolean expression into standard SOP / POS format if required and complete
the logic diagram design accordingly for realization of the same.
Digital Electronics Lab (Pattern 2019)
i) As an example:

Function = Sum of Product (SOP)


Y = ∑m (1, 2, 3, 4, 5, 6, 7)

SELECTION STROBE
LINES OUTPUTS

C B A Y Y
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 0
0 1 1 0 1 0
1 0 0 0 1 0
1 0 1 0 1 0
1 1 0 0 1 0
1 1 1 0 1 0

SOP realization Diagram

SOP Y = ∑m (1, 2, 3, 4, 5, 6, 7)

Solution:-Since there are 3 variable, the multiplexer have 3 select I/P should be used.
Hence one 8:1 mux should be used.
Ste p 1:-Identify the number decimal corresponding to each minterm.
Here 1,2,3,4,5,6,7
Step 2:-Connect the data input lines 1,2,3,4,5,6,7 to logic 1(+Vcc) & remaining input line
0 to logic 0(GND)
Step 3:-Connect variables A, B & C to select input.
Digital Electronics Lab (Pattern 2019)

ii) As an example
Function = Product of Sum (POS)
Y = ∏ M (0, 5, 6, 7)

SELECTION STROBE
LINES OUTPUTS

C B A Y Y
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 0
0 1 1 0 1 0
1 0 0 0 1 0
1 0 1 0 0 1
1 1 0 0 0 1
1 1 1 0 0 1

POS realization exp:


1. As there are 3 i/p so use 8:1 MUX
2. Connect the given min terms to GND and else decimal numbers to logic1(+VCC).
Digital Electronics Lab (Pattern 2019)

POS realization Diagram

POS Y = ∏ M (0, 5, 6, 7)

Outcome:

Multiplexer is used as a data selector to select one out of many data inputs.
It is used for simplification of logic design.
It is used to design combinational circuit.
Use of multiplexer minimizes no. of connect
Pin Diagram IC 74151 8:1 multiplexer
Digital Electronics Lab (Pattern 2019)
Digital Electronics Lab (Pattern 2019)

EXPERIMENT NO.5
TITLE: COMPARATOR

 TITLE: Study of IC-74LS85 as a magnitude comparator.


Title: - Comparators
 Objective: - 1 bit, 2 bit Comparator.
 Problem Statement: To Verify the truth table of two bit comparators using logic gates.
 Hardware & Software Requirement’s :

Digital Trainer Kit, Comparator IC-7485, patch cords, +5V power supply.

Theory:

Another common and very useful combinational logic circuit is that of the Digital Comparator
circuit. Digital or Binary Comparators are made up from standard AND, NOR and NOT gates that
compare the digital signals present at their input terminals and produce an output depending upon
the condition of those inputs.

For example, along with being able to add and subtract binary numbers we need to be able to
compare them and determine whether the value of input A is greater than, smaller than or equal to
the value at input B etc. The digital comparator accomplishes this using several logic gates that
operate on the principles of Boolean algebra. There are two main types of Digital Comparator
available and these are

1. Identity Comparator – an Identity Comparator is a digital comparator that has only one
output terminal for when A = B either ―HIGH‖ A = B = 1 or ―LOW‖ A = B = 0

 2. Magnitude Comparator – a Magnitude Comparator is a digital comparator which has


three output terminals, one each for equality, A = B greater than, A > B and less than A
< B.

The purpose of a Digital Comparator is to compare a set of variables or unknown numbers, for
example A (A1, A2, A3… An, etc) against that of a constant or unknown value such as B (B1, B2,
B3… Bn, etc) and produce an output condition or flag depending upon the result of the comparison.
For example, a magnitude comparator of two 1-bits, (A and B) inputs would produce the following
three output conditions when compared to each other. Which means: A is greater than B, A is
equal to B, and A is less than B
Digital Electronics Lab (Pattern 2019)

This is useful if we want to compare two variables and want to produce an output when any of the
above three conditions are achieved. For example, produce an output from a counter when a certain
count number is reached. Consider the simple 1-bit comparator below

1. 1-bit comparator

 Truth Table:-
Inputs Outputs
B A A>B A=B A<B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
 K-Map
Digital Electronics Lab (Pattern 2019)

 Logic Diagram of 1 bit Comparator

2 Bit Comparator:-

 Truth Table:-
Digital Electronics Lab (Pattern 2019)

 K-map :-

1. For A>B:

2. For A=B

3. For A<B :-
Digital Electronics Lab (Pattern 2019)

 Circuit Diagram:-
Digital Electronics Lab (Pattern 2019)

 For n bit Comparator :-

Digital comparators actually use Exclusive-NOR gates within their design for comparing their
respective pairs of bits. When we are comparing two binary or BCD values or variables against
each other, we are comparing the ―magnitude‖ of these values, a logic ―0‖ against a logic ―1‖
which is where the term Magnitude Comparator comes from.

As well as comparing individual bits, we can design larger bit comparators by cascading together
n of these and produce a n-bit comparator just as we did for the n-bit adder in the previous
tutorial. Multi-bit comparators can be constructed to compare whole binary or BCD words to
produce an output if one word is larger, equal to or less than the other.

Outcome:
Up and down counters are successfully implemented, the comparators are studied &
o/p are checked. The truth table is verified.
Digital Electronics Lab (Pattern 2019)

EXPERIMENT NO.6
TITLE: PARITY GENERATOR/CHECKER

 Title: Parity
TITLE: Study of IC-74LS85
Generator andas a magnitude
Parity Checker.comparator.
 Objective: Learn Even/Odd parity Generator/Checker using logic gates
 Problem Statement: Design & Implement Parity Generator using EX-OR
 Hardware & software requirement: Digital Trainer Kit, IC 7486 (Ex-OR), IC 7404
(NOT), IC 74180, Patch Cord ,+ 5V Power Supply

Theory:
In digital communication, the digital data is sent over the telephone lines using
different binary codes.

During the transmission, because of ―noise‖(i.e: Unwanted voltage fluctuation)


, signal 0 may become 1 or 1 may become 0 and wrong information (i.e: corrupted data ) may be
received at the destination and must be resent.

This problem of communication is overcome by using Error-detecting code.


To detect these errors, Parity Bit is usually transmitted along with the data bits.

At the receiving end, parity will be checked.

Parity: A term used to specify the number of one‘s in a digital word as odd or even.

There are two types of Parity - even and odd.

Even Parity Generator will produce a logic 1 at its output if the data word contains an odd
number of ones. If the data word contains an even number of ones then the output of the parity
generator will be low. By concatenating the Parity bit to the data word, a word will be formed
which always has an even number of ones i.e. has even parity.

Parity bit: An extra bit attached to a binary word to make the parity of resultant word even or odd.
Parity bits are extra signals which are added to a data word to enable error checking.

Definition:- 2 A check bit appended to an array of binary digit to make the sum of all binary
digits.

Parity generator: A logic circuit that generates an additional bit which when appended to a digital
word makes its parity as desired (odd or even).

o Parity generators calculate the parity of data packets and add a parity amount to them.
Digital Electronics Lab (Pattern 2019)

o Parity is used on communication links (e.g. Modem lines) and is often included in memory
systems.

Parity checker: At the receiving end a logic circuit is used to check the parity of received
information, and determines whether the error is included in the message or not.

Even bit Parity Code: The total number of ones in parity code word is even.

Odd bit Parity Code: The total number of ones in parity code word is odd.

The single parity bit code can detect the single bit error. If error is more than 1 bit, it is not
possible to detect the error.

Eg:- 1) Assume the even parity code word is sent by the transmitter is 10111, the
code word received by the receiver is 10011.

The parity of received code word is odd, it shows that one bit error is introduced over the
channel.

Eg:- 2) But if the received code word is 10001, the parity of received code is even and
shows that there is no error introduced over the channel.

Actually two bits are changed over the path.

Limitations: -

1) The one bit parity code word can detect one bit error.

2) It cannot detect the location of error and hence error cannot be corrected
Digital Electronics Lab (Pattern 2019)
A) Even Parity Generator:

1) Truth Table:

INPUT OUTPUT
B2 B1 B0 P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

2) K-Map For Reduced Boolean Expressions Of Output:

B1B0
B2 00 01 11 10
0 0 1
0 1 1

0 1 0
1 1 1

P = B2 (EX-OR) B1 (EX-OR) B0
Digital Electronics Lab (Pattern 2019)

3) Circuit Diagram:

Even parity generator:

Even parity generator O/p P = B2 (EX-OR) B1 (EX-OR) B0

B) Odd Parity Generator:


1) Truth Table:

INPUT OUTPUT
B2 B1 B0 P
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Digital Electronics Lab (Pattern 2019)

2) K-Map For Reduced Boolean Expressions Of Output:

B1B0
B2 00 01 11 10
0 0
0 1 1

0 0
1 1 1

P = B2 (EX-NOR) B1 (EX-NOR) B0

3) Circuit Diagram:
Odd parity generator:

Odd parity generator O/p P = B2 (EX-NOR) B1 (EX-NOR) B0


Digital Electronics Lab (Pattern 2019)

C) Parity checker
1) Truth Table:
2) K-Map For Reduced Boolean Expressions Of Output:
3) Circuit Diagram:
Even parity detector:

Parity checker O/p: PEC = P (EX- NOR) B2 (EX- NOR) B1 (EX- NOR) B0

Outcome: Thus, we studied parity generator / checker and their working & limitation
Digital Electronics Lab (Pattern 2019)

GROUP – B
Digital Electronics Lab (Pattern 2019)

EXPERIMENT NO.7
TITLE: FLIPFLOP CONVERSION

TITLE: Study of IC-74LS85 as a magnitude comparator.


 Title: Flip-flop.

 Objective: Conversion of Flip-flop.

 Problem Statement: Conversion from one type of flip-flop to another type of flip-flop.
.
 Hardware & Software Requirement’s :

Digital Trainer Kit, IC 7476, IC 7474, IC 7408, IC 7432 & IC 7404.patch cords, +5V power
supply.

Theory:

A Flip – flop is an electronic device which is having two stable states and a feedback path
which is used to store 1 – bit of information by using the clock signal as input. Latches are also
used to do the same task except that they do not use a clock signal. Hence to say it simply, ―Flip
– flops are clocked latches‖. They are used to store only 1 – bit of information and it can remain
in the same state until the clock signal affects the state of the input.

 General model used to convert one type of FF to other

In order to convert one flip – flop to other type of flip – flop, we should design a combinational
circuit that is connected to the actual flip – flop. Inputs to combinational circuit are same as the
inputs of the desired flip – flop. Outputs of combinational circuit are same as the inputs of the
available flip – flop. So the output of combinational circuit is connected to the input of our
available flip – flop. The pictorial representation of the same is shown below.
Digital Electronics Lab (Pattern 2019)

1. JK Flip – flop to D Flip – flop

Converting the JK flip – flop to D flip – flop, involves in connecting the Data input (D) to the JK
flip – flop through a combinational circuit. Here the Data input is connected directly to the J
input and the inverted D input (using a NOT gate) is connected to K input.

The design of the combinational circuit should be in such a way that D is its input and J & K are
its outputs. The outputs of the combinational circuit J & K are connected as inputs to the flip –
flop. QP is the present state output of the flip – flop. Q‘P is its complementary and QN is the
next state output. The truth table for converting JK flip – flop to D flip – flop is shown below.

The conversion table:-

The K – maps in order to solve for J and K in terms of D and QP are shown below.

F/F PRESENT NEXT OUTPUTS


INPUTS STATE STATE
D Qn Qn+1 J K
0 0 0 X 0
1 0 1 X 1
0 1 0 0 X
1 1 1 1 X

K – Map:-

The Boolean equation for J is J = D.


Digital Electronics Lab (Pattern 2019)

K – Map:-

The Boolean equation for K is K = D.

The Boolean equations for J and K are J = D and K = D‘. The logic diagram that represents the
implementation of D flip – flop from JK flip – flop is shown below.

The logic diagram:-

2.D Flip – flop to JK Flip – flop

When we need to convert the D flip – flop into JK flip – flop, J and K are the inputs of the
combinational circuit with D as its output. Here Data (D) is the input of actual flip – flop. The
truth table is drawn with the 8 possible combinations of the two inputs J & K along with QP. QP
and QP‘ are the present state and its complement outputs of the flip – flop.The truth table consists
of combinations of J, K and QP in order to get QN. Here QN is the next state output of the flip –
flop. The truth table also consists of D inputs that lead to QN output.

The conversion table:-


Digital Electronics Lab (Pattern 2019)

F/F INPUT PRESENT STATE NEXT STATE OUT PUT


J K Qn Qn+1 D
0 0 0 0 0
0 1 0 0 0
1 0 0 1 1
1 1 0 1 1
0 1 1 0 0
1 1 1 0 0
0 0 1 1 1
1 0 1 1 1

The K – map:-

D = JQ‘P + K‘QP.

The Boolean equation of D deduced from the above K – map is the logical representation of
implementing JK flip – flop from D flip – flop is shown below.
Digital Electronics Lab (Pattern 2019)

The logic diagram:-

Application of Flip-flop:
1. Elimination of keyboard de-bounce.
2. As a memory element.
3. In a various types of Registers.
4. In counters/timers.
5. As a delay element.

Outcomes: Successfully implemented the conversion of flip-flop


Digital Electronics Lab (Pattern 2019)

EXPERIMENT NO: 8
TITLE: RIPPLE COUNTER

 Title: Ripple Counter


 Objective: Ripple up and down counter using IC 7476
 Problem statement: To design and implement 3 bit UP, Down, Ripple Counter using JK
Flip-flop.
 Hardware & software requirements:
IC 7476 (MS-JK Flip-flop), Digital Trainer Kit, patch cords, +5V power supply.

Theory:

1) Asynchronous counter:

A digital counter is a set of flip flop. An Asynchronous counter uses T flip flop to
perform a counting function. The actual hardware used is usually J-K flip-flop connected to logic
1.
In ripple counter, the first flip-flop is clocked by the external clock pulse & then
each successive flip-flop is clocked by the Q or /Q‘ output the previous flip-flop. Therefore in an
asynchronous counter the flip-flop are not clocked simultaneously. The input of MS-JK is
connected to VCC because when both inputs are one output is toggled. As MS-JK is negative edge
triggered at each high to low transition the next flip-flop is triggered. On this basis the design is
done for MOD-8 counter.

2) Up Counter:

Fig 1 shows 3 bit Asynchronous Up Counter. Here Flip-flop A act as a MSB


Flip-flop and Flip-flop C can act as a LSB Flip-flop. Clock pulse is connected to the Clock of flip-
flop C. Output of Flip-flop C (Qc) is connected to clock of next flip-flop(i.e. Flip-flop B) and so
on. As soon as clock pulse changes out put is going to -change(at the negative edge of clock pulse)
as a Up count sequence. For 3 bit Up counter Truth table is as shown below.

3) Down Counter:

Fig 2 shows 3 bit Asynchronous Down Counter. Here Flip-flop a act as a


MSB Flip-flop and Flip-flop C can act as a LSB Flip-flop. Clock pulse is connected to the Clock
of flip-flop C. Output of Flip-flop C (Qc‘) is connected to clock of next flip- flop (i.e. Flip-flop B)
and so on. As soon as clock pulse changes output is going to change (at the
negative edge of clock pulse) as a down count sequence. For 3 bit down counter Truth table is as
shown below.
Digital Electronics Lab (Pattern 2019)

In both the counters Inputs J and K are connected to Vcc, hence J-K Flip flop can work in toggle
mode. Preset and Clear both are connected to logic 1.

 Truth Table:

Up Counter Down Counter


Counter States F/F Output
Counter States F/F Output
QA QB QC
QA QB QC
7 1 1 1
0 0 0 0
6 1 1 0
1 0 0 1
5 1 0 1
2 0 1 0
4 1 0 1
3 0 1 1
3 0 1 1
4 1 0 0
2 0 1 0
5 1 0 1
1 0 0 1
6 1 1 0
0 0 0 0
7 1 1 1
 Logic diagram:

Fig 1:
3 Bit Asynchronous Up Counter
Digital Electronics Lab (Pattern 2019)

Fig 2: 3 Bit Asynchronous Down Counter

Timing Diagram:

1. 3 Bit Asynchronous Up Counter

CLK

Qa

Qb

Qc

2. 3 Bit Asynchronous Down Counter:


Digital Electronics Lab (Pattern 2019)

CLK

Qc 0

Qb

Qa

 Uses:
1) The counters are specially used as the counting devices.
2) They are also used to count number of pulses applied.
3) It also works for dividing frequency.
4) It helps in counting the number of product coming out of the machinery where
product is coming out at equal interval of time.

Outcomes: Thus, we implemented up and down ripple counter. Using IC 7476


Digital Electronics Lab (Pattern 2019)

EXPERIMENT NO: 9
TITLE: SYNCHRONOUS COUNTER

 Title: Synchronous counter


 Objective: 3 Bit up/down synchronous Counter
 Problem Statement: To design and implement 3 bit UP and Down, Controlled UP/Down
Synchronous Counter using MS-JK Flip-flop.
 Hardware & Software Requirement’s :
Digital Trainer Kit, IC 7476, IC 7408, IC 7432 & IC 7404.patch cords, +5V power supply.

Theory:

Counters: counters are logical device or registers capable of counting the no of states or no of
clock pulse arriving at its clock input where clock is a timing parameter arriving at regular intervals
of time, so counters can be also used to measure time & frequencies. They are made up of flip
flops. Where the pulse are counted to be made of it goes up step by step & the o/p of counter in
the flip flop is decoded to read the count to its starting step after counting n pulse incase of module
& counters.

 Synchronous Counter:

In this counter, all the flip flops receive the external clock pulse simultaneously.

Ex:- Ring counter & Johnson counter

The gates propagation delay at reset time will not be present or we may
say will not occur.

 Classification of synchronous counter:

Depending on the way in which counting processes, the synchronous


counter is classified is :-

1) Up counter.
2) Down counter.
3) Up down counter.

 Up Counter:
Digital Electronics Lab (Pattern 2019)

The up counter counts binary form 0 to7 i.e.(000 to 111).It counts from small to
large number. It‘s O/P goes on increasing as they receive clock pulse

 Down Counter:
This down counter counts binary from 7-0 i.e.(111-000).It counts from large to
small number. It‘s O/P goes on increasing as they receive clock pulse

 Excitation Table:- The tabular representation of the operation of flip flop (i.e:
Operational Characteristic)

Present State Next State J K


0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

For M = 0, it acts as an Up counter and for M =1 as an Down counter.

State Table for 3 bit Up-Down Synchronous Counter:

Control Present State Next State Input for Flip-flop


input M QC QB QA QC+1 QB+1 QA+1 JC KC JB KB JA KA
0 0 0 0 0 0 1 0 X 0 X 1 X
0 0 0 1 0 1 0 0 X 1 X X 1
0 0 1 0 0 1 1 0 X X 0 1 X
0 0 1 1 1 0 0 1 X X 1 X 1
0 1 0 0 1 0 1 X 0 0 X 1 X
0 1 0 1 1 1 0 X 0 1 X X 1
0 1 1 0 1 1 1 X 0 X 0 1 X
0 1 1 1 0 0 0 X 1 X 1 X 1
1 0 0 0 1 1 1 1 X 1 X X 1
1 0 0 1 0 0 0 0 X 0 X 1 X
1 0 1 0 0 0 1 0 X X 1 X 1
1 0 1 1 0 1 0 0 X X 0 1 X
1 1 0 0 0 1 1 X 1 1 X X 1
1 1 0 1 1 0 0 X 0 0 X 1 X
1 1 1 0 1 0 1 X 0 X 1 X 1
1 1 1 1 1 1 0 X 0 X 0 1 X
Digital Electronics Lab (Pattern 2019)
K- map Simplification:

QBQA
MQC 00 01 11 10 QBQA 00 01 11 10
MQC
00 1 X X 1
00 X 1 1 X
01 1 X X 1
01 X 1 1 X
11 1 X X 1 11 X 1 1 X
10 1 X X 1 10 X 1 1 X

JA = 1 KA = 1

QBQA 00 01 11 10 QBQA
MQC MQC 00 01 11 10
00 0 1 X X 00 X X 1 0
01 0 1 X X 01 X X 1 0
11 1 0 X X 11 X X 0 1
10 1 0 X X 10 X X 0 1

JB = M QA + M QA KB = M QA + M QA

QBQA QBQA
00 01 11 10 MQC 00 01 11 10
MQC
00 0 0 1 0 00 X X X X
01 X X X X 01 0 0 1 0
11 X X X X 11 1 0 0 0
10 1 X 0 0 10 X X X X

JC = M QA QB + M QA QB KC = M QA QB + M QA QB
Digital Electronics Lab (Pattern 2019)

Uses:
2) The synchronous counter is specially used as the counting devices.
3) They are also used as counter to count the no of clock pulses applied.
4) It also works for counting frequency & is used in frequency divider circuit.
5) It is used in digital voltmeter.
6) It is also used in counter type A to D converter.
7) It is also used for time measurement.
8) It is also used in digital triangular wave generator.
9) It helps in counting the no of product coming out from machinery where product is
coming out at equal interval of time.

Outcome:
Up and down counters are successfully implemented, the counters are studied & o/p
are checked. The truth table is verified.
Digital Electronics Lab (Pattern 2019)

EXPERMINET NO: 10
TITLE: MOD-N COUNTER

 Title: Mod-N counter using Decade counter IC 7490

 Objective: Modulo N counter using 7490(N>10).


 Problem Statement: Realization of mod N counter using IC 7490.
 Hardware & software requirements:
Digital Trainer Kit, 7490 (Decade Counter IC), Patch Cord, + 5V Power Supply
Theory:
Ripple counter IC-7490 (decade counter): i.e .having various name like mod-n
counter, decade counter ,BCD counter.
IC-7490 is a TTL MSI decade counter. It contains four master slave flip flops and
additional gating to provide a divide-by-two counter and a three stage binary
counter which provides a divide by 5 counter.
Digital Electronics Lab (Pattern 2019)

Table 1:-Reset/count truth table


Reset inputs Output
R0(1) R0(2) R9(0) R9(1) QD QC QB QA
1 1 0 X 0 0 0 0
1 1 X 0 0 0 0 0
X X 1 1 1 0 0 1
X 0 X 0 COUNTER
0 X 0 X COUNTER
0 X X 0 COUNTER
X 0 0 x COUNTER

IC 7490 is MOD-10 or decade counter. It is a 14 pin IC with the pin configuration as shown
in fig:
Digital Electronics Lab (Pattern 2019)

Fig. 2 Pin configuration of IC7490.

Table 2:-Pin name and description of IC 7490


Pin name Description
Input B This is clock input to the internal MOD-5 ripple counter, which is negative
edge triggered.
R0(1),R0(2) Gated zero reset inputs
R9(1),R9(2) These are gated set to nine inputs
QD,QC,QB Output of internal MOD-5 counter with QD as MSB.
QA Output of internal MOD-2 counter with QA as LSB.
Input A Clock input to FF-A which is negative edge triggered.
Digital Electronics Lab (Pattern 2019)

Decade Counter Operation :


1. The output of MOD-2 is externally connected to the input B which is the clock input of the
internal MOD-5 counter.
2. Hence QA toggles on every falling edge of clock input whereas the output QD,QC,QB of the
MOD-5 counter will increment from 000 to 100 on low going change of Q A output.
3. Due to cascading of MOD-2 and MOD-5 counter, the overall configuration becomes a MOD-
10 i.e. decade counter.
4. The reset inputs Ro(1), Ro(2) and preset inputs R9(1), R9(2) are connected to ground so as to
make them inactive.

Table: Summarizes the opération of the 7490 as décade counter


O/p of MOD-5 O/p of MOD-2 CLK Count
QD QC QB QA
0 0 0 0 0 0
0 0 0 1 1 1
0 0 1 0 2 2
0 0 1 1 3 3
0 1 0 0 4 4
0 1 0 1 5 5
0 1 1 0 6 6
0 1 1 1 7 7
1 0 0 0 8 8
1 0 0 1 9 9
Implémentations:
Realization of MOD 10 counter using IC 7490
Digital Electronics Lab (Pattern 2019)

Fig 3.MOD-10 counter using IC 7490

Outcomes:
Thus, we implemented divide by two (MOD-2) and divide by 5 (MOD-5) counter.
Using IC7490.
Digital Electronics Lab (Pattern 2019)

EXPERMINET NO: 11
TITLE: SEQUENCE GENERATOR

AIM : To design and implement sequence generator with and without bushing using

IC 7476.

OBJECTIVE : To understand sequence generator, one of the sequential circuit.

IC’s USED : IC 7476(Dual JK), 7408 (AND-gate), 7432 (OR-gate).

THEORY :
A sequential circuit which generates a prescribed sequence of bits in synchronism with a
clock is referred to as a sequence generator. These pulse trains or sequence of bits can be used to
open valves, close gates, turn on lights, and turn off machines and other variety of jobs.

For the design of sequence generator, we first determine the required no. of flip flops and
the logic circuit for the next state decoder.

No. of flip flops required to generate particular sequence can be determined as follows.

1) Find the no. of 1‘s in the sequence.


2) Find the no. of 0‘s in the sequence.
3) Take the maximum out of two.
4) If N is the required no. of flip flops, choose minimum value of ‗n‘ to satisfy equation
given below.
Max (0‘s , 1‘s) ≤ 2n-1

The aim in this experiment is to design a sequence generator to generate a sequence of bit i.e.
10101.

For finding the no. of flip flops we use the formula

m≤2n-1

where m= maximum count and

n= no. of flip flops required.


Digital Electronics Lab (Pattern 2019)

For the given sequence no. of 1‘s=3 no. of 0‘s=2, so minimum value of n which satisfies above
relation is 3. Once the no. of flip flops are decided we have to assign unique states corresponding
to each bit in the given sequence such that flip flop representing least significant bit generates the
given sequence ( usually the o/p of flip flop representing the least significant bit is used to generate
the given sequence)

Design -

For the sequence of bits 10101 we require three flip flops as calculated above. The State Diagram,
state assignment for this problem is shown below. Where we will use the o/p FF 0 i.e. o/p of first
flip flop Q0 as a sequence of bits & assign unique states corresponding to each bit in the sequence
as shown in state assignment table.

1. Sequence Generator

State assignment table :

Q2 Q1 Q0 STATES

0 0 1 1

0 0 0 0

0 1 1 3

0 1 0 2

1 0 1 5

State Diagram :-

5 0

2 3
Digital Electronics Lab (Pattern 2019)
State table :

Present states Next states Flip flop input


Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 1 1 0 X 1 X 1 X
0 0 1 0 0 0 0 X 0 X X 1
0 1 0 1 0 1 1 X X 1 1 X
0 1 1 0 1 0 0 X X 0 X 1
1 0 0 X X X X X X X X X
1 0 1 0 0 1 X 1 0 X X 0
1 1 0 X X X X X X X X X
1 1 1 X X X X X X X X X

K-Map simplification:

1) For J0 –

00 01 11 10

1 X X 1

X X X X

J0 = 1
Digital Electronics Lab (Pattern 2019)

2) For K0 –

00 01 11 10

X 1 1 X

X 0 X X

K0 = Q2

3) For J1 –

00 01 11 10

1 0 X X

X 0 X X

J1 = Q0

3) For K1 –

00 01 11 10

X X 0 1

X X X X

K1 = Q0
Digital Electronics Lab (Pattern 2019)

3) For J2–

00 01 11 10

0 0 0 1

X X X X

J2 = Q1Q0

3) For J1 –

00 01 11 10

X X X X

X 1 X X

K2 = 1
Logic Diagram-

vcc
vcc J0 Pr Q0 J1 Pr Q1 J2 Pr Q2

Clk
F/F -1 F/F-2 F/F-3

Q0(LSB) Q1 Q2(MSB)

Hardware requirements:

GATE ICs Quantity

JK F/F 7476 2

AND 7408 1

Conclusion: In this way sequence generator with & without bushing is studied and implemented.
Digital Electronics Laboratory manual (2019 Pattern)

GROUP - C
Digital Electronics Laboratory manual (2019 Pattern)

EXPERMINET NO: 12
TITLE: SHIFT REGISTER

AIM: Study of Shift Registers(SISO,SIPO,PISO,PIPO).


OBJECTIVE: We are using shift register for data storage , and transfer and certain arithmetic
and logic operations.

APPARATUS: Digital board, connecting wires , IC-7474,IC-7432,IC-7408.


THEORY:

Shift Register:
1. The binary data in a register can be moved within the register from one filp-flop to the other or
outside it with appliction of clock pulses.
2. The register that allow such data storage ,data transfers and certain arithmetic andlogic
operations are called as shift registers

Mode of Operation of a Shift Register:


The various modes in which a shift register can operate as follows:
1. Serial Input Serial Output(SISO).
2. Serial Input Parallel Output(SIPO).
3. Parallel Input Serial Output(PISO).
4. Parallel Input Parallel Output(PIPO).
Digital Electronics Laboratory manual (2019 Pattern)

Sr No Mode Illustrative Diagram Comments


.

Serial input Data bites shift from left to


1 serial output right by 1 position per clock
(serial cycle.
shift right)

Serial input serial Data bits shift from right to


2 output(ser left by 1 position per clock.
ial shift
register)

Parallel input All inputs are loaded


3 serial output. simultaneously but output bit
by bit

Serial input All output bits are made


4 parallel output available simultaneously
after 4-clock pluses.

Parallel input All inputs are loaded


5 parallel output simultaneously and are
available at the output
simultaneously
Digital Electronics Laboratory manual (2019 Pattern)

Fig1: Serial Shift Left Register

Serial Input Serial Output(Shift Left Mode):-

1. The serial input serial output type shift register with shift left mode is shown in figure.
2. Let all the filp-flops be initially in the reset condition i.e Q3=Q2=Q1=Q0=0.
3. We are going to illustrate the entery of a four bit binary number 1111 into the register.
4. When this is to be done this number should be applied to “Din” bit by with the MSB bit applied
first.
5. The D input of FF-O i.e D0 is connected to serial data input(Din). Output of FF-O
i.e Q0 is connected to the input of the next filp-flop i.e D1 and so on.

CLK Q3 Q2=D3 Q1=D Q0=D1 Serial input


2 Din=D0
Initially 0 0 0 0
1 0 0 0 1 1
2 0 0 1 1 1
3 0 1 1 1 1
4 1 1 1 1 1

Fig 2:Summary of Shift Left Operation

Serial In Parallel Out (SIPO):

1. In this operation the data is entered serially and taken out in parallel.
Digital Electronics Laboratory manual (2019 Pattern)

2. That means first the data is loaded bit by bit. The outputs are disabled as long as the loading is
taking place.
3. As soon as the loading is complete, and all the flip- flop contain their required data, the outputs
are enabled so that all the loaded data is made available over all the output lines simultaneously.
4. Number of clock cycles required to load a four bit word is 4.Hence the speed of operationof
SIPO mode is same as that of SISO mode.

Parallel In Serial Out Mode(PISO):

1. In this mode, the bitsare entered in parallel i.e simultaneously into a shift register as shown in
figure.
2. The circuit shown in figure is a four bit parallel input serial output register.
3. Output of previous FF is connected to the input of the next one via a combinational circuit.
4. The binary input word B0, B1 , B2 , B3 is applied through the same combinational circuit.
5. There are two modes in which this circuit can work namely shift register mode or load mode
Digital Electronics Laboratory manual (2019 Pattern)

Load Mode:
1. In order to load the word B3, B2 ,B1 , B0 into the shift register we have to select the load mode
by setting shift/load input to Q.
2. When the shift/load line is low (0), the AND gates 2,4 and 6 becomes active. They will pass B1
, B2 and B3 bits to the inputs D1 , D2 , D3 of corresponding filp-flops. D0 is directly connected to
B0.
3. On the low going edge of clock , the binary inputs B0 , B1 , B2 , B3 will get loaded into
the corresponding filp-flops. Thus parallel loading takes place.

Shift Mode:
1. In order to operate the shift register in the shift mode we have to select the shift mode by
applying a logic 1 to the shift/load input.
2. When the shift/load line is high (1) , the AND gates 2,4,6 becomes inactive. Hence the parallel
loading of the data becomes impossible.
3. But the AND gates 1,3 and 5 become active. Therefore the shifting of data from left to right bit
by bit on application of clock pulses becomes possible. D0 acts as the data input terminal and at
Q3 we get the serial data output.
4. Thus the parallel in serial out operation takes place.

Parallel In Parallel Out(PIPO):


1. Figure demonstrates the parallel in parallel out mode of operation.
2. The 4 bit binary input B0 , B1 , B2 , B3 is applied to the data inputs D0 , D1 , D2 AND
D3 respectively of the four Filp-Flops.
3. As soon as a negative clock edge is applied the input binary bits will be loaded into the flip-flops
simultaneously.
4. The loaded bits will appear simultaneously to the output side. Only one clock pulse is
essential to load all the bits. Therefore PIPO mode is the fastest mode of operation.

Fig:-Parallel In Parallel Out Shift Register

Outcomes: In this way , we have studied shift registers SISO , SIPO , PISO, PIPO.

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