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candy machine verilog

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rohithfx504
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10 views

candy machine verilog

Uploaded by

rohithfx504
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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`timescale 1ns / 1ps

module candy_b(
input clk_100MHz,
input reset,
input btn_25,
input btn_10,
input btn_5,
output [0:6] seg
);

wire btnR, btnU, btnC, btnD;


wire w_2Hz, w_10Hz;
wire [4:0] w_change;
wire [2:0] w_the_state;

btn_debounce bdR(.clk(clk_100MHz), .btn_in(reset), .btn_out(btnR));


btn_debounce bdU(.clk(clk_100MHz), .btn_in(btn_25), .btn_out(btnU));
btn_debounce bdC(.clk(clk_100MHz), .btn_in(btn_10), .btn_out(btnC));
btn_debounce bdD(.clk(clk_100MHz), .btn_in(btn_5), .btn_out(btnD));
state_machine
sm(.clk(w_10Hz), .reset(btnR), .btn_25(btnU), .btn_10(btnC), .btn_5(btnD),.the_state(w_the_state), .change(w_chan
ge));
tenHz_generator ten(.clk_100MHz(clk_100MHz), .reset(btnR), .clk_10Hz(w_10Hz));
seg7_control sev(.clk(clk_100MHz), .reset(btnR),.the_state(w_the_state), .seg(seg) , .an(an));

endmodule

module tenHz_generator(input clk_100MHz,input reset,output clk_10Hz );

reg [23:0] counter_reg = 0;


reg clk_out_reg = 0;

always @(posedge clk_100MHz or posedge reset) begin


if(reset) begin
counter_reg = 0;
clk_out_reg = 0;
end
else
if(counter_reg == 9_999_999)
begin
counter_reg <= 0;
clk_out_reg <= ~clk_out_reg;
end
else
counter_reg <= counter_reg + 1;
end

assign clk_10Hz = clk_out_reg;


endmodule

module state_machine(input clk,input reset, input btn_25,input btn_10,input btn_5,output [2:0] the_state,
output reg [4:0] change );

reg [5:0] counter_reg = 0;


reg [5:0] ch_counter_reg = 0;
reg [2:0] state_reg;
parameter idle = 3'b000;
parameter s_5 = 3'b001;
parameter s_10 = 3'b010;
parameter s_15 = 3'b011;
parameter s_20 = 3'b100;
parameter s_25 = 3'b101;
parameter ch = 3'b110;

always @(posedge clk or posedge reset) begin


if(reset)
state_reg <= idle;
else
case(state_reg)
idle : begin
change = 5'd0;
if(btn_25)
state_reg <= s_25;
else if(btn_10)
state_reg <= s_10;
else if(btn_5)
state_reg <= s_5;
end

s_5 : begin
if(btn_25) begin
state_reg <= s_25;
change <= 5'd5;
end
else if(btn_10)
state_reg <= s_15;
else if(btn_5)
state_reg <= s_10;
end

s_10 : begin
if(btn_25) begin
state_reg <= s_25;
change <= 5'd10;
end
else if(btn_10)
state_reg <= s_20;
else if(btn_5)
state_reg <= s_15;
end
s_15 : begin
if(btn_25) begin
state_reg <= s_25;
change <= 5'd15;
end
else if(btn_10)
state_reg <= s_25;
else if(btn_5)
state_reg <= s_20;
end

s_20 : begin
if(btn_25) begin
state_reg <= s_25;
change <= 5'd20;
end
else if(btn_10) begin
state_reg <= s_25;
change = 5;
end
else if(btn_5)
state_reg <= s_25;
end

s_25 : begin
if(counter_reg == 29)
state_reg <= ch;
end

ch : begin
if(ch_counter_reg == 29)
state_reg <= idle;
end
endcase
end

always @(posedge clk or posedge reset) begin


if(reset)
counter_reg <= 0;
else
if(state_reg == s_25)
if(counter_reg == 29)
counter_reg <= 0;
else
counter_reg <= counter_reg + 1;
end

always @(posedge clk or posedge reset) begin


if(reset)
ch_counter_reg <= 0;
else
if(state_reg == ch)
if(ch_counter_reg == 29)
ch_counter_reg <= 0;
else
ch_counter_reg <= ch_counter_reg + 1;
end

assign the_state = state_reg;

endmodule

module seg7_control(input clk,input reset,input [2:0] the_state,output reg [0:6] seg );


parameter C = 7'b011_0001;
parameter B = 7'b110_0000;
reg [1:0] anode_select;
reg [16:0] anode_timer;

always @(posedge clk or posedge reset) begin


if(reset) begin
anode_select <= 0;
anode_timer <= 0;
end
else
if(anode_timer == 99_999) begin
anode_timer <= 0;
anode_select <= anode_select + 1;
end
else
anode_timer <= anode_timer + 1;
end

always @(anode_select) begin


case(anode_select)
2'b00 : an = 4'b0111;
2'b01 : an = 4'b1011;
2'b10 : an = 4'b1101;
2'b11 : an = 4'b1110;
endcase
end

always @(posedge clk) begin


case(the_state)
3'b000 : begin
case(an)
4'b0111 : seg = B;
4'b1011 : seg = B;
4'b1101 : seg = B;
4'b1110 : seg = B;
endcase
end
3'b101 : begin
case(an)
4'b0111 : seg = C;
4'b1011 : seg = C;
4'b1101 : seg = C;
4'b1110 : seg = C;
endcase
end

endcase
end
endmodule

module btn_debounce(input clk, input btn_in, output btn_out );


reg a, b, c;
always @(posedge clk) begin
a <= btn_in;
b <= a;
c <= b;
end

assign btn_out = c;
endmodule

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