UNIT-III EC3552-VLSI AND CHIP DESIGN

UNIT – III

SEQUENTIAL LOGIC CIRCUITS AND CLOCKING STRATEGIES

Static Latches and Registers, Dynamic Latches and Registers, Pipelines, Non-bistable Sequential Circuits,
Timing classification of Digital Systems, Synchronous Design, Self-Timed Circuit Design .

3.1 Static Latches and Registers:

 Discuss in detail various static latches and registers. (Nov 2016)

 Explain the methodology of sequential circuit design of Latches. (May 2014)
 Discuss the operation of a CMOS latch. (Nov 2007)

3.1.1 The Bi-stability Principle

 Static memories use positive feedback to create a bistable circuit. A bistable circuit has two
stable states that represent 0 and 1.
 The basic idea is shown in Figure 3.1a, which shows two inverters connected in cascade
along with a voltage-transfer characteristic (VTC).
 The output of the second inverter Vo2 is connected to the input of the first V i1, as shown
by the dotted lines in Figure 3.1a.
 The resulting circuit has only three possible operation points (A, B, and C).
 A and B are stable operation points, and C is a metastable operation point.

Figure 3.1: a. Two inverters connected in cascade b. VTCs

 Cross-coupled inverter pair is biased at point C. It is amplified and regenerated around the
circuit loop.
 The bias point moves away from C until one of the operation points A or B is reached.
 C is an unstable operation point. Every deviation causes the operation point to run away
from its original bias. Operation points with this property are termed as metastable.

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(a) Figure 3.2 Metastability.

 A bistable circuit has two stable states. In absence of any triggering, the circuit remains in a
single state.
 A trigger pulse must be applied to change the state of the circuit.
 Common name for a bistable circuit is flip-flop.

3.1.2 SR Flip-Flops
 The SR or set-reset flip-flop implementation is shown in Figure (a) below.
 This circuit is similar to the cross-coupled inverter pair with NOR gates replacing the
inverters.
 The second input of the NOR gates is connected to the trigger inputs (S and R), that make it
possible to force the outputs Q and Qbar.
 These outputs are complimentary (except for the SR = 11 state).
 When both S and R are 0, the flip-flop is in a quiescent state and both outputs retain their
value.
 If a positive (or 1) pulse is applied to the S input, the Q output is forced into the 1 state
(with Qbar going to 0).
 Vice versa, a 1 pulse on R resets the flip-flop and the Q output goes to 0.

Figure 3.3
 When both S and R are high, both Q and Qbar are forced to zero. This input mode is
considered to be forbidden.
 An SR flip-flop can be implemented using a cross-coupled NAND structure as shown in
Figure 3.4

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Figure 3.4 NAND based SR flip-flop

Clocked SR flip-flop:
 Clocked SR flip-flop (a level-sensitive positive latch) is shown in Figure 3.5.
 It consists of a cross-coupled inverter pair, plus 4 extra transistors to drive the flip-flop
from one state to another and to provide clocked operation.
 Consider the case where Q is high and R pulse is applied.
 The combination of transistors M4, M7, and M8 forms a ratioed inverter.
 In order to make the latch switch, we must succeed in bringing Q below the switching
threshold of the inverter M1-M2.
 Once this is achieved, the positive feedback causes the flip-flop to invert states. This
requirement forces to increase the sizes of transistors M5, M6, M7, and M8.

Figure 3.5 CMOS clocked SR flip-flop

 The clocked SR flip-flop does not consume any static power.

3.1.3 Multiplexer Based Latches:

 Multiplexer based latches can provide similar functionality to the SR latch.
 But sizing of devices only affects performance and is not critical to the functionality.
 Figure 3.6 shows an implementation of static positive and negative latches based on
multiplexers.
 For a negative latch, when the clock signal is low, the input 0 of the multiplexer is selected,
and the D input is passed to the output.
 When the clock signal is high, the input 1 of the multiplexer connected to the output of the
latch.
 The feedback holds the output stable while the clock signal is high.

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 Similarly in the positive latch, the D input is selected when clock is high and the output is
held (using feedback) when clock is low.

Figure 3.6 Negative and positive latches based on multiplexers.

 Design a d-latch using transmission gate. (May 2015)

 Design a D-latch using transmission gate. Using which realize a two phase non –
overlapping master slave negative edge triggered D flip-flop. (April 2019-13M)
 Illustrate the circuit designs for basic latches, then build the flip-flops and pulsed
latches. [May 2021][Nov/Dec 2022]
 A transistor level implementation of a positive latch is shown in Figure 3.7.
 When CLK is high, the bottom transmission gate is ON and the latch is transparent – i.e,
the D input is copied to the Q output.
 During this phase, the feedback loop is open due to the top transmission gate is OFF.

Figure 3.7 Transistor level implementation of a positive latch built using transmission gates.

 To reduce the clock load, implement a multiplexer based NMOS latch using two pass
transistors as shown in Figure 3.8.
 The advantage of this approach is the reduced clock load of only two NMOS devices.
 When CLK is high, the latch samples the D input, while a low clock-signal enables the
feedback-loop and puts the latch in the hold mode.

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Figure 3.8 Multiplexer based NMOS latch using NMOS only pass transistors for multiplexers.

 Explain the operation of master-slave based edge triggered register. (May 2016)
 Draw and explain the operation of conventional CMOS, pulsed and resettable latches.
(Nov 2012)
 Discuss about CMOS register concept and design master slave triggered register, explain
its operation with overlapping periods. (April 2018, NOV 2018)
 Realize a negative level sensitive latch using which realize an edge triggered master slave
D-Flip flop. Explain its working. (Nov 2019) [April / May 2023]

3.1.4 Master-Slave Based Edge Triggered Register:

 An edge-triggered register is to use a master-slave configuration as shown in Figure 3.9.

 The register consists of cascading a negative latch (master stage) with a positive latch
(slave stage).
 A multiplexer based latch is used to realize the master and slave stages.
 On the low phase of the clock, the master stage is transparent and the D input is passed to
the master stage output, QM.
 During this period, the slave stage is in the hold mode, keeping its previous value.
 On the rising edge of the clock, the master slave stops sampling the input and the slave
stage starts sampling.
 During the high phase of the clock, the slave stage samples the output of the master stage
(QM), while the master stage remains in a hold mode.
 A negative edge-triggered register can be constructed using the same principle by simply
switching the order of the positive and negative latch (i.e., placing the positive latch first).

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Figure 3.9: Positive edge-triggered register based on a master-slave configuration.
 A complete transistor level implementation of the master-slave positive edge-triggered
register is shown in Figure 3.10.
 When clock is low (CLK bar = 1), T1 is ON and T2 is OFF and the D input is sampled onto
node QM.
 During this period, T3 is OFF and T4 is ON and the cross-coupled inverters (I5 & I6) hold the
state of the slave latch.

Figure 3.10 Transistor-level implementation of a master-slave positive edge-triggered register

using multiplexers.
 When the clock goes high, the master stage stops sampling the input and goes into a hold
mode.
 T1 is OFF and T2 is ON and the cross coupled inverters I3 and I4 hold the state of QM. Also
T3 is ON and T4 is OFF and QM is copied to output Q.
3.1.5 Non-ideal clock signals:
 We have assumed that CLK is a perfect inversion of CLK.
 Even if this was possible, this would still not be a good assumption.
 Variations can exist in the wires. It is used to route the two clock signals or the load
capacitances can vary based on data stored in the connecting latches.
 This effect, known as clock skew is a major problem and causes the two clock signals to
overlap as is shown in Figure 3.11 b.
 Clock-overlap can cause two types of failures, as illustrated for the NMOS-only negative
master-slave register of Figure 3.11 a.

Figure 3.11 Master-slave register based on NMOS-only pass transistors.

 When the clock goes high, the slave stage should stop sampling the master stage output and
go into a hold mode.
 However, since CLK and CLK are both high for a short period of time (the overlap
period).

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 Both sampling pass transistors conduct and there is a direct path from the D input to the Q
output.
 As a result, data at the output can change on the rising edge of the clock, which is
undesired for a negative edge triggered register.
 The is known as a race condition in which the value of the output Q is a function of
whether the input D arrives at node X before or after the falling edge of CLK .
 If node X is sampled in the metastable state, the output will switch to a value determined
by noise in the system.
 Those problems can be avoided by using two non-overlapping clocks PHI and PH2.
 By keeping the non-overlap time tnon_overlap between the clocks large enough, such that no
overlap occurs even in the presence of clock-routing delays.
 During the non-overlap time, the FF is in the high-impedance state.
 Leakage will destroy the state, if this condition holds for too long a time.
 Hence the name pseudostatic: the register employs a combination of static and dynamic
storage approaches depending upon the state of the clock.

Figure 3.12 Pseudostatic two-phase D register.

3.1.6 Low-Voltage Static Latches:
 The scaling of supply voltages is critical for low power operation.
 At very low power supply voltages, the input to the inverter cannot be raised above the
switching threshold, resulting in incorrect evaluation.
 Scaling to low supply voltages, hence requires the use of reduced threshold devices.
 The shaded inverters and transmission gates are implemented in low-threshold devices.
 The low threshold inverters are gated using high threshold devices to eliminate leakage.
 During normal mode of operation, the sleep devices are tuned on.
 During idle mode, the high threshold devices in series with the low threshold inverter are
turned OFF (the SLEEP signal is high), eliminating leakage.

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Figure 3.13: One solution for the leakage problem in low-voltage operation using MTCMOS.
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3.2 Dynamic Latches and Registers:

 Discuss about the design of sequential dynamic circuits. (Nov 2012, Nov 2017)
 Explain the methodology of sequential circuit design of flip-flop. (May 2014)

 A stored value remains valid as long as the supply voltage is applied to the circuit, hence
the name static.
 The major disadvantage of the static gate is, its complexity.
 Registers are used in computational structures that are constantly clocked, such as pipelined
data path.
 The requirement that the memory should hold state for extended periods of time.
 This results in circuits, based on temporary storage of charge on parasitic capacitors.
 The principle is identical to the dynamic logic. In dynamic logic, logic signal is a charge,
stored on a capacitor.
 The absence of charge denotes as logic 0 and presence of charge denotes as logic 1.
 A stored value can be kept for a limited amount of time (range of milliseconds).
 A periodic refresh of its value is necessary.

3.2.1 Dynamic Transmission-Gate Based Edge-triggered Registers:

 Design a d-flipflop using transmission gate. (Nov 2016)
 A dynamic positive edge-triggered register based on the master-slave concept is shown in
Figure 3.14.
 When CLK = 0, the input data is sampled on storage node 1. It has an equivalent
capacitance of C1 consisting of the gate capacitance of I1, the junction capacitance of T1,
and the overlap gate capacitance of T1.

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 During this period, the slave stage is in a hold mode with node 2 in a high-impedance state.
 On the rising edge of clock, the transmission gate T2 turns on. The value is sampled on
node1 before the rising edge propagates to the output Q.
 Node 2 stores the inverted version of node 1.
 The reduced transistor provides high-performance and low-power systems.

Figure 3.14 Dynamic edge-triggered register.

 The set-up time of this circuit is the delay of the transmission gate and time takes node 1 to
sample the D input.
 The hold time is approximately zero, since the transmission gate is turned OFF.
 The propagation delay (tc-q) is equal to two inverter delays plus the delay of the
transmission gate T2.
 Dynamic register has storage nodes (i.e., the state). A node has to be refreshed at periodic
intervals to prevent a loss. Loss due to charge leakage and diode leakage.
 Clock overlap is an important for register. Consider the clock waveforms shown in Figure
3.15.
 During the 0-0 overlap period, the NMOS of T1 and the PMOS of T2 are simultaneously
on.
 It is creating a direct path for data to flow from the D input of the register to the Q output.
This is known as a race condition.
 The output Q can change on the falling edge, if the overlap period is large.
 Overlap period constraint is given as: toverlab00  tT 1  tI 1  tT 2
 Similarly, the constraint for the 1-1 overlap is given as: thold > toverlab1-1

Figure 3.15 Impact of non-overlapping clocks

3.2.2 C2MOS Dynamic Register:

The C2MOS Register

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 Figure 3.16 shows positive edge-triggered register based on the master-slave concept,
which is insensitive to clock overlap. This circuit is called the C2MOS (Clocked CMOS)
register.

1. CLK = 0 ( CLK = 1):

o The first tri-state driver is turned ON. The master stage acts as an inverter,
sampling the inverted of D on the internal node X.
o The master stage is, in evaluation mode. The slave section is, in hold mode.
o Both transistors M7 and M8 are OFF, decoupling the output from the input. The
output Q retains its previous value stored on the output capacitor CL2.

2. CLK = 1 ( CLK = 0):

o The master stage section is in hold mode (M3-M4 off), while the second section
evaluates (M7-M8 on).
o The value stored on CL1 propagates to the output node through the slave stage,
which acts as an inverter.
o The overall circuit operates as a positive edge-triggered master-slave register.

Figure 3.16 C2MOS master-slave positive edge-triggered register.

 It is similar to the transmission-gate based register, presented earlier. However, there is
an important difference.
 A C2MOS register with CLK-CLK clocking is insensitive to overlap, as long as the rise
and fall times of the clock edges are small.

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Figure 3.17 C2MOS D FF during overlap periods.

3.2.3 True Single-Phase Clocked Register (TSPCR):

Explain the operation of True Single Phase Clocked Register. (Nov 2016, April 2017)

 In the two-phase clocking schemes, care must be taken in routing the two clock signals to
ensure that overlap is minimized.
 While the C2MOS provides a skew-tolerant solution, it is possible to design registers that
only use a single phase clock.
 The True Single-Phase Clocked Register (TSPCR) uses a single clock without an inverse
clock.
 Figure 3.19 shows positive and negative latch concept.
 For the positive latch, when CLK is high, the latch is in the transparent mode and
propagates the input to the output. Latch has two cascaded inverters, so latch is non-
inverting.
 When CLK = 0, both inverters are disabled and the latch is, in hold-mode.
 Only the pull-up networks are still active, while the pull-down circuits are deactivated.
 As a result of the dual-stage approach, no signal can ever propagate from the input to the
output.
 For the negative latch, when CLK is low, the latch is in the transparent mode and
propagates the input to the output.
 When CLK = 1, both inverters are disabled and the latch is in hold-mode.
 A register can be constructed by cascading positive and negative latches.
 The main advantage is the use of a single clock phase.
 The disadvantage is, increase in the number of transistors (12 transistors are required).

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Figure 3.19 TSPC approach.

 The TSPC latch circuits can be reduced, as in Figure 3.20, where only the first inverter is
controlled by the clock.
 Number of transistors are reduced and clock load is reduced by half.

Figure 3.20 Simplified TSPC latch (also called split-output).

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3.3 Timing Issues:

 Explain in detail about timing issues needed for a logic operation. (April 2017)
 Explain the timing basics in synchronous design in detail. (Nov 2017)[April/May 2023]
 Discuss the timing parameters that characterize the timing of sequential circuit. (NOV 2021)

(A)Sequencing methods:-
 Three methods of sequencing block of combinational logic are possible, as shown in
figure below.
 In flip-flop based system, one flip flop use one cycle boundary.
 Token (data) advances from one cycle to the next on the rising edge. If a token arrives too
early, it waits at the flip flop until next cycle.
 In 2-phase system, phases may be separated by tnonoverlap. [tnonoverlap>0]
 In pulsed system, pulse with is tpw.

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 In 2-phase system, full cycle of combinational logic is divided into two phases,
sometimes called “half-cycles”. Two latch clocks are called 𝜑1 and 𝜑 2.
 Flip flop can be viewed as, a pair of back to back latches using clk and its
complements.
 Table shows delay and timing notations of combinational and sequencing elements.
These delays may differ for rising (with suffix ‘r’) and falling (with suffix ‘f’).

TERM NAME
Tpd logic propagation delay
Tcd logic contamination delay
Tpcq latch flop clock-Q propagation delay
Tccq latch flop clock- to Q contamination delay
Tpdq latch flop D –to Q propagation delay
Tcdq latch flop clock D to Q contamination delay
Tsetup latch flop setup time
Thold latch flop hold time

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 The delay with timing diagram for all three sequencing elements are, as shown in figure
below.
 In combinational logic, input A changing to another value, output Y cannot change
instantaneously. After the contamination delay {tcd}, Y may begin to change (or) glitch.
 Output Y settles to a value in propagation delay {t pd} .
 Input D in flip flop must have settled by some setup time {tsetup} before the rising edge of
clock and should not change again until, a hold time {thold} after the clock edge.

Figure: Timing diagrams

 The output begins to change after a clock-to-contamination delay {tccq} and completely
settles after clock to-Q propagation delay {tpcq}.

(B) Max Delay Constraints:-

 Ideally, the entire clock cycle will be available for computation in the combinational
logic.
 If the combination logic delay is too high, the receiving element {next flop/latch} will
miss its setup time and sample the wrong value.
 This is called as “setup-time failure” or “max-delay failure”.
 It can be solved by redesigning the logic to be faster (or) by increasing the clock period.

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 The clock period must be 𝑇𝑐 ≥ 𝑡𝑝𝑐𝑞 + 𝑡𝑝𝑑 + 𝑡𝑠𝑒𝑡𝑢𝑝

(or)
𝑇𝑝𝑑 ≤ 𝑡𝑐 − (𝑡𝑠𝑒𝑡𝑢𝑝 + 𝑡𝑝𝑐𝑞)

Where, tsetup+tpcq – sequencing overhead.

(C) Min-delay constraints:-

 Sequencing elements can be placed back to back without intervening combinational logic
and still function correctly.
 If the hold time is large and contamination delay is small, data can incorrectly propagate
through successive elements, on one clock edge.
 This corrupt the state of the system called, race condition (or) hold time failure (or) min-
delay failure.
 It can be fixed by redesigning the logic and not by slowing the clock.

𝑡𝑐𝑑 ≥ 𝑡ℎ𝑜𝑙𝑑 − 𝑡𝑐𝑐𝑞

(D)Time Borrowing:
 In flip-flop, dada departs the first flip-flop on the rising edge of the clock and must set up
at the second flip-flop before the next rising edge of the clock.
 If data arrives late, produces wrong result.
 If data arrives early, it is blocked until the clock edge arrives and the remaining time goes
unused and clock imposes a “hard edge”.

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 If one half cycle (or) stage of a pipeline has too much logic, it can borrow time in half-
cycle (or) stage.
 This is called as “Time borrowing”, which can accumulate across multiple cycles.

𝑇𝑐
𝑡𝑏𝑜𝑟𝑟𝑜𝑤 ≤ − (𝑡𝑠𝑒𝑡𝑢𝑝 − 𝑡𝑛𝑜𝑛𝑜𝑣𝑒𝑟𝑙𝑎𝑝)
2
(E) Clock Skew
Analyze the impact of spatial variations of clock signal on edge-triggered sequential logic
circuits. (NOV 2018)
 The spatial variation in arrival time of a clock transition in an integrated circuit is referred
as clock skew.
 The clock skew between two points i and j on a IC is given by δ(i,j)=ti-tj, where ti and tj are
the position of the rising edge of the clock with respect to a reference.
 The clock skew can be positive or negative, depending upon the routing direction and
position of the clock source.
 The timing diagram for the case with positive skew, is shown in figure.
 In the figure, the rising clock edge is delayed by a positive δ at the second register.

Figure: Timing diagram to study the impact of clock skew on performance and
functionality. In this sample timing diagram, δ >0.
(F) Clock Jitter:
 Clock jitter is the temporal variation of the clock period at a given point. The clock period
can reduce or expand on a cycle-by-cycle basis. It is a temporal uncertainty measure.
 Cycle-to-cycle jitter refers to time varying deviation of a single clock period.
 For a given spatial location, i is given as Tjitter, i(n) = Ti,n+1 – Ti,n – TCLK.

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Where Ti,n is the clock period for period n, Ti,n+1 is clock period for period n+1, and TCLK
is the nominal clock period.
 Jitter directly impacts the performance of a sequential system.
 Figure shows the nominal clock period as well as variation in period.

Figure: Circuit for studying the impact of jitter on performance.

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3.4 Pipelining:

 Explain in detail about pipelining structure needed for a logic operation. (April 2017, Nov 2017)
 Discuss in detail various pipelining approaches to optimize sequential circuits. (May 2013, 2016,
May 2021)[Apr/May 2022] [April / May 2023]
 Pipelining is a design technique used to accelerate the operation of the datapaths in digital
processors.
 The idea is explained with Figure 3.22a.
 The goal of the circuit is to compute log(|a - b|), where both a and b represent streams of
numbers.
 The minimal clock period Tmin necessary to ensure correct evaluation is given as:
Tmin  tcq  t pd ,logic  tsu
Where, tc-q and tsu are the propagation delay and the set-up time of the register respectively.
 Registers are edge-triggered D registers.
 The term tpd,logic stands for the worst-case delay path through the combinatorial network,
which consists of the adder, absolute value and logarithm functions.
 In conventional systems, the delay is larger than the delays associated with the registers and
dominates the circuit performance.
 Assume that each logic module has an equal propagation delay.
 Each logic module is then, active for only 1/3 of the clock period.
 Pipelining is a technique to improve the resource utilization and increase the functional
throughput.
 Introduce registers between the logic blocks, as shown in Figure 3.22b.

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 This causes the computation for one set of input data to spread over a number of clock
periods, as shown in Table 1.
 The result for the data set (a1, b1) only appears at the output after three clock-periods.

Figure 3.22 Data path for the computation of log(|a + b|).

 At that time, the circuit has already performed parts of the computations for the next data
sets, (a2, b2) and (a3, b3).
 The computation is performed in an assembly-line fashion, hence the name pipeline.
 The combinational circuit block has been partitioned into three sections, each of which has
a smaller propagation delay than the original function.
 This reduces the value of the minimum allowable clock period:
Tmin, pipe  tcq  max(t pd ,add , t pd ,abs , t pd ,log )
 Suppose all logic blocks have same propagation delay and that the register overhead is
small with respect to the logic delays.

Table 1: Example of pipelined computations.

 The pipelined network performs the original circuit by a factor of three, under these
assumptions Tmin,pipe=Tmin/3.
 The increased performance comes at the relatively small cost of two additional registers,
and an increased latency.
 Pipelining is implemented for very high-performance datapaths.

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3.4.1 NORA-CMOS—A Logic Style for Pipelined Structures:
Discuss about the NORA–CMOS structure. (Nov 2016)

 The latch-based pipeline circuit can also be implemented using C2MOS latches, as shown
in Figure 3.24.
 This topology has one additional property:
 A C2MOS-based pipelined circuit is race-free as long as all the logic functions F
(implemented using static logic) between the latches are noninverting.

Figure 3.24 Pipelined datapath using C2MOS latches

 The only way, a signal can race from stage to stage under this condition is, when the logic
function F is inverting, as in Figure 3.25.
 Here F is replaced by a single, static CMOS inverter. Similar considerations are valid for
the (1-1) overlap.
 It combines C2MOS pipeline registers and NORA dynamic logic function blocks.
 Each module consists of a block of combinational logic, that can be a mixture of static and
dynamic logic, followed by a C2MOS latch.

Figure 3.25 Potential race condition during (0-0) overlap in C2MOS-based design.
 Logic and latch are clocked, in such a way that both are simultaneously in either evaluation
or hold (precharge) mode.
 A block that is, in evaluation during CLK = 1 is called a CLK-module, while the inverse is
called a CLK -module.
 The operation modes of the modules are summarized in Table 2.

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Table 2: Operation modes for NORA logic modules.

3.4.2 Latch- vs. Register-Based Pipelines:

Compare Latch and register based pipelines.

 Pipelined circuits can be constructed using level-sensitive latches instead of edge-triggered

registers.
 Consider the pipelined circuit of Figure 3.23.
 The pipeline system is implemented based on pass-transistor-based positive and negative
latches instead of edge triggered registers.
 Here logic is introduced between the master and slave latches of a master-slave system.
 When the clocks CLK and CLK are non-overlapping, correct pipeline operation is
obtained.
 Input data is sampled on C1 at the negative edge of CLK and the computation of logic
block F starts.
 The result of the logic block F is stored on C2 on the falling edge of CLK and the
computation of logic block G starts.
 The non-overlapping of the clocks ensures correct operation.
 The value stored on C2 at the end of the CLK low phase, is the result of passing the
previous input through the logic function F.
 When overlap exists between CLK and CLK , the next input is already being applied to F,
and its effect might propagate to C2 before CLK goes low.

Figure 3.23 Operation of two-phase pipelined circuit using dynamic registers.

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3.5 Choosing a Clocking Strategy:

Discuss about strategy required for choosing a clock signal.

 Choosing the right clocking scheme affects the functionality, speed and power of a circuit.
 The simple clocking scheme is the two-phase master-slave design.
 The predominant approach is use the multiplexer-based register and to generate the two
clock phases locally, by simply inverting the clock.
 High-performance CMOS VLSI design is using simple clocking schemes, even at the
expense of performance.

3.5.1 Static sequencing element methodology:-

 Many issues are related to static sequencing element methodology.
(a) Choice of element:-

Flip-flop: Flip-flop has high sequencing overhead. It is simple and easy to understand the
operation of flip-flop.
Pulsed latches:-
 Faster than flip-flop.
 Provides some time borrowing option.
 Consumes law power.
Transparent Latch:-
 It has low sequencing overhead compared with flip-flop.
 It allows almost half cycle of time borrowing and it is good choice.

(b)Low power sequential design:-

 Pulsed latches are power efficient.
 Flip-flop consumes more power.
 Clock gating can be used to reduce power.
(c) Two-phase Timing types:-In this type, the signal can belong to phase 1 (or) phase 2. In each
phase, 3 different clocks are stable, valid and qualified clock.
Stable clock:-
A signal is stable (in 𝜑1 ), if it settles to a value before rises and remains constant until
after, 𝜑1falls.
Valid clock: - A signal is valid (in𝜑1), if it settles to a value before 𝜑1falls and remains at that
value after 𝜑1 falls.
Qualified signal: -A signal is said to be in qualified clock in𝜑1 , if it either rises and falls like
𝜑1(or) remains low for the entire cycle.

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3.6 Synchronous and Asynchronous circuits-Timing issues:

 A synchronous system approach is one, in which all memory elements in the system are
simultaneously updated using a globally distributed periodic synchronization signal.
 Functionality is ensured by imposing some strict constraints on the generation of the clock
signals and their distribution to the memory elements.
 Analyze the impact of spatial variations of the clock signal, called clock skew and temporal
variations of the clock signal, called clock jitter.
 Asynchronous design avoids the problem of clock uncertainty by eliminating the need for
globally-distributed clocks.
 The important issues of synchronization, which is required when interfacing different clock
domains or when sampling an asynchronous signal.
Classification of Digital Systems:
 In digital systems, signals can be classified depending on, how they are related to a local
clock.
 Signals that transition only at predetermined periods in time can be classified as
synchronous, mesochronous and plesiochronous with respect to a system clock.
 A signal that can transition at arbitrary times is considered asynchronous.
3.6.1 Synchronous Interconnect
 A synchronous signal has the exact same frequency and a known fixed phase offset with
respect to the local clock.
 In such a timing methodology, the signal is “synchronized” with the clock and the data can
be sampled directly without any uncertainty.
 In digital logic design, synchronous systems are straight forward type of interconnect,
where the flow of data in a circuit proceeds with the system clock as shown below.

3.6.2 Mesochronous interconnect:

 A mesochronous signal has the same frequency but an unknown phase offset with respect
to the local clock (“meso” from Greek is middle).
 For example, if data is being passed between two different clock domains, then the data
signal transmitted from the first module can have an unknown phase relationship to the
clock of the receiving module.
 In such a system, it is not possible to directly sample the output at the receiving module
because of the uncertainty in the phase offset.
 A (mesochronous) synchronizer can be used to synchronize the data signal with the
receiving clock as shown below.

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 The synchronizer serves to adjust the phase of the received signal to ensure proper
sampling.

3.6.3 Plesiochronous Interconnect

 A plesiochronous signal has nominally the same, but slightly different frequency as the
local clock (“plesio” from Greek is near).
 This scenario can easily arise when two interacting modules have independent clocks
generated from separate crystal oscillators.
 Since the transmitted signal can arrive at the receiving module at a different rate than the
local clock, one need to utilize a buffering scheme to ensure, all data is received.
 A possible framework for plesiochronous interconnect is shown in Figure below.

3.6.4 Asynchronous Interconnect:

 Asynchronous signals can transition at any arbitrary time and are not slaved to any local
clock.
 As a result, it is not to map these arbitrary transitions into a synchronized data stream.
 Asynchronous signals are used to eliminate the use of local clocks and utilize a self-timed
asynchronous design approach.
 In this approach, communication between modules is controlled through a handshaking
protocol.

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3.7 Clock-Distribution Techniques

 Explain the clock distribution techniques in synchronous design in detail. (Nov 2017)
 Design a clock distribution network based on H tree model for 16 nodes. (April 2018)

 Clock skew and jitter are major issues in digital circuits and they limit the performance of a
digital system.
 It is necessary to design a clock network, that minimizes skew and jitter.
 Another important consideration in clock distribution is the power dissipation.
 In most high-speed digital processors, a majority of the power is dissipated in the clock
network.
 To reduce power dissipation, clock networks must support clock conditioning, the ability to
shut down parts of the clock network.
 Unfortunately, clock gating results in additional clock uncertainty.
Fabrics for clocking:
 Clock networks include a network that is used to distribute a global reference to various
parts of the chip.
 A final stage is responsible for local distribution of the clock, while considering the local
load variations.
 Most clock distribution schemes use the absolute delay from a central clock source to the
clocking elements.
 Therefore one common approach to distributing a clock is, to use balanced paths (or called
trees).
 The most common type of clock primitive is, the H-tree network (named for the physical
structure of the network) in figure, where a 4x4 array is shown.
 In this scheme, the clock is routed to a central point on the chip and balanced paths.
 Include both matched interconnect as well as buffers, are used to distribute the reference to
various leaf nodes.
 If each path is balanced, the clock skew is zero. It takes multiple clock cycles for a signal to
propagate from the central point to each leaf node. The arrival times are equal at every leaf
node.
 The H-tree configuration is particularly useful for regular-array networks, in which all
elements are identical and the clock can be distributed as a binary tree.

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Figure: Example of an H-tree clock-distribution network for 16 leaf nodes.

Latch-Based Clocking:
 The use of a latch based methodology (in Figure) enables more flexible timing, allowing
one stage to pass slack to or steal time from following stages.
 This flexibility allows an overall performance increase.
 In this configuration, a stable input is available to the combinational logic block A
(CLB_A) on the falling edge of CLK1 (at edge2).
 On the falling edge of CLK2 (at edge3), the output CLB_A is latched and the computation
of CLK_B is launched.
 CLB_B computes on the low phase of CLK2 and the output is available on the falling edge
of CLK1 (at edge4).
 This timing appears, equivalent to having an edge-triggered system where CLB_A and
CLB_B are cascaded and between two edge-triggered registers.
 In both cases, it appears that the time available to perform the combination of CLB_A and
CLB_B are TCLK.

Figure: Latch-based design in which transparent latches are separated by combinational logic.
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3.8 Self-Timed Circuit Design

Discuss about asynchronous design in logic design.

3.8.1 Self-Timed Logic : An Asynchronous Technique

 A more reliable and robust technique is the self-timed approach, which presents a local
solution to the timing problem.
 Figure uses a pipelined datapath to illustrate how this can be accomplished.
 The computation of a logic block is initiated by asserting a Start signal.
 The combinational logic block computes on the input data.
 This signaling ensures the logical ordering of the events and can be achieved with the aid
of an extra Ack(nowledge) and Req(uest) signal.

Figure: Self-timed, pipelined datapath.

In the case of the pipelined datapath, the scenario could proceed as follows.
1. An input word arrives, and a Req(uest) to the block F1 is raised. If F1 is inactive at that time,
it transfers the data and acknowledges this fact to the input buffer.
2. F1 is enabled by raising the Start signal. After a certain amount of time, dependent upon the
data values, the Done signal goes high indicating the completion of the computation.
3. A Req(uest) is issued to the F2 module. If this function is free, an Ack(nowledge) is raised, the
output value is transferred and F1 can go ahead with its next computation.

3.8.2 A simple synchronizer

How do eliminates metastability problem in sequential circuit and explain?

 A synchronizer accepts an input D and a clock ф. It produces an output Q that should be

valid for some bounded delay after the clock.
 The synchronizer has an aperture, defined by a setup and hold time around the rising edge
of the clock.

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 If the data is stable during the aperture, Q should equal D. If the data changes during the
aperture, Q can be chosen arbitrarily.

Figure: Simple Synchronizer

 Figure shows a simple synchronizer built from a pair of flip-flops. F1 samples the
asynchronous input D.
 The output X may be metastable for some time, but will settle to a good level with high
probability, if we wait long enough.
 F2 samples X and produce an output Q, that should be a valid logic level and be aligned
with the clock.
 The synchronizer has a latency of one clock cycle Tc .

3.8.3 Communicating between asynchronous clock domains

 A common application of synchronizers is in communication between asynchronous
clock domains, i.e., blocks of circuits that do not share a common clock.
 Suppose System A is controlled by clkA that needs to transmit N-bit data words to
System B, which is controlled by clkB, as shown in Figure.
 The systems can represent separate chips or separate units within a chip using unrelated
clocks.
 System A must guarantee that the data is stable, while the flip-flops in System B sample
the word.
 It indicates when new data is valid by using a request signal (Req), so System B receives
the word exactly once rather than zero or multiple times.
 System B replies with an acknowledge signal (Ack), when it has sampled the data, so
System A knows when the data can safely be changed.
 If the relationship between clkA and clkB is completely unknown, a synchronizer is
required at the interface.

Figure: Communication between asynchronous systems

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3.8.4 Arbiter
 The arbiter of Figure (a) is related to the synchronizer. It determines which of two inputs
arrived first.
 If the spacing between the inputs exceeds some aperture time, the first input should be
acknowledged.
 If the spacing is smaller, exactly one of the two inputs should be acknowledged, but the
choice is arbitrary.
 For example, in a television game show, two contestants may hit buttons to answer a
question.
 If one presses the button first, should be acknowledged. If both presses the button at
times too close to distinguishes, the host may choose one of the two contestants
arbitrarily.

Figure: Arbiter
 Figure (b) shows an arbiter built from an SR latch and a four-transistor metastability
filter.
 If one of the request inputs arrives well before the other, the latch will respond
appropriately.
 If they arrive at nearly the same time, the latch may be driven into metastability, as
shown in Figure (c).
 The filter keeps both acknowledge signals low, until the voltage difference between the
internal nodes n1 and n2 exceeds Vt , indicating that a decision has been made.
 Such an asynchronous arbiter will never produce metastable outputs.

3.8.5 Synchronous versus Asynchronous Design:

Compare synchronous and asynchronous design.

 The self-timed approach offers a potential solution to the growing clock-distribution

problem.
 It translates the global clock signal into a number of local synchronization problems.

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 Handshaking logic is needed to ensure the logical ordering of the circuit events and to
avoid race conditions.
 In general, synchronous logic is both faster and simpler since the overhead of completion-
signal generation and handshaking logic is avoided.
 Skew management requires extensive modeling and analysis, as well as careful design.
 It will not be easy to extend this methodology into the next generation of designs.
 This observation is already reflected in the fact that the routing network for the latest
generation of massively parallel supercomputers is completely implemented using self-
timing.
 For self timing to become a mainstream design technique however (if it ever will), further
innovations in circuit and signaling techniques and design methodologies are needed.
*****************************************************************************
3.9 Pulse Registers

Design the pulse registers suitable for sequential CMOS circuits. [May 2021][Nov/Dec 2022]

 A fundamentally different approach for constructing a register uses pulse signals.

 The idea is to construct a short pulse around the rising (or falling) edge of the clock.
 This pulse acts as the clock input to a latch, sampling the input only in a short window.
 Race conditions are thus avoided by keeping the opening time (i.e, the transparent period)
of the latch very short.
 The combination of the glitch generation
circuitry and the latch results in a positive
edge-triggered register.

 Figure b shows an example circuit for constructing a short intentional glitch on each
rising edge of the clock.
 When CLK = 0, node X is charged up to VDD (MN is off since CLKG is low).
 On the rising edge of the clock, there is a short period of time when both inputs of the
AND gate are high, causing CLKG to go high.

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 This in turn activates MN, pulling X and eventually CLKG low.
 The length of the pulse is controlled by the delay of the AND gate and the two inverters.
 Note that there exists also a delay between the rising edges of the input clock (CLK) and
the glitch clock (CLKG) — also equal to the delay of the AND gate and the two
inverters.
 If every register on the chip uses the same clock generation mechanism, this sampling
delay does not matter.
 However, process variations and load variations may cause the delays through the glitch
clock circuitry to be different.
 This must be taken into account when performing timing verification and clock skew
analysis.

Waveform

 If set-up time and hold time are measured in reference to the rising edge of the glitch
clock, the set-up time is essentially zero, the hold time is equal to the length of the pulse
(if the contamination delay is zero for the gates), and the propagation delay (tc-q) equals
two gate delays.

Advantage

 The reduced clock load and the small number of transistors required.
 The glitch-generation circuitry can be amortized over multiple register bits.

Disadvantage

 A substantial increase in verification complexity.

 This has prevented a wide-spread use.

3.10 Sense-Amplifier Based Registers

Write short notes on Sense – Amplifier Based Registers. [Nov/Dec 2022][April/May 2023]

 A sense amplifier structure to implement an edge- triggered register.

 Sense amplifier circuits accept small input signals and amplify them to generate rail-to-
rail swings.
 There are many techniques to construct these amplifiers, with the use of feedback (e.g.,
cross-coupled inverters).

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Positive edge-triggered register based on sense-amplifier

 The circuit uses a precharged front-end amplifier that samples the differential input signal
on the rising edge of the clock signal.
 The outputs of front-end are fed into a NAND cross- coupled SR FF that holds the data
and guarantees that the differential outputs switch only once per clock cycle.
 The differential inputs in this implementation don’t have to have rail-to-rail swing and
hence this register can be used as a receiver for a reduced swing differential bus.

Operation
 The core of the front-end consists of a cross-coupled inverter (M5-M8) whose outputs
(L1 and L2) are precharged using devices M9 and M10 during the low phase of the clock.
 As a result, PMOS transistors M7 and M8 to be turned off and the NAND FF is holding
its previous state.
 Transistor M1 is similar to an evaluate switch in dynamic circuits and is turned off
ensuring that the differential inputs don’t affect the output during the low phase of the
clock.
 On the rising edge of the clock, the evaluate transistor turns on and the differential input
pair (M2 and M3) is enabled, and the difference between the input signals is amplified on
the output nodes on L1 and L2.
 The cross-coupled inverter pair flips to one of its the stable states based on the value of
the inputs.
 For example, if IN is 1, L1 is pulled to 0, and L2 remains at VDD. Due to the amplifying
properties of the input stage, it is not necessary for the input to swing all the way up to
VDD and enables the use of low swing signaling on the input wires.

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 The shorting transistor, M4, is used to provide a DC leakage path from either node L3, or
L4, to ground.
 This is necessary to accommodate the case where the inputs change their value after the
positive edge of CLK has occurred, resulting in either L3 or L4 being left in a high-
impedance state with a logical low voltage level stored on the node.
 Without the leakage path that node would be susceptible to charging by leakage currents.

3.11 Schmitt Trigger

Explain the circuit and working of CMOS implementation of Schmitt Trigger. (NOV 2021)
[Nov/Dec 2022]

 A Schmitt trigger is a device with two important properties:

1. It responds to a slowly changing input waveform with a fast transition time at the
output.
2. The voltage-transfer characteristic of the device displays different switching thresholds
for positive- and negative-going input signals.

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A typical voltage-transfer characteristic of the Schmitt trigger is shown (and its
schematics symbol). The switching thresholds for the low-to-high and high to-low
transitions are called VM+ and VM−, respectively. The hysteresis voltage is defined as the
difference between the two.

Fig: Non-inverting Schmitt trigger.

 One of the main uses of the Schmitt trigger is to turn a noisy or slowly varying input
signal into a clean digital output signal.
 Notice how the hysteresis suppresses the ringing on the signal.
 At the same time, the fast low-to-high (and high-to-low) transitions of the output signal
should be observed.
 For instance, steep signal slopes are beneficial in reducing power consumption by
suppressing direct-path currents.
 The “secret” behind the Schmitt trigger concept is the use of positive feedback.

CMOS Implementation
 Increasing kn/kp ratio decreases the logical switching threshold
 If V in =0 the V out (connected to M 4 ) is also zero So effectively the input is connected to
M 2 and M 4 in parallel This increases kp and the switching threshold

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 If V in =0 the situation is reversed and kn increases reducing the switching threshold

 Suppose that Vin is initially equal to 0, so that Vout = 0 as well.

 The feedback loop biases the PMOS transistor M4 in the conductive mode while M3 is
off.
 The input signal effectively connects to an inverter consisting of two PMOS transistors in
parallel (M2 and M4) as a pull-up network, and a single NMOS transistor (M1) in the pull-
down chain.
 This modifies the effective transistor ratio of the inverter to kM1/(kM2+kM4), which moves
the switching threshold upwards.
 Once the inverter switches, the feedback loop turns off M4, and the NMOS device M3 is
activated.
 This extra pull-down device speeds up the transition and produces a clean output signal
with steep slopes.
 A similar behavior can be observed for the high-to-low transition.
 In this case, the pull-down network originally consists of M1 and M3 in parallel, while the
pull-up network is formed by M2.
 This reduces the value of the switching threshold to VM–.

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3.12 Multivibrator Circuits

Explain about Monostable and Astable Sequential Circuits. [Apr/May 2022] [Nov/Dec 2022]
Sketch and explain the Monostable sequential circuits based on CMOS logic. (May 2021)
[April / May 2023]

Sequential circuits are of three types −

Bistable − Bistable circuits have two stable operating points and will be in either of the states.
Example − Memory cells, latches, flip-flops and registers.
Monostable − Monostable circuits have only one stable operating point and even if they are
temporarily perturbed to the opposite state, they will return in time to their stable operating
point. Example: Timers, pulse generators.
Astable − circuits have no stable operating point and oscillate between several states.
Example − Ring oscillator.

Transition-Triggered Monostable Sequential Circuits

 A monostable element is a circuit that generates a pulse of a predetermined width every

time the quiescent circuit is triggered by a pulse or transition event.
 It is called monostable because it has only one stable state (the quiescent one).
 A trigger event, which is either a signal transition or a pulse, causes the circuit to go
temporarily into another quasi-stable state.
 This means that it eventually returns to its original state after a time period determined by
the circuit parameters.
 This circuit, also called a one-shot, is useful in generating pulses of a known length.

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 This functionality is required in a wide range of applications.
 We have already seen the use of a one-shot in the construction of glitch registers.
 Another notorious example is the address transition detection (ATD) circuit, used for the
timing generation in static memories.
 This circuit detects a change in a signal, or group of signals, such as the address or data
bus, and produces a pulse to initialize the subsequent circuitry.
 The most common approach to the implementation of one-shots is the use of a simple
delay element to control the duration of the pulse.
 In the quiescent state, both inputs to the XOR are identical, and the output is low.
 A transition on the input causes the XOR inputs to differ temporarily and the output to go
high.
 After a delay t d (of the delay element), this disruption is removed, and the output goes
low again.
 A pulse of length td is created.
 The delay circuit can be realized in many different ways, such as an RC-network or a
chain of basic gates.

Fig: Transition-triggered one-shot.

3.13 Astable Sequential Circuits

 An astable circuit has no stable states.
 The output oscillates back and forth between two quasi-stable states with a period
determined by the circuit topology and parameters (delay, power supply, etc.).
 One of the main applications of oscillators is the on-chip generation of clock signals.
 This application is discussed in detail in a later chapter (on timing). The ring oscillator is
a simple, example of an astable circuit.
 It consists of an odd number of inverters connected in a circular chain.
 Due to the odd number of inversions, no stable operation point exists, and the circuit
oscillates with a period equal to 2 × tp × N, with N the number of inverters in the chain
and tp the propagation delay of each inverter.
 The ring oscillator composed of cascaded inverters produces a waveform with a fixed
oscillating frequency determined by the delay of an inverter in the CMOS process.

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 In many applications, it is necessary to control the frequency of the oscillator.
 An example of such a circuit is the voltage-controlled oscillator (VCO), whose oscillation
frequency is a function (typically non-linear) of a control voltage.
 The standard ring oscillator can be modified into a VCO by replacing the standard
inverter with a current-starved inverter as shown in Figure.
 The mechanism for controlling the delay of each inverter is to limit the current available
to discharge the load capacitance of the gate.
 In this modified inverter circuit, the maximal discharge current of the inverter is limited
by adding an extra series device.
 Note that the low-to-high transition on the inverter can also be controlled by adding a
PMOS device in series with M2.
 The added NMOS transistor M3, is controlled by an analog control voltage Vcntl, which
determines the available discharge current.
 Lowering Vcntl reduces the discharge current and, hence, increases tpHL.
 The ability to alter the propagation delay per stage allows us to control the frequency of
the ring structure.
 The control voltage is generally set using feedback techniques.
 Under low operating current levels, the current-starved inverter suffers from slow fall
times at its output. This can result in significant short-circuit current.
 This is resolved by feeding its output into a CMOS inverter or better yet a Schmitt
trigger.
 An extra inverter is needed at the end to ensure that the structure oscillates.

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UNIT – III
SEQUENTIAL LOGIC CIRCUITS AND CLOCKING STRATEGIES
1. What is a Sequential circuit?
In sequential circuits, the output depends on previous as well as current inputs.

2. What are sequencing methods available in sequential circuit design? (NOV/DEC-2012)

The sequencing methods available in sequential circuit design are,
i. Flipflop
ii. Two phase transparent latches
iii. Pulsed latches

3. What is meant by maximum delay or setup time failure and how to avoid?
If the combinational logic delay is too high, the receiving element will miss its setup
time and sample the wrong value. This is called a setup time failure or max-delay failure. Max-
delay can be solved by redesigning the logic to be faster or by increasing the clock period.

4. Define sequencing overhead.

Sequencing overhead is defined as an additional delay to Tokens (Data) that are already
critical, decreasing the performance of the system. This extra delay is called sequencing
overhead.

5. What is meant by Min-delay failure and how to avoid?

If the hold time is large and the contamination delay is small, data can incorrectly
propagate through two successive elements on one clock edge, corrupting the state of the system.
This is called a race condition, hold-time failure, or min-delay failure.
Min-delay can only be fixed by redesigning the logic, not by slowing the clock.

6. Define time borrowing.

Time borrowing is defined as if one half-cycle or stage of a pipeline has too much logics,
it can borrow time into the next half-cycle or stage.
Time borrowing can accumulate across multiple cycles.

7. Define clock skew. (April 2018, April 2019, NOV 2021)[Apr/May 2022]
Clocks have some uncertainty in their arrival times that can cut into the time available for
useful computation.

8. How to design CMOS flip-flop?

Dynamic inverting flip-flop built from a pair of back-to-back dynamic latches.

9. How to design Semidynamic Flip-flop?

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Semidynamic flip-flop (SDFF) is a cross coupled between a pulsed latch and a flip-flop.

10. What is meant by semidynamic flip-flop(SDFF)?

The SDFF accepts rising inputs slightly after the rising clock edge. Like a flip-flop,
falling inputs must set up before the rising clock edge called as semidynamic. It combines the
dynamic input stage with static operation.

11. What is meant by Differential flip-flop?

Differential flip-flops accept true and complementary inputs and produce true and
complementary outputs. They are built from a clocked sense amplifier so that they can respond
to small differential input voltages.

12. What is meant by True Single Phase Clock (TSPC) Latch or flip-flop?
True Single Phase clock Latch or flipflop avoids complementary clock pulse.

13. What are sequencing dynamic circuits?

Sequencing dynamic circuits are
i. Traditional domino circuit
ii.Skew tolerant domino circuit

14. Define Synchronizer. (MAY/JUE-2014)

Synchronizer is defined as a circuit that accepts an input that can change at arbitrary
times and produces an output aligned to the synchronizer’s clock.

15. What is a Latch? (NOV/DEC-2014)

Latch is a bistable device. i.e., it has two stable states (0 and 1). It is the level triggering
method.

16. What is a flip-flop? (NOV/DEC-2014)

Flip-flop is a bistable device. i.e., it has two stable states (0 and 1). It is the edge
triggering method.

17. What is meant by Bistability and metastability? (NOV 2021) [Apr/May 2022]
A latch is a bistable device. i.e., it has two stable states (0 and 1). Latch can enter a
metastable state in which the output is at an indeterminate level between 0 and 1.

18. Define aperture.

Aperture is defined as a setup and hold time around the rising edge of the clock.

19. How to design simple synchronizer circuit.

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Simple synchronizer built from a pair of flip-flops. F1 samples the asynchronous input D.
The output X may be metastable for some time, but will settle to a good level with high
probability.

20. What is meant by Arbiter?

The arbiter is closely related to the synchronizer. It determines which of two inputs
arrived first.
If the spacing between the inputs exceeds some aperture time, the first input should be
acknowledged.
If the spacing is smaller, exactly one of the two inputs should be acknowledged, but the
choice is arbitrary.

21. What are the advantages of differential Flip flop? (Nov 2011)
The advantages of differential Flip flops are
a. Reduce the parasitic delay of the pull down networks.
b. Lower electric fields across the pull down networks.
c. It reduces the channel length of the transistors.

22. State the reasons for the speed advantages of CVSL family. (Nov 2012, Nov 2014)
CVSL has a potential speed advantage because all of the logic is performed with nMOS
transistors, thus reducing the input capacitance.

23. Enumerate the features of synchronizers. (May 2013)

The features of synchronizers are,
a. A good synchronizer should have a feedback loop with high gain bandwidth product.
b. It can produce metastable output.

24. What are the disadvantages of using a pseudo nMOS gate instead of a full CMOS gate?
(May 2012)
Ratioed circuits dissipate power continually in certain states and have poor noise margin
than complementary circuits. Ratioed circuits used in situations where smaller area is needed.

25. What is Klass-semidynamic flip-flop?

Klass-semidynamic is a single-input single-output positive edge-triggered flip-flop. It is
domino-style from end allows for efficient embedded combinational logic and reduces the load
on the data network.

26. What are the different phases of VLSI design flow?

The different phases of VLSI design flows are,
 Function Verification and testing, logic synthesis/Timing verification
 Logical verification and testing

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 Floor planning automatic place and route
 Layout verification
 Implementation

27. Draw the circuit diagram of a CMOS bistable element and its time domain behavior.
(APRIL/MAY-2011)

28. What is CMOS clocked SR flipflop?

CMOS Clocked SR flip-flop consists of a cross-coupled inverter pair, plus 4 extra
transistors to drive the flip-flop from one state to another and to provide clocked operation.

29. What do mean by multiplexer based latches?

Multiplexer based latches can provide similar functionality to the SR latch, but has the
important added advantage that the sizing of devices only affects performance and is not critical
to the functionality.

30. What is Master-Slave Based Edge Triggered Register?

The register consists of cascading a negative latch (master stage) with a positive latch
(slave stage).

31. What is the advantage of multiplexer based latch?

The advantage of the multiplexer-based register is the feedback loop is open during the
sampling period, and sizing of devices is not critical to functionality.

32. What is pseudostatic?

The register employs a combination of static and dynamic storage approaches depending
upon the state of the clock.

33. What is called Clocked CMOS Register? (May 2016)

C2MOS is a positive edge-triggered register based on the master-slave concept which is
insensitive to clock overlap. The register operates in two phases.

34. What is meant by Dual-edge Triggered Register? Give it advantage.

Dual-edge triggered register is a design of sequential circuits that sample the input on
both edges. The advantage of this scheme is that a lower frequency clock.

35. What is True Single-Phase Clocked Register (TSPCR)?

The True Single-Phase Clocked Register (TSPCR) uses a single clock (without an inverse
clock).

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36. What is the advantage and disadvantage of True Single-phase clocked register?
The main advantage is the use of a single clock phase. The disadvantage is the increase
the number of transistors. 12 transistors are required.

37. What is pipelining? (Dec. 2016, April 2017)

Pipelining is a popular design technique used to accelerate the operation of the datapaths
in digital processors.

38. What is necessary of non-overlapping clocks?

The non-overlapping of the clocks ensures correct operation. When CLK and CLK
signals are non-overlapping, correct pipeline operation is obtained.

39. What is topology for NORA-CMOS?(Nov 2017)

The latch-based pipeline circuit implemented using C2MOS latch is known as NORA-
CMOS circuit. A NORA CMOS circuit is race-free as long as all the logic functions between the
latches are non-inverting.

40. Tabulate the operation modules of NORA-CMOS circuit.

41. Define the dynamic-logic rule.

Inputs to a dynamic CLKn (CLKp) block are only allowed to make a single 01 (1  0)
transition during the evaluation period.

42. Define C2MOS design rule.

C2MOS design rule is defining to avoid races, the number of static inversions between
2
C MOS latches should be even.

43. Draw the switch level schematic of multiplexer. (May 2016)

44. What is known as H-tree clock distribution?

The H-tree configuration is useful for regular-array networks in which all elements are
identical and the clock can be distributed as a binary tree. For example, arrays of identical tiled
processors.

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45. Define clock jitter. (Nov 2017)[Apr/May 2022]
Clock jitter refers to the temporal variation of the clock period at a given point. i.e, the
clock period can reduce or expand on a cycle-by-cycle basis.

46. What is meant by Latch based clocking?

Use of registers in sequential circuits enables a robust design methodology. Advantage is
combinational logic is separated by transparent latches.

47. Compare synchronous and asynchronous design. (April 2017)

Synchronous design Asynchronous design
Synchronous logic is both faster and Asynchronous logic is slow and complex.
simpler.
Distributing a clock at high speed Distributing a clock at high speed
becomes exceedingly difficult. becomes easy.

48. Define Set up time and hold time. (Nov 2019)

The setup time is the interval before the clock where the data must be held stable.

The hold time is the interval after the clock where the data must be held stable. Hold time
can be negative, which means the data can change slightly before the clock edge and still be
properly captured. Most of the current day flip-flops has zero or negative hold time.

49. Draw the circuit and wave form for Pulse Registers.

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50. Define Pulse Registers.

The idea is to construct a short pulse around the rising (or falling) edge of the clock.
This pulse acts as the clock input to a latch, sampling the input only in a short window.
Race conditions are thus avoided by keeping the opening time (i.e, the transparent period)
of the latch very short.
The combination of the glitch generation circuitry and the latch results in a positive edge-
triggered register.
51. List the advantage and disadvantage of Pulse Registers.
Advantage
 The reduced clock load and the small number of transistors required.
 The glitch-generation circuitry can be amortized over multiple register bits.
Disadvantage
 A substantial increase in verification complexity.
 This has prevented a wide-spread use.
52. What is Sense – Amplifier Based Registers?
 A sense amplifier structure to implement an edge- triggered register.
 Sense amplifier circuits accept small input signals and amplify them to generate rail-to-
rail swings.
 There are many techniques to construct these amplifiers, with the use of feedback (e.g.,
cross-coupled inverters).
53. Draw the circuit of Sense – Amplifier Based Registers.

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54. Differentiate between latch and flip-flop. (Nov 2015) (Nov 2019) [May 2021]
Compare register and latch. (April 2018) [April / May 2023]
Latch is a bistable device. i.e., it has two stable states. It is the level triggering method.
Flip-flop is a bistable device. i.e., it has two stable states. It is the edge triggering method.
Register has number of flipflops.
55. Define Schmitt trigger.
A Schmitt trigger is a device with two important properties:
1. It responds to a slowly changing input waveform with a fast transition time at the
output.
2. The voltage-transfer characteristic of the device displays different switching thresholds
for positive- and negative-going input signals.
56. Draw the symbol, circuit and voltage transfer characteristics of Schmitt trigger.

57. Define Astable sequential circuits. Draw the circuit also. [April / May 2023]
 An astable circuit has no stable states.
 The output oscillates back and forth between two quasi-stable states with a period
determined by the circuit topology and parameters (delay, power supply, etc.).
 One of the main applications of oscillators is the on-chip generation of clock signals.

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58. Define Monostable sequential circuits. [April / May 2023]
Monostable − Monostable circuits have only one stable operating point and even if they
are temporarily perturbed to the opposite state, they will return in time to their stable
operating point. Example: Timers, pulse generators.

59. State the use of Schmitt trigger.[Nov/Dec 2022]

Schmitt triggers can be used to change a sine wave into a square wave, clean up noisy
signals, and convert slow edges to fast edges.
60. Draw a MUX based negative level sensitive D-latch. [Nov/Dec 2022]

61. List the timing classification of Digital system. [May 2021]

Synchronous, mesochronous and plesiochronous with respect to a system clock.

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