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Low Power VLSI Circuits and Systems

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27 views

Low Power VLSI Circuits and Systems

Uploaded by

Saranya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Code: EC20APE703 R 20

B.Tech IV Year I Semester Regular Examinations Dec/Jan – 2023/2024


LOW POWER VLSI CIRCUITS AND SYSTEMS
(Electronics & Communication Engineering)
Time: 3 hrs. Max Marks: 60
PART-A
(Compulsory Question)
1. Answer the following 05 x 02 = 10 Marks
a) Why low power has become an important issue in the present-day VLSI circuit 2M
Realization?
b) How the noise margin is affected by voltage scaling? 2M
c) What are the reasons of Leakage Power dissipation? 2M
d) What is the effect of feature scaling on power dissipation? 2M
e) How multiple threshold voltages can be achieved in a circuit? 2M
PART-B
Answer All five Units 05 x 10 = 50 Marks
UNIT-I
2. a) Explain the three modes of operation of nMOS transistor. 5M
b) Explain about the drain current variations due to channel length modulation. 5M
OR
3. a) Derive the expression for Ids in saturation and active region 5M
b) Explain about the different methodologies for Low power. 5M
UNIT-II
4. a) Draw the ideal characteristics of a CMOS inverter and compare it with the actual 5M
Characteristics.
b) Differentiate the Inverters with different pull ups with neat diagrams. 5M
OR
5. Explain about Domino CMOS Circuits and NORA Logic 10 M
UNIT-III
6. a) What is the subthreshold leakage current? Briefly explain the mechanisms that 5M
affect subthreshold leakage current.
b) Briefly explain various sources of power dissipation. 5M
OR
7. a) Derive the expression for short-circuit power dissipation of a CMOS inverter. And 5M
also explain its variation for different load capacitances.
b) What is switching power dissipation? Explain How it can be minimized. 5M
UNIT-IV
8. a) List out the advantages of voltage scaling 5M
b) summarize the optimization procedures for low power dissipation at the algorithm 5M
and architecture level.
OR
9. a) Demonstrate the concept Adaptive Voltage scaling. 5M
b) What is multi-level voltage scaling (MVS) and Explain about the challenges in 5M
MVS.

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Code: EC20APE703 R 20
UNIT-V
10. a) Differentiate VTCMOS and MTCMOS approach. 5M
b) Explain Adiabatic charging and Adiabatic Amplification. 5M
OR
11. a) Why it is necessary to isolate the output of a power-gated block when applied to 5M
a non-power-gated block?
b) Distinguish between standby and run-time leakage power dissipation. 5M
*****

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