VLSI TESTING Requirements of testing:

Verification vs. Testing

Once design a product, is fabricated and tested, and if it • Verifies correctness of • Verifies correctness of
design. manufactured hardware.
fails the test, then there must be a cause for the failure:
• Performed by simulation, • Two-part process:
– the test was wrong, or hardware emulation, or – Test generation: software process
– the fabrication process was faulty, or formal methods. executed once during design
– the design was incorrect, or • Performed once prior to – Test application: electrical tests
– the specification had a problem. manufacturing. applied to hardware
• Responsible for quality of • Test application performed on every
Correctness and effectiveness of testing are
design. manufactured device.
important for quality products.
• No limit on the number of • Responsible for quality of
A good test process can weed out all bad Test points/test vectors devices.
products before they reach the user. Limited on number of test points/test
For VLSI, failing of good chips by tests is known as yield vectors based on I/O Pins
loss, which increases the cost of manufacturing

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Role of Testing Role of Testing

• The role of testing is to detect whether something went • If the test procedure is good and the product fails, then
wrong. we suspect the fabrication process, the design, or the
– Detection: determination of whether or not the device under specification.
test (DUT) has some fault. • A well-thought-out test strategy is crucial to the
• The role of diagnosis is to determine what went wrong, economical realization of products.
and where the process needs to be altered. • The benefits of testing are quality and economy.
– Diagnosis: identification of a specific fault that is present on – These two attributes are not independent and neither can
DUT. be defined without the other.
• Device characterization: determination and correction of • Quality means satisfying the user’s needs at a minimum
errors in design and/or test procedure. cost.

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Testing Principle How to test chips

How to test chips?
Binary patterns (or test vectors) are applied to the inputs of the
circuit. The response of the circuit is compared with the
expected response. The circuit is considered good if the
responses match. Obviously, the quality of the tested circuit
will depend upon the thoroughness of the test vectors.

Quality of the tested circuit will depend upon the thoroughness of the test vectors.
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VLSI Realization Process VLSI Testing

Customer’s need
• The arrows out of the
Determine requirements FMA block represent
the corrective actions
Write specifications Applied to the faulty
steps of the realization
process.
Design synthesis and Verification • Companies emphasize
on doing it right the first
Test development time, or pursuing the
Fabrication goal of zero defects.

Manufacturing test

Chips to customer VLSI realization process

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VLSI Testing Failure Mode Analysis

• The objective of design is to produce data necessary for • Failures are defects that reach a customer.
the next steps of fabrication and testing. • Procedures for diagnosing defects and finding their
• Important function of testing is the process diagnosis. causes are known as failure mode analysis.
– We must find what went wrong with each faulty chip, be it – Faulty chip analysis.
in design, in fabrication, or in testing. • Failing devices often show patterns of repeated failures.
– Or, we may have started with unrealizable specifications. • The causes of these failures can point to
• FMA uses different test types, including examination weaknesses (sensitivity to process variations) in
through optical and electron microscopes, to determine the design.
the failure cause and fix the process. • Information is useful for improving logic and
layout design rules.

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Introduction Design for Testability (DFT)

• Introduction to VLSI Testing • DFT refers to hardware design styles or added

hardware that reduces test generation complexity.
• Design for Testability • Test generation complexity increases exponentially with
the size of the circuit.
• VLSI Technology Trends
• Example: Test hardware applies tests to blocks A and B
• Types of Testing and to the internal bus; avoids test generation for
• Failure Patterns combined A and B blocks.
Internal
• Automated Test Equipment Logic bus Logic PO
• Testing Economics PI block A block B

Test Test
input output

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 Benefits and Costs of DFT
• Consider life-cycle cost; DFT on the chip may impact the
Level Design Fabri- Manuf. Maintenance Diagnosis Service
costs at board and system levels. and test cation Test test and repair interruption
• Weigh costs against benefits:
• Cost examples: reduced yield due to area overhead, yield
Chips +/- + -
loss due to non-functional tests.
• Benefit examples: reduced automatic test equipment
(ATE) cost due to self-test, inexpensive alternatives to the Boards +/- + - -
burn-in test.
• A DFT or test method should be selected to improve the
System +/- + - - - -
product quality with minimal increase in cost due to area
overhead and yield loss. + Cost increase
- Cost saving
+/- Cost increase may balance cost reduction

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Introduction VLSI Technology Trends

Affecting Testing
• Introduction to VLSI Testing The complexity of VLSI technology has reached the point
• Design for Testability where we are trying to put 100 million transistors on a
single chip, and we are trying to increase the on-chip
• VLSI Technology Trends clock frequency to 1 GHz.
Trends have a profound effect on the cost and difficulty of
• Types of Testing chip testing.

• Failure Patterns
• Automated Test Equipment
• Testing Economics

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VLSI Technology Trends Affecting

Types of Testing
Testing
• Rising Chip Clock Rates: The exponentially rising clock • VLSI testing can be classified into four types depending on the
specific purpose it accomplishes:
rate indicates several changes in testing over the next 10 1. Characterization
years: • Design debug or verification testing
• Determines the exact limits of device operating values
1. At-Speed testing 2. Production
• Enforce the quality requirements by determining whether the
2. Automatic Test Equipment (ATE) cost
device meets the specifications
3. Electromagnetic Interference (EMI) 3. Burn-in
• Increasing Transistor Density • Ensures reliability of tested devices by testing, over a period
of time, and by causing the bad devices to actually fail
1. Test complexity
• Subjects the chips to a combination of production tests, high
2. Feature scaling and power dissipation temperature, and over-voltage power supply
3. Current (IDDQ) testing 3. Incoming Inspection
• To avoid placing a defective device in a system assembly
• Integration of Analog & Digital Devices onto One Chip

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1. Characterization 2. Manufacturing Test/Production

• Worst-case test: • Must enforce the quality requirements

• Determines whether the manufactured chip meets the
– Choose a test that passes/fails chips
specification
– Select a statistically significant sample of chips
• The vectors may not cover all possible functions and data
– Repeat test for every combination of environmental
patterns but must cover a high percentage of modeled
variables
faults
– Plot results in Shmoo plot
• Must minimize test time (to control cost)
– Diagnose and correct design errors
• No fault diagnosis
• Continue throughout the production life of chips to
• Production tests are typically short but test every device
improve design and process to increase yield
on the chip
a shmoo plot is a graphical display of the response of a component or system • Test at the rated speed or at the maximum speed
varying over a range of conditions or inputs.
guaranteed by the supplier
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3. Burn-in or Stress Test 4. Incoming Inspection

• All devices that pass production tests are not identical. When put to • System manufacturers perform incoming inspection on
actual use, some will fail very quickly while others will function for a the purchased devices before integrating them into the
long time. Burn-in ensures reliability of tested devices by testing,
either continuously or periodically, over a long period of time, and by system.
causing the bad devices to actually fail • Depending upon the context this testing either
• Process: Subject chips to high temperature and over-voltage – Similar to production testing
supply, while running production tests – More comprehensive than production testing
• Briefly, two types of failures are isolated by burn-in:
– Tuned to specific system application
– Infant mortality cases – these are damaged or weak (low
reliability) chips that will fail in the first few days of operation • Often done for a random sample of devices:
– burn-in causes bad devices to fail before they are shipped – Sample size depends on device quality and system
to customers. Short burn in time(10-30hrs) reliability requirements
– Freak failures – devices having the same failure – Avoids placing defective devices in a system where the cost
mechanisms as reliable devices. Long burn in time(100- of diagnosis and repair exceeds the incoming inspection
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cost BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Types of Tests Test Specifications and Test Plan

Parametric Tests • Test Specifications: The device specification document

• measures electrical properties of pin electronics initiates the development activity, and contains
• DC Parametric test: shorts, opens, leakage, output – Functional characteristics
drive current test… – Type of Device
– Technology-CMOS, GA, standard cell…
• AC parametric test: delay, functional speed, access tet,
– Physical constraints – package, pin numbers, etc.
rise and fall time test.
– Environmental characteristics–temperature, power supply
• fast and cheap – Reliability–acceptance quality level, failure rate, etc.
• Functional Tests • Test specifications, if not given explicitly, are derived from the above
data. Based on these specifications, a test plan is generated. In this
• consists of input vectors and corresponding responses
– Type of test equipment to use
• check for proper operation of a verified design by
– Types of tests
testing the internal chip nodes
– Fault coverage requirement
• cover a very high percentage of modeled faults
• long and expensive BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Testers Test Programming

The basic purpose of a tester is to drive the inputs and to monitor • Once the device-under-test has been mounted in
the outputs of a device-under-test. the tester, three things are needed to conduct the
Testers are popularly known as ATE (automatic test equipment.) test.
Fast-changing VLSI technology has driven the development of • These are the test program, the digital test
modern ATE.
vectors, and the analog test waveforms.
Selection of ATE for a VLSI device must consider the
specifications of the device.
• Until recently, test programs were written
Major factors are speed (clock rate of the device), timing (strobe)
manually.
accuracy, number of input/output pins, etc. • However, the use of CAD tools is now becoming
Other considerations in selecting a tester are cost, reliability, widespread in this area
serviceability, ease of programming, etc.

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Test Programming Generation

• Test program contains the sequence of instructions that

a tester would follow to conduct testing.
• An automatic test program generation (TPG) system
requires three types of inputs:
i. Tester specification and the information on the types
of tests are obtained from the test plan.
ii. Physical data on the device (pin locations, wafer
map, etc.) are obtained from the layout.
iii. Timing information on signals and test vectors
(inputs and expected responses) are obtained from
simulators.

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Test Data Analysis Introduction

• Test data obtained from the ATE serves three purposes: • Introduction to VLSI Testing
– First, it helps to accept or reject the device under test. • Design for Testability
– Second, it provides useful information about the fabrication • VLSI Technology Trends
process. • Types of Testing
– Third, it provides information about design weaknesses.
• Devices that did not fail are good only if tests covered
100% of faults.
• Failure Patterns
• Failing tests quickly point to faulty devices. • Automated Test Equipment
• Test data analysis allows the sorting of chips for higher • Testing Economics
than the nominal performance.

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Failure Pattern Types of Failures

• A failure pattern describes how a fault becomes a failure Failures can be:
indicating how the fault propagates through the system
• Manufacturing failures
units until it produces a failure.
– Defect or outside parametric specifications
• The pattern explicitly shows how flaws in the system
• Functional failures
allow the propagation of faults.
– Chip fails under all conditions
• The information in failure patterns is useful to evaluate
• Electrical failures
and design reliable systems.
– Malfunctions under certain conditions
– Shmoo plots can help to debug electrical failures in silicon

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How to diagnose failures? Introduction

• Hard to access chips • Introduction to VLSI Testing

• Pico probes • Design for Testability
• Electron beam • VLSI Technology Trends
• Laser voltage probing • Types of Testing
• Picosecond imaging circuit analysis • Failure Patterns
•
•
Infrared imaging
Focused ion beam
• Automated Test Equipment
• Testing Economics

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Automatic Test Equipment (ATE) Automatic Test Equipment

• The ATE is an instrument used to apply test patterns to a • ATE Consists of:
DUT/CUT, analyze the responses from the DUT, and mark
– Powerful computer
the DUT as good or bad.
– Powerful 32-bit Digital Signal Processor (DSP) for
• The ATE is controlled by a central UNIX work station or
PC, and additional CPUs is often built into it to provide analog testing
data reduction capability. – Test Program (written in a high-level language)
• The tester has one or more test heads. running on the computer
• The ATE is connected to external equipment that – Probe Head (actually touches the bare or packaged
handles the wafers or IC packages being tested. chip to perform fault detection experiments)
– While one chip or wafer is being tested in one test head – Probe Card (contains electronics to measure
(chip handler), another chip/wafer can be loaded into a signals on chip pin or pad)
second test head, so the tester overlaps mechanical
handling of parts with electrical testing of parts.

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ADVANTEST Model T6682ATE T6682 ATE Specifications

• Uses 0.35μ VLSI chips in implementation

• 1,024 digital pin channels
• Speed: 250, 500, or 1000 MHz
• Timing accuracy: +/- 200 ps
• Drive voltage: - 2.5 to 6 V
• Clock/strobe accuracy: +/- 870 ps
• Clock settling resolution: 31.25 ps
• Pattern multiplexing: write 2 patterns in one ATE cycle
• Pin multiplexing: use 2 pins to control 1 DUT pin

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Block Diagram ofT6682 VLSI Test System

When testing wafers, a probe card mechanically interfaces the

ATE’s test head to a set of probe needles (or probe membrane),
which actually contact the test pads on the wafer. The
Advantest T6682 can support up to 1024 pins.
The standard sequential pattern generator (SQPG) stores patterns
applied to the DUT.
The optional algorithmic pattern generator (ALPG) handles 32
independent address bits and 36 independent data bits. It can
be assigned to any tester channel, and is useful for embedded
memory testing, since it generates address and data lines in
real time, up to 250 MHz speeds.

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T6682 ATE Software

The address failure memory (AFM) module records • Runs Solaris UNIX on UltraSPARC 167 MHz CPU for
addresses in the memory-under-test that failed. The non-real-time functions.
optional scan pattern generator (SCPG) supports JTAG • Runs real-time OS on UltraSPARC 200 MHz CPU for
boundary scan. tester control.
The high-speed reload server provides for rapid internal • Peripherals: disk, CD-ROM, micro-floppy, monitor,
pattern transfer from a Host machine. keyboard, HP GPIB, Ethernet.
• Viewpoint software provided to debug, evaluate, and
analyze VLSI chips.

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Test Description Language (TDL) Multi-site Testing

• A test programming language, used to describe a • One ATE tests several devices at the same time
program that operates the ATE using the test vectors. • This is frequently done both in probe and package test
• Provides this information for controlling the ATE: • DUT interface board has > 1 sockets
– strobe times (for sampling the DUT outputs), voltage/current
stimulus information, the clocking rate for vectors, the vector
• Add more instruments to ATE to handle multiple
slew rate (rate at which waveforms rise or fall), and filtering devices simultaneously
information for sampling DUT signals. • Usually test 2 or 4 DUTs at a time, usually test 32 or
• In TDL one can set the resolution of the pin signal, which 64 memory chips at a time
is useful for determining causes of failures in DUTs. • Major cost reduction
• Test vectors must be edited, to adjust them to avoid • Limits: One limitation is the number of instruments
burning out the chip by exceeding the maximum allowable installed in the ATE to handle all of the required pins.
power dissipation.

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Introduction Test Economics

• Introduction to VLSI Testing Testing is responsible for the quality of VLSI devices. Several
• Design for Testability tradeoffs are often necessary to obtain the required quality
level at minimal cost.
• VLSI Technology Trends
• Types of Testing Costs include the cost of automatic test equipment (ATE) (initial
• Failure Patterns and running costs), the cost of test development (CAD tools,
• Automated Test Equipment test vector generation, test programming), and the cost of DFT.

• Testing Economics In the future, DFT will dominate test economics equations. The
scan design technique can significantly reduce the cost of test
generation and the BIST method can lower the complexity and
cost of ATE.

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Defining Costs Test Economics

Fixed Costs (FC.): These are the costs of things that are necessary but
do not change with use. For example, if we wish to produce
computers, we require a factory building and machinery which
contribute to fixed costs. These costs do not change with the number
of computers that are built, whether we build one or one thousand
computers.
Variable Costs (VC.) These costs increase with the production output.
variable costs generally consist
of labor, energy, and raw materials.
Total Costs (TC.) Total costs are the sum of the fixed and variable
costs, and increase with production output.
Average Costs (AC.) These are obtained by dividing the total costs by When the aging factor is taken into account, the average cost
the number of units produced. might be as shown by the rising curve (shown as real), called a
bathtub curve. Thus, durability of equipment may be more
important than the initial purchase price for realizing lower
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Costs of Testing The Rule of Ten

• Design for testability (DFT) • Chips must be tested before they are assembled onto
– Chip area overhead and yield reduction printed circuit boards (PCBs), which, in turn, must be
– Performance overhead tested before they are assembled into systems.
• Software processes of test • Experience has shown that the rule of ten holds.
– Test generation and fault simulation • If a chip fault is not caught by chip testing, then finding
– Test programming and debugging the fault costs *10 times as much at the PCB level as at
the chip level.
• Manufacturing test
• Similarly, if a board fault is not caught by PCB testing,
– Automatic test equipment (ATE) capital cost
then finding the fault costs *10 times as much at the
– Test center operational cost system level as at the board level.

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VLSI Chip Yield

• A manufacturing defect is a finite chip area with 1)Diagnosis and Repair. The parts that are found defective after test
electrically malfunctioning circuitry caused by errors in are diagnosed for specific failures which are then repaired. Although
the fabrication process. the yield is improved, this procedure increases the cost of
• A chip with no manufacturing defect is called a good chip. manufacturing. The reason is that we first allow the process to make
• The fraction (or percentage) of good chips produced in a errors which are then corrected.
manufacturing process is called the yield. A more economical procedure is to eliminate the sources of errors.
• The term wafer yield is sometimes used to refer to the
average number of good chips produced per wafer. (2) Process Diagnosis and Correction. The defects found in the failed
• Testing cannot improve the process yield. parts are traced to specific causes, which may be defective material,
• There are two ways of improving the process yield: faulty machines, incorrect human procedures, etc. Once the cause is
eliminated, the yield improves. Process diagnosis is the preferred
i. Diagnosis and repair
method of yield improvement.
ii. Process diagnosis and correction

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Clustered VLSI Defects Yield Equation

Y = Prob ( zero defect on a chip ) = p (0)
Good chips
Y = ( 1 + Ad / α) – α
Faulty chips
A: Area of a chip
d: Defect density
α: clustering parameter

Example: Ad = 1.0, α= 0.5, then, Y = 0.58

Defects
Unclustered defects: α= ∞, Y = e - Ad
Wafer

Unclustered defects Clustered defects (VLSI) Example: Ad = 1.0, α= ∞, then, Y = 0.37

Wafer yield = 12/22 = 0.55 Wafer yield = 17/22 = 0.77
Defect Level or Reject Ratio Summary

• Defect level (DL) is the ratio of faulty chips among the chips • Overall benefit/cost ratio for design, test, and manufacturing
that pass tests, measured as parts per million (ppm). should be maximized; one should select the most economical
• A measure of the effectiveness of tests. design over the cheapest design.
• A quantitative measure of the manufactured product quality. • A DFT or test method should be selected to improve the
product quality with minimal increase in cost due to area
• The DL is determined from the field return data.
overhead and yield loss.
• The chips thus returned are examined by the manufacturer to
• VLSI yield depends on two process parameters, defect density
determine the causes of failures.
(d) and clustering parameter (α).
• These causes may point to areas of improvement in
• Yield drops as chip area increases; low yield means high cost.
specification, design, fabrication, or test.
• Fault coverage measures the test quality.
• Such improvements reduce the defect level.
• Defect level (DL) or reject ratio is a measure of chip quality.
• For VLSI chips, while a defect level of 500 ppm may be
acceptable, 100 ppm or lower represents high quality. • DL can be determined by an analysis of test data.

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FaultModelingandLogicSimulation Defects, Faults, and Errors

• Definitions and Fault models Defect. A defect in an electronic system is the unintended
• Stuck at faults difference between the implemented hardware and its intended
• Propagation and Detectability of faults design.
Example: Unwanted wire(short to ground)
• Fault Equivalence, Collapsing, Dominance
Some typical defects in VLSI chips are
• Check Point Theorem 1.Process Defects – missing contact windows, parasitic
• Logic Simulation transistors, oxide break-down, etc.
2. Material Defects – bulk defects (cracks, crystal imperfections),
surface impurities, etc.
3. Age Defects – dielectric breakdown, electromigration, etc.
4. Package Defects – contact degradation, seal leaks, etc.

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3 of UGC Campus
1956

Defects, Faults, and Errors Defects, Faults, and Errors

Error: A wrong output signal produced by a defective • Defects occur either during manufacture or during the
system is called an error. An error is an “effect” whose use of devices.
cause is some “defect.” • Repeated occurrence of the same defect indicates the
Fault: A representation of a “defect” at the abstracted need for improvements in the manufacturing process
function level is called a fault. or the design of the device.
• Procedures for diagnosing defects and finding their
Error: a=1, b=1 , output c=0, correct output c=1 . Notice causes are known as FMA.
that the error is not permanent. As long as at least one
input is 0, there is no error in the output.

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Untestable Fault Functional Versus Structural Testing

• A fault for which no test can be found is called an • Functional tests is often found necessary for verification
untestable fault. of design.
• There are two classes of untestable faults: • The purpose of hardware/manufacturing test is to
i. Faults that are redundant, i.e., whose presence does not discover any faults caused due to manufacturing defects
change the input-output behavior of the circuit. or errors.
ii. Faults that change the input-output behavior of the circuit – Assumption is that the design being manufactured is correct.
but no test can be found by a given method of testing or • Structural Test depend on the specific structure (gate
test generation. types, interconnects, netlist) of the circuit.
• Advantages of structural testing is that it allows us to
develop algorithms.
• Central to these algorithms are fault models.

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Functional Versus Structural

Testing Why Model Faults?
Input/Output (I/O) function tests are inadequate for
manufacturing
• Real defects (often mechanical) too numerous and often not
analyzable
• A fault model identifies targets for testing
• A fault model makes analysis possible
• Effectiveness measurable by experiments
• Most test generation and test evaluation (fault simulation)
algorithms are based on selected fault models.

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Levels of Fault Models Fault Models

• Modelling of faults is related to the modelling of the • Different fault models are:
circuit.
▪ Stuck-at faults
• In design hierarchy, level refers to the degree of
• Single stuck-at faults
abstraction: • Multiple stuck-at faults
▪ Behavioral (high) level
▪ Stuck-open faults
▪ Register-transfer (logic) level
▪ Bridging faults
▪ bridging faults and delay faults
▪ Component (lower) levels
▪ Delay faults
▪ stuck open types of faults also known as technology- ▪ Assertion Fault
dependent faults ▪ Behavioral Faults
▪ Quiescent current (realistic) ▪ Branch Fault:

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Structural Faults Single Stuck-at Fault
• We assume that the circuit is modeled as an
• Structural faults are related to structural models. interconnection (called a netlist) of Boolean gates.
• Structural fault models assume that components are fault- • A stuck-at fault is assumed to affect only the
free and only their interconnections are affected. interconnection between gates.
• Each connecting line can have two types of faults:
• Typical faults affecting interconnections are short and
– stuck-at-1 and stuck-at-0
opens.
• A line has a fault stuck-at-1 (s-a-1) or stuck-at-0 (s-a-0).
• A short is formed by connecting points not intended to be
connected. • A circuit with n lines can have 3n – 1 possible stuck line
combinations.
• An open results from the breaking of a connection. – This is because each line can be in one of the three states:
s-a-1, s-a-0, or fault-free.
• An n-line circuit can have at most 2n single stuck-at
faults.
– This number is further reduced by a technique known as
fault collapsing.
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Single Stuck-at Fault An Example of a single stuck-at fault

• Examples:
– A short between ground (s-a-0) or power (s-a-1) and a
signal line.
– An open on a unidirectional signal line.
– Any internal fault in the component driving its output
that it keeps a constant value.

• Three properties (assumptions) define a single stuck-at

fault: Consider the circuit of Figure . A stuck-at-1 fault as marked at the
• Only one line is faulty output of the OR gate means that the faulty signal remains 1
• The faulty line is permanently set to 0 or 1 irrespective of the input state of the OR gate.
• The fault can be at an input or output of a gate If the normal output of the OR gate is 1, as it would be if the
inputs were 01, 10, or 11, then this fault will not affect any signal
in the circuit.
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An Example of a single stuck-at fault

However, a 00 input to the OR gate will produce a 0 output in the This example illustrates the basic features of a
normal circuit. The faulty circuit will have a 1 there. single stuck-at fault.
Figure shows the normal (faulty) value as 0(1), which is applied to
Notice that gates are assumed to function
the AND2 gate at the output.
correctly. Only the signal interconnects are
This signal state must be propagated to the output of the AND2
gate, which is an observable output of this circuit. considered to be faulty.
This is done by setting the other input of AND2 as 1, which is The circuit of Figure has seven lines, which are
justified by setting the inputs of AND1 as 11. Now we have the the potential sites for single stuck-at faults.
input vector 1100 as a test for the s-a-1 fault since for this vector The number of possible faults is 14.
the normal output (true response) and the faulty output differ.

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Example Single Stuck-at Fault
• Consider the exclusive-OR function implemented by the
circuit of Figure below As shown, the single fault h s-a-0 is
detectable by a 10 input.
• Signal lines g, h, and i, commonly known as a signal net,
carry the same signal value.
Faulty circuit value
Good circuit value
c j
s-a-0 0(1)
a d g h 1(0)
1
z
0 1 i
b e 1
f k
Test vector for h s-a-0 fault
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Single Stuck-at Fault

The 10 input also activates single s-a-0 faults on g and i. But, To consider all possible faults, we model single stuck-at faults on
only g s-a-0 is detectable by this input. the stem and all fanout branches of the net. Considering all
The effect of fault i s-a-0 is blocked from propagating to the nets in the circuit, this is equivalent to modeling faults on
primary output z by f=0 which uniquely sets k=1. inputs and outputs of all gates .
We notice that the faults on the fanout branches of a net are not The circuit has 12 fault sites and hence we would model 24 single
identical. stuck-at faults.
In a logic circuit, a net contains a stem or source (g in this circuit) To reduce this number, we will use the concepts of fault
and fanout branches (h and i.) The stem is the output of some equivalence and fault dominance,
gate and fanout branches are inputs of some other gates.

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Multiple Stuck-at Faults Why MSF is not preferred

• A multiple stuck-at fault means that any set of lines is

stuck-at some combination of (0,1) values.
• The total number of single and multiple stuck-at faults
in a circuit with n single fault sites is 3n-1.
• A single fault test can fail to detect the target fault if
another fault is also present, however, such masking of
one fault by another is rare.
• Statistically, single fault tests cover a very large number
of multiple faults.
• MSF is not considered in practice

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Transistor (Switch) Faults Stuck-Open Example
Vector 1: test for A s-a-0
• MOS transistor is considered an ideal switch and two
(Initialization vector)
types of faults are modeled:
Vector 2: (test for A s-a-1)
▪ Stuck-open - a single transistor is permanently stuck in pMOS VDD
the open state. Two-vector s-open test
FETs
▪ Stuck-short - a single transistor is permanently shorted can be constructed by
A ordering two s-at tests
irrespective of its gate voltage. 1 0 Stuck-
• Detection of a stuck-open fault requires two test vectors. open
• Detection of a stuck-short fault requires the B
measurement of quiescent current (IDDQ). 0 0 C
0 1(Z)

Good circuit states

nMOS
FETs Faulty circuit states

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Logic gate model of NOR gate

Consider the fault P1 stuck-open. If we apply A=B=0 then P1 and

P2 are shorted in the fault-free circuit but only P2 is shorted in
the faulty circuit.
N1 and N2 are open in both circuits. Thus, the output C is 1 in
good circuit but is “floating” (not connected either to VDD or
to ground) in the faulty circuit.
We denote this state as Z and 1/Z denotes the good/faulty states in
Figure shows a NOR gate implemented in CMOS technology. P1 Figure .
and P2 are transistors that will be shorted when their gate-inputs, A
The complete test consists of two vectors,10→00 which
and B, are 0. The same values on the gate-inputs of nmos
transistors, N1 and N2, make them open. Thus A=B=0 will produce an output 0->1 in the good circuit and 0->0 in the faulty
connect the output C to VDD while isolating it from ground. circuit.
EitherA=1 or will connect C to ground while isolating it from
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Fault Modeling and Logic Simulation

Stuck-Short Example
Test vector for A s-a-0 • Definitions and Fault models
• Stuck at faults
pMOS
FETs
VDD
IDDQ path in • Propagation and Detectability of faults
1
A
Stuck-
faulty circuit
• Fault Equivalence, Collapsing,
short Dominance
B Good circuit state • Check Point Theorem
0 C
0 (X) • Logic Simulation

nMOS
FETs Faulty circuit state

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Fault Equivalence Fault Equivalence

• Number of fault sites in a Boolean gate circuit is • Consideroutputfunctionasf0(V).The outputfunctioninthepresenceof

= #PI + #gates + # (fanout branches) fault1 bef1(V)andthatinthepresenceoffault2 be f2(V)
• Two faults of a Boolean circuit are called equivalent iff
they transform the circuit such that the two faulty circuits
have identical output functions.
• Fault equivalence: Two faults f1 and f2 are equivalent if
all tests that detect f1 also detect f2.
• If faults f1 and f2 are equivalent then the corresponding
faulty functions are identical.
• Equivalent faults are also called indistinguishable and
have exactly the same set of tests.

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Fault Equivalence Equivalence Rules

sa0 sa0
Consider a k input AND gate. It has k + 1 s-a-0 faults on its input and
output lines. Each s-a-0 fault transforms the AND gate to a constant sa1 sa1
0 output function. Thus all s-a-0 faults are equivalent. No such sa0 sa1 sa0 sa1 WIRE
equivalence relation is found among the k + 1 s-a-1 faults. sa0 sa1 sa0 sa1
AND OR
Similar analysis of other Boolean gates leads to the equivalences shown
in Figure in next slide. which also includes connecting wire and fan- sa0 sa1 sa0 sa1
out that are necessary components for a circuit. sa0 sa1
A two-way arrow shows pair-wise equivalence. Note that the NOT gate NOT sa0
sa1
is identical to a single-input NAND or NOR gate.
Similarly, the wire (or a non-inverting buffer) is identical to a single- sa0 sa1 sa0 sa1
input AND or OR gate. sa0 sa1 sa0 sa1 sa0
NAND NOR
The case of the fanout no fault equivalences are possible seems sa1
sa0
to violate the conclusions of the last subsection. sa0 sa1 sa0 sa1
sa1
sa0
FANOUT sa1

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Fault Collapsing Fault Equivalence

• The set of all faults in a circuit can be partitioned into Fault collapsing is performed in a level-by-level pass from inputs
equivalence sets, such that faults in an equivalent set are to output using local gate fault equivalences discussed earlier.
equivalent to each other. The procedure begins at primary inputs and a gate is not
• All single faults of a logic circuit can be divided into processed until all gates feeding its inputs have been
disjoint equivalence subsets, where all faults in a processed.
subset are mutually equivalent.
At a gate, first input faults are examined. Only one among the
• A collapsed fault set contains one fault from each equivalent faults is retained.
equivalence subset.
Then any input faults that are equivalent to some output fault are
• The process of selecting one fault from each deleted.
equivalence set is called fault collapsing.
Note that the collapse ratio is around 50 or 60% and that more
• The set of selected faults is known as the equivalence reduction occurs in the absence of fanouts.
collapsed set.

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Equivalence Fault Collapsing Example Examples of Equivalence Fault Collapsing
Faults in boldface
sa0 sa1 removed by
sa0 sa1 equivalence
sa0 sa1 collapsing
sa0 sa1 sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1
sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
20
Collapse ratio = ──= 0.625
32
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Fault Dominance Fault Dominance

• If all tests of some fault F1 detect another fault F2, then • Consider a three-input AND gate with two single s-a-1
F2 is said to dominate F1. faults shown as F1 and F2.
• Dominance fault collapsing: If fault F2 dominates F1, • Suppose that T(F1) is the set of all tests for F1 and T(F2)
then F2 is removed from the fault list. is the set of all tests for F2.
• When dominance fault collapsing is used, it is sufficient • T(F1) contains one vector and T(F2) has seven vectors.
to consider only the input faults of Boolean gates. • The fault F2 dominates fault F1.
• In a tree circuit (without fanouts) PI faults form a F1
dominance collapsed fault set. s-a-1
• If two faults dominate each other then they are F2
s-a-1
equivalent.

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Dominance Example Dominance Fault Collapsing

All tests of F2
1. An n-input Boolean gate requires n + 1 single stuck-at
F1 faults to be modeled.
s-a-1 001
F2 2. To collapse faults of a gate, all faults from the output can
s-a-1 110 010 be eliminated retaining one type (s-a-1 for AND and
000 011 NAND; s-a-0 for OR and NOR) of fault on each input
101 and the other type (s-a-0 for AND and NAND; s-a-1 for
100 OR and NOR) on any one of the inputs.
s-a-1 Only test of F1 3. The output faults of the NOT gate, the non-inverting
A dominance s-a-1 buffer, and the wire can be removed as long as both
collapsed fault s-a-1 faults on the input are retained. No collapsing is possible
set for fanout.
s-a-0
Fault F2 dominates fault F1
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Dominance Fault Collapsing Example Examples of dominance fault co lapsing

sa0 sa1 Faults in blue

sa0 sa1
removed by
sa0 sa1
equivalence
sa0 sa1 sa0 sa1 collapsing
sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1
sa0 sa1

sa0 sa1 sa0 sa1 Faults in red

sa0 sa1 removed by
sa0 sa1 dominance
sa0 sa1
collapsing
sa0 sa1
15
Collapse ratio = ──= 0.47
32
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Dominance Collapsing Example Example:

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FaultModelingandLogicSimulation Checkpoint Theorem

• Definitions and Fault models • Primary inputs and fanout branches of a combinational
• Stuck at faults circuit are called checkpoints.
• Propagation and Detectability of faults • Checkpoint Theorem: A test set that detects all single
• Fault Equivalence, Collapsing, Dominance (multiple) stuck-at faults on all checkpoints of a
combinational circuit, also detects all single (multiple)
• Check Point Theorem stuck-at faults in that circuit.

• Logic Simulation
• Total fault sites = 16

• Checkpoints ( ) = 10

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Summary Definitions
• Fault models are analyzable approximations of defects
and are essential for a test methodology.
• For digital logic single stuck-at fault model offers best
advantage of tools and experience.
• Many other faults (bridging, stuck-open and multiple
stuck-at) are largely covered by stuck-at fault tests.
• Stuck-short and delay faults and technology-dependent
faults require special tests.
• Memory and analog circuits need other specialized fault
models and tests.
• Fault simulator is an essential tool for test development.

Simulation Simulation for Design Verification

• Definition: Simulation refers to modeling of a design, • Simulation serves two distinct purposes in electronic
its function and performance. design:
• A software simulator is a computer program.
– First, it is used to verify the correctness of the design.
• An emulator is a hardware simulator.
– Second, it verifies the tests.
• Simulation is used for design verification:
• Validate assumptions • The process of realizing an electronic system begins
• Verify logic with its specification, which describes the input/output
• Verify performance (timing) electrical behavior.
• Types of simulation: • The process of synthesis produces an interconnect of
• Logic or switch level components (called a netlist).
• Timing
• Circuit • The design is verified by a true-value simulator.
• Fault

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Simulation for Design Verification

• True-value means that the simulator will compute the

Specification response for given input stimuli without injecting any
faults in the design.
Synthesis
• The input stimuli are also based on the specification.
Response Design Design • The stimuli correspond to those input and output
analysis changes (netlist) specifications that are either critical or considered risky
by the synthesis procedures.
• A frequently used strategy is to exercise all functions
with only critical data patterns.
Computed True-value
responses simulator
Input stimuli • True-value simulator, computes the responses that a
circuit (if built using the netlist) would have produced if
the given input stimuli were applied.

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Simulation for Test Evaluation Simulation for Test Evaluation

• Fault simulator is used for the development of

manufacturing tests. Verified design Verification
netlist input stimuli
• A fault simulator incorporates many of the details of a
true-value simulator.
Fault simulator Test vectors
• A fault simulator has the capability to simulate the
circuit response in the presence of faults. Modeled Remove Test Delete
fault list tested faults compactor vectors
• Fault simulation is done after the design has been
verified and the verified circuit netlist and verification
vectors are available. Fault Low Test
coverage
• These two inputs to the fault simulator are shown as the ?
generator Add vectors
shaded boxes i Adequate
Stop
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Algorithms for Fault Simulation

The fault simulator performs two functions: A fault simulator must classify the given target faults in a
1. It determines the coverage of a given set of input stimuli circuit as detected or undetected by the given stimuli.
(vectors) for a given fault model or a given fault list.
2. With the help of other programs (a test generator or a
vector compacter ), it can produce a set of vectors with
a given fault coverage for manufacturing test.
If no fault list is supplied, the fault simulator generates one
for the specified fault model.

The block C( ) is the fault-free circuit and blocks C(f1) through C(fn) are copies
of the same circuit with faults f1 through fn permanently inserted. The same
vectors are applied to all blocks and the outputs of the faulty circuits are
compared in the comparators shown as Comp.

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All signal lines in Figure are buses that provide parallel While the multiple detection of a fault, as shown in Figure is desirable
access to all primary inputs and outputs. for fault diagnosis ,it is expensive in computation time.
If any comparator shows a mismatch, the corresponding Therefore, when fault fn is detected for the first time by vector 35, the
fault is noted as detected by the vector being simulated. simulation of block C(fn) is suspended beyond that vector.
This procedure, known as fault dropping, considerably speeds up the
Thus, the simulator records the numbers of vectors that
fault simulation process.
detect a fault.
We notice that, except for fault dropping, the effort of simulating
For example, in Figure fault f1 is detected by vectors 5, 12, n faults is equivalent to either simulating a circuit that is n
and 19. Fault fn is detected by vectors 35 and 102, and times larger, or repeating the original true-value simulation n
f2 is not detected by any vector. In addition, the simulator times.
may also record the specific output at which a fault is The algorithms in the following subsections attempt to reduce
detected. this effort.

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Serial Fault Simulation

This is the simplest algorithm for simulating faults. A serial fault simulator repeatedly uses a true-value simulator. Its
The circuit is first simulated in the true-value mode for all vectors implementation is, therefore, simple.
and primary output values are saved in a file. Next, faulty It can simulate any fault that can be introduced in the circuit
circuits are simulated one by one. description. Thus, apart from the stuck-at and stuck-open
This is done by modifying the circuit description for a target fault types, bridging, delay, and analog faults can also be simulated.
and then using the true-value simulator. For this reason, analog circuit faults are usually simulated by this
As the simulation proceeds, the output values of the faulty circuit method.
are dynamically compared with the saved true responses. Also, a serial fault simulator can easily simulate all types of fault
The simulation of a faulty circuit is stopped as soon as the conditions, such as fault-induced races, hazards, loss of
comparison indicates detection of the target fault. initialization, etc., in sequential circuits, which present
All faults are simulated serially in this way difficulties to other types of simulators.

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Example of serial fault simulation

The fault-free responses are Kgood =1, 1, 0 for input patterns P1,
P2, and P3, respectively.
After the fault-free responses are available, fault f is processed;
fault injection is achieved by forcing A to a constant one and
the obtained faulty circuit is simulated. The circuit responses
for fault f are Kf = 0, 0, 0 with respect to the three input
In this example, the fault list is comprised of two faults, A patterns.
stuck-at one (denoted by f) and J stuck-at zero (denoted by g). It is observed that patterns P1 and P2 detect fault f but pattern P3
Note that, although both faults are drawn in the figure, only does not. After fault f has been simulated, circuit is restored
one fault is present at a time under the single stuck-at fault by removing fault f. The next fault, g, is then injected by
model. forcing J to zero.
The test set consists of three test patterns (denoted by P1, P2,
and P3 shown in the table
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Simulation of the resulting faulty circuit is then performed to The simplified serial fault simulation flow is depicted in Figure
obtain the faulty outputs Kg =1,1,1 Fault g is detected by below.
pattern P3 but not P1 and P2. Prior to fault simulation, fault collapsing is executed to reduce
the size of the fault list, denoted by F
one can observe that, if we are only concerned with the set of
faults that is detected by the test set {P1, P2, P3}, simulations Fault-free simulation is then performed for all test patterns to
of the faulty circuit with fault f for patterns P2 and P3 are obtain the correct responses Ogood.
redundant because f is already detected by P1. The algorithm then proceeds to fault simulation.
Halting simulation of detected faults is called fault dropping. For each fault f in F, if there exists a test pattern whose output
response of differs from that of the corresponding good circuit
For the purpose of fault grading, fault dropping dramatically Ogood, f is removed from F, indicating that it is detected.
improves fault simulation performance, as most faults are When all patterns have been simulated, the remaining faults in F
detected after relatively few test patterns have been applied are the undetected faults.

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 Advantages and disadvantages

The major advantage of serial fault simulation is its ease of

implementation; a regular logic simulator plus fault injection
and output comparison procedures will suffice. In addition,
serial fault simulation can handle a wide range of fault models,
as long as the fault effects can be properly injected into the
circuit.
The major disadvantage of serial fault simulation is its low
performance.

practical fault simulation techniques exploit parallelism or

similarities among the faulty circuits to speed up the fault
simulation process.

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Parallel Fault Simulation Parallel Fault Simulation

Let us assume that the circuit consists of only logic gates and we wish If no fault-dropping is used, a parallel fault simulator will run
to simulate stuck-at faults. about w – 1 times faster than a serial fault simulator.
Also, signals are assumed to take only binary, i.e., 0 and 1, values. Both simulators will gain speed by fault dropping.
Also, all gates are assumed to have the same delay. In serial fault simulator, the pass is terminated as soon as the
It is under these conditions that parallel fault simulation is most single target fault is detected.
effective.
In parallel fault simulator, all w – 1 faults must be detected before
For a large number of faults, a parallel fault simulator will process
a pass can be terminated. Therefore, the serial fault simulator
w – 1 faults in one pass, where w bits is the machine word size.
gains more by fault dropping.
This is because one bit of the word is used for the signal value of the
fault-free circuit. Advantages: A large number of faults can be detected by each pattern
Disadvantage: Faults cannot be dropped unless all faults are detected.
Thus, w – 1 faults are simulated in the same CPU time as that taken by
the true-value simulation.

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Example-1

Since the line a and the stem b are not affected by any fault, these
have the same values for all three circuits.
The fault on c is present only in the first faulty circuit and so it
affects the middle bit. When the words on a and c are AND ed,
we get the three-bit word for line e.
Line f is the inversion of d, hence its values, where the right bit
(bit 2) is affected by the s-a-1 fault, are given by the word 001.
The output g is obtained by a bit-by-bit OR of e=101 and f=101
Figure shows a circuit that is being simulated for two faults: c stuck-at-0 and f We notice that only the output of the circuit with c s-a-0
stuck-at-1. The computer has a three-bit word. To simulate the fault-free and (middle bit) differs from that of the fault-free circuit (left bit.)
two faulty circuits in parallel, the signal on each line is expressed as one word. Hence, that fault is detected. The other fault, which produces
The state of the left-most bit (bit 0) represents the signal value in the fault-free the same output as the fault-free circuit, is not detected
circuit, the middle bit (bit 1) that in the circuit with c s-a-0, and the right-most
bit (bit 2) that in the circuit with f s-a-1. We apply a vector S

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Example-2 :Parallel Fault Example-2 Contd.,

Assuming that the width of a computer word is three bits, the first
bit stores the fault-free (FF) circuit response, and the second
and third bits store the faulty responses in the presence of
faults f and g, respectively.
The simulation results are shown in Table Because fault f, A
stuck-at one, uses the second bit, it is injected by forcing the
second bit of the data word of signal A to 1 during fault
simulation (shown in the “Af” column with the forced value
underlined; the “A” column corresponds to the fault-free case).
Similarly, the “Jg” column depicts how fault g is injected by
forcing the third bit to 0.

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Example-2 Contd., Deductive Fault Simulation

parallel fault simulation is performed using bitwise logic operations. In the deductive method only the fault-free circuit (C( ) is
For example, the logic value of signal H is obtained by a bitwise AND simulated. All signal values in each faulty circuit are
operation on the data words of signals A and L (A, L, and H are deduced from the fault-free circuit values and the circuit
circled in Table ).
structure. Since the circuit structure is the same for all
The faulty response of the first pattern is {1, 0, 1}.
faulty circuits, all deductions are carried out
This means that fault f is detected (the second bit) but fault g (the third
bit) is not. simultaneously.
Similarly, the outputs of P2 and P3 are {1, 0, 1} and {0, 0, 1},
respectively.
In this example, three simulations (in one simulation pass) are
performed. Compared to serial fault simulation, which requires nine
simulations, parallel fault simulation saves two-thirds of the
simulation time.

Fault lists in a deductive fault simulator.

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Deductive Fault Simulation Deductive Fault Simulation

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 Fault list propagation in deductive fault
simulator
Here ak fault means signal a stuck-at-k, with k=0 or 1.
For the AND gate with primary inputs a=0 and b=1 the output is
c=0.
Since a and b are primary inputs, their fault lists simply contain
their own faults activated by the present signal values.
We will denote their fault lists as sets, La=[a1] and Lb=[b0] Since
b=1 the path from a to c is sensitized, but the path from b to c
is not sensitized.
Therefore, the fault list of c contains a1.
In addition, it also contains the fault c s-a-1 as the current state
of c is 0.
The fanouts d and e simply adopt the fault list from their source
stem c and add their own respective faults.

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Example of deductive fault simulation

The output fault list of a gate is generated by set operations
such as union (U) intersection (∩)and complementation
(-), among fault lists. For example, when both inputs of a
two-input AND gate are 0, to propagate through, the
effect of a fault must be present on both inputs. This is
achieved by the intersection,La∩Lb of the two input fault
lists. In addition, the fault is included.

Consider the vector (1,1) applied to the circuit of Figure . We will simulate the s-a-0
and s-a-1 faults on all lines a through g for this vector. First, true-value simulation is
carried out to determine all signal values, which are shown in the figure. This requires
a single pass from inputs to the output. Next, we conduct a second input to output
pass for fault list generation and propagation. The lists of primary inputs just contain
the respective s-a-0 faults that are active there.

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Fault lists for fanouts c and d are obtained by adding their Notice that the fault b0 is present at both inputs of the OR
locally active faults to the fault list Lb of the stem. The gate. That is, this fault will invert both inputs and the
fault list for e is obtained by the propagation rules. output of the faulty circuit will remain 1, the same as the
fault-free output. That is why b0 is absent from Lg. This
completes the fault propagation, which tells us that four
faults, a s-a-0, c s-a-0, e s-a-0, and g s-a-0, are
The fault list of d simply propagates through the NOT gate. Thus:
detected by the (1,1) input vector

Using the propagation rule for OR gate, we get:

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Example-2 for input pattern 010 Example-2 for input pattern 010 contd.,

On the other hand, because the fault-free value of C is a non controlling

value of G1, the fault effect of each fault in LB will propagate to E
(which causes E to be 1); therefore, all faults in LB are propagated
to LE. LC is not propagated to the gate output because the other
input B holds the controlling value (one) of gate G1. Similarly, the
fault list LE is propagated to signals L and F. The fanout branches
do nothing but add faults L/0andF/0toLL and LF,respectively. The
fault list of gate output H contains A/1 and H/1; the fault list of A is
propagated through G2 because L is one, and the fault list of L is
discarded because A is zero. Finally, the fault list of primary output
Figure shows the fault list of each signal with respect to test pattern P1. Fault A/1 K is the union of the fault lists of the two gate inputs; that is, LK
appears in LA because its presence causes the value of primary input A to deviate from =LH ∪LJ = A/1, H/1, B/0, E/0, F/0, J/1, K/0 because both gate inputs
its correct value of zero. Fault A/0 is not in the fault list because the value of A remains
of G4 are zeros; all the fault effects at the gate inputs are propagated
correct when the fault A/0 is present. The fault lists for inputs B and C are derived in
the same way. Based on logic reasoning, the process of deriving the fault list of a gate
to the gate output.
output from those of the gate inputs is called fault list propagation; for example, the
fault list of gate output E is the union of the fault list of B and the E/0 fault.
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Example-2 for input pattern 010 contd., Limitations of Deductive fault simulation

we can conclude that pattern P1 detects the seven faults in LK. Although deductive fault simulation is efficient in that it processes all faults at
the same time, it has several limitations. The first problem is that unknown
From this simple example, we can see the advantage of
values are not easily handled. For each unknown value, both cases must be
deductive fault simulation—all faults detected by a test pattern considered (ie, when the unknown is a controlling or non-controlling
are obtained in one fault list propagation pass. value). The logic reasoning becomes even more complicated if more than
one unknown appears.
The second problem is that deductive fault simulation is only suitable for the
zero-delay timing model, because no timing information is considered
during the deductive fault propagation process.
Finally, deductive fault simulation has a potential memory management
problem.
Because the size of fault lists can not be predicted in advance, there can be a
large variation in memory requirements during algorithm execution.

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Deductive fault simulation flowchart Concurrent Fault Simulation

Concurrent fault simulation is essentially an event-driven

simulation with the fault-free circuit and faulty circuits
simulated altogether.
In concurrent fault simulation, every gate has a concurrent fault
list, which consists of a set of bad gates.
A bad gate of gate x represents an imaginary copy of gate x in the
presence of a fault.
Every bad gate contains a fault index and the associated gate I/O
values in the presence of the corresponding fault.
Initially, the concurrent fault list of gate x contains local faults of
gate x.

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The local faults of gate x are faults on the inputs or outputs of
gate x. As the simulation proceeds, the concurrent fault list
contains not only local faults but also faults propagated from
previous stages. Local faults of gate x remain in the concurrent
fault list of gate x until they are detected.

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Example Bad Events

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Bad gates diverges from its good gate

The fault list of G1, G2, and G3 initially contains their local faults: C/0, A/1, and J/0. A bad event does not occur in the good circuit; it only
When we apply the first pattern, three events occur in the primary inputs: u → 0 on A, u occurs in the faulty circuit of the corresponding fault. A
→ 1on B, and u →0 on C. They are good events because they happen in the good circuit.
A bad gate is invisible if its faulty output is the same as the good output. The bad gates new copy of bad gate A/1 is added to the concurrent fault
C/0 and J/0 are both invisible so they are not propagated to the subsequent stages. A bad list of G4 because it has one input different from the
gate is visible if its faulty output is different from the good output. The visible bad gate good gate. It is said that bad gate A/1 diverges from its
A/1 creates a bad event u →1on net H (in gray).
good gate. Finally, fault A/1 is detected because the
faulty output K is different from the good output.

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 Pattern 010-001 Example pattern 3:001-100
Two good events occur in this figure: 0→1 on C and 1→0 on B.The badgateC/0,which
was invisible in pattern P1, now becomes newly visible. The newly visible bad gate
creates a bad event—net E falls to zero, which in turn creates two divergences in G2
and G3. Bad event—net J rises to one. Finally, the concurrent fault list of G4 contains
two bad gates; both faults A/1 and C/0 are detected.

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Example: Fault-lists (bad-gates) in

concurrent fault simulation for input 11
For the last test pattern P3 (Figure ), two good events occur at primary
inputs A and C. The bad gate C/0 now becomes invisible. The bad
gate C/0 is deleted from the concurrent fault list of G3.
A bad gate converges to its good gate if it is not a local fault and its I/O
values are identical to those of the good gate.
Similarly, the other bad gates of C/0 also converge to G2 and G4. Note
that bad gate C/0 does not converge to G1 because it is a local fault
for G1.
The bad gate A/1 can be examined in the same way. For gate G3,
although the faulty output of bad gate J/0 does not change, the good
event 0 → 1on J makes bad gate J/0 newly visible. The newly
visible event (in gray) is propagated to G4 and a new bad gate J/0
diverges from G4. Eventually, the fault J/0 is detected by pattern P3

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Event processing and convergence in Bad-gate divergence in concurrent fault

concurrent fault simulation simulation.

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Concurrent fault simulation flowchart. Concurrent Fault Simulation

Advantages
1. Efficient
2. Fault can be simulated in any modelling style or detail
supported in true value simulation
3. Faster than other method
Disadvantage
1.Potential memory problem
2. Size of the concurrent fault list changes at run time

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Comparison of fault simulation techniques Roth's TEST-DETECT Algorithm

Speed Roth devised an easy-to-program algorithm for simulating

1. Serial fault simulation is slower faults in combinational circuits.
2. Parallel fault simulation O(n3) n: number of gates All gates are assumed to have zero delay. The circuit is
3. Deductive fault simulation o(n2) simulated for a vector in the true-value mode.
4. Concurrent fault is faster than deductive fault simulation
Next, faults are analyzed one at a time to determine which
faults are detected by the presently simulated vector.
Memory Usage
Serial fault and parallel fault simulation: no problem The analysis is based on Roth’s D-calculus that allows a
Deductive fault simulation, dynamic allocate memory and hard to composite representation of a signal in the fault-free and
predict size. faulty circuits.
Concurrent fault simulation: more sever than deductive fault
simulation.

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Example

Assuming a two-value simulation, the signal state (fault-free

value, faulty value) can take four possible assignments. These
are symbolically denoted as:0=(0,0),1=(1,1), D=(1,0) and
D’=(0,1).
To simulate a fault, we start at the fault site. If the fault is
activated, a D or D’ is placed at the fault site. These values are
propagated through fan-outs and gates, using the true-values or
the newly placed symbolic states. If a D or D’ reaches a
primary output, the fault is considered detected at that output. Consider the multiplexer circuit with input vector 101 as shown in Figure
The signal values are restored to their true-values before
The binary logic values shown are a result of the true-value simulation.
analyzing the next fault. When all faults have been analyzed, we consider the s-a-1 fault on the lower fanout of the second primary input.
we proceed with the simulation of the next vector. The fault is active and the input to the inverter is changed to D’
Now perform an event-driven simulation by evaluating the active gates.The 0-
D’ event makes the NOT gate active. Its evaluation puts a 1->D at its output
making the lower AND gate active.
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 Alternatives to Fault Simulation

Evaluation of AND causes an output event 1->D and the Because fault simulation is very time consuming and difficult for
activation of the OR gate Evaluation of OR produces 1->D at large circuits, alternatives to avoid “true” fault simulation have
the output. indicating the detection of the fault. Next, we been developed.
restore the signals to the original fault-free values and apply These alternatives require only one fault-free simulation or very
the procedure to the next fault, which is not detected. few fault simulations, so the run time is significantly reduced.
The alternatives give approximate fault coverage numbers. It
should be noted that these alternatives are probably
acceptable if the purpose of fault simulation is to estimate the
quality of test patterns (ie, fault grading).
These alternatives are probably not acceptable when it comes to
diagnosis. This is because diagnosis requires exact
information about which patterns detect which faults.

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Alternatives to Fault Simulation Techniques Testability Measures

Toggle Coverage • Controllability and Observability

Fault Sampling
Critical Path Tracing • Combinational SCOAP measures
Statistical Fault Analysis • Combinational circuit example
• Sequential SCOAP measures
• Sequential circuit example

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Controllability and Observability SCOAP Controllability and Observability

Controllability for a digital circuit is defined as the difficulty of setting Goldstein invented an algorithm to determine the difficulty of controlling
a particular logic signal to a 0 or a 1. Observability for a digital (called controllability) and observing (called observability) signals in
digital circuits. Goldstein was the first to propose a systematic, efficient
circuit is defined as the difficulty of observing the state of a logic algorithm to compute these measures, which he called SCOAP(Sandia
signal. The controllability and observability measures are useful Controllability/Observability Analysis Program) It is still widely used.
because they approximately quantify how hard it is to set and SCOAP consists of six numerical measures for each signal (l) in the circuit.
observe internal signals of a circuit. Testability analysis usually has 1. Combinational 0-controllability, CC0(l) L = list
two significant attributes: 2. Combinational 1-controllability, CC1(l)
It involves circuit topological analysis, but no test vectors. It is a static 3. Combinational observability, CO(l)
type of analysis. It has linear complexity, because otherwise 4. Sequential 0-controllability, SC0(l)
testability analysis is pointless and one might as well use automatic 5. Sequential 1-controllability, SC1(l)
test-pattern generation (ATPG) or fault simulation . Nearly all of the 6. Sequential observability, SO ( l)
testability analysis methods in this chapter, and most of those used The controllabilities range between 1 and ꝏ and observabilities lie
between 0 and ꝏ
in industry, have these attributes

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SCOAP Controllability and Observability Combinational Controllability Calculation rules
The CC0 and CC1 values of Primary input( PI) is set to 1
The SC0 and SC1 values of Primary Inputs are set to 0
The CO and SO values of Primary Outputs are set to 0

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Combinational Observability Calculation rules SCOAP controllability calculation.

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SCOAP controllability calculation SCOAP Observability calculation

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SCOAP Observability calculation Combinational Circuit Example

1. We first assign (1,1) to all Primary inputs: R, PPI7, and PPI8.

2. Next, these ordered pairs are propagated to all fan-out branches of the primary
inputs(Pis) , leading to the labeling of the top two inputs of gate 4, the top input
of gate 5, and the inputs to INVERTERS 1 and 2 with (1,1).

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Combinational circuit with controllabilities through level 2

Referring to chart , we see that for the inverter,

This leads to the outputs of INVERTERS 1 and 2 being labeled with (2,2), and both
inputs of logic gate 3 being labeled with (2,2), as shown in Figure. Next, we process
AND gate 3. for the AND gate:

This causes the AND gate 3 output, the bottom inputs to gates 4 and 5, and PP08 Next, the algorithm processes logic gates at level number 3. For NOR gate 4:
to be labeled with (3,5)

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Final combinational circuit controllability's

Hence, logic gate 4 and the top input of logic gate 6 in
Figure are labeled with (2,6). For AND gate 5:

Therefore, logic gate 5, the bottom input of logic gate 6, and PO Z in Figure are
labeled with (2,7). Now we process OR gate 6 at level 4. For OR gate 6:

This causes OR gate 6 and PP07 in Figure 6.7 to be labeled with (5,7). The
circuit is now completely labeled with the final controllability's.

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Computation of observabilities

Next, we renumber the circuit level numbers from primary We process logic gates in level order from POs backwards to PIs. In Figure we assign 0
to PO Z and PPOs PPO7and PPO8.
outputs (Pos) backwards to PIs, so that each gate is This causes observability 0 to be assigned to gate 6, as well. We cannot yet assign
labeled with the maximum distance in logic gates of any observabilities to gates 5 and 3, because they are fanout stems, and not all fanout
branch observabilities are known. So, we process OR gate 6 at level 1 in Figure
of its fan-outs from a PO. above. For each input,

Combinational circuit with observabilities through level 1

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Next, we process NOR gate 4 at level 2 in Figure . for a three-input OR gate:

Next, we process AND gate 3 at level 3 in Figure 6.10, according to Figure

Next, we process AND gate 5 at level 2 in Figure . All of its fanout branch
observabilities are now known. Since its stem observability is the minimum of all
branch observabilities, Figure 6.3, for a two-input AND gate:
Now we process the two INVERTERS at level 4. From Figure

for a two-input AND gate:

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Final combinational circuit observabilities

For INVERTER 1, we get

For PI R, which is a fanout stem, the observability is the minimum of all branch
observabilities, so

For PPI PPI8, the observability is 4.

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 Sequential SCOAP Measures

Note that the computational complexity of this algorithm is where There are two main differences in the sequential measures
n is the number of gates. This is because we process all inputs from the combinational controllability and observability
and logic gates once in the forward pass to compute measures:
controllabilities, and then processes all logic gates and inputs 1. One increments the sequential measure by 1 only when
again in the backward pass to compute observabilities. We see signals propagate from flip-flop inputs to Q or Q outputs,
that the fanout branches from PPI PPI7 to gate 4 and from R to or from flip-flop outputs backwards to D, C (clock), SET,
gate 4 are the hardest signals to observe. The hardest signals to or RESET inputs.
control to logic 1 are PPO7 and all fanouts from gate 5. The 2. One must iterate in calculating controllability numbers in
hardest signal to control to logic 0is PPO7. sequential circuits because of feedback loops involving
flip-flops.

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D Flip-Flop Equations
Sequential controllabilities SC0 and SC1 roughly measure the number
of times var ious flip-flops must be clocked to control a signal. Thus,
if a given line l can only be set to 1 by clocking flip-flop a twice and
flip-flop b three times, then we would ex pect Sequential
observability SO measures the number of times various flip-flops
must be clocked to observe a signal. In a sequential circuit, the In order to control the Q line to 1, one must set D to 1, cause a falling clock (C) edge
combina tional controllabilities and observabilities roughly measure (first a 1 and then a 0), and control the RESET line to 0 to avoid clearing Q. The
the number of lines that must be set, over all of the required clock combinational and sequential difficulties of controlling Q to a 1 are:
periods, in order to control or observe a combinational signal. The
sequential controllability and observability equations for basic logic
gates differ from the equations for combinational gates only in that a
1 is not added as we move from one level of logic to another, but
rather a 1 is added when a signal passes through a flip-flop. The
procedure to convert the com binational measure formulas of CC1 measures how many lines in the circuit must be set to make Q as 1, whereas
Figures 6.2 and 6.3 to those of sequential measures is given in SC1 measures how many flip-flops in the circuit must be clocked to set Q to 1.
Table 6.1. 6.1 SCOAP Controllability and Observability There are two ways to set Q to a 0. We can either use the RESET line and apply a
falling edge to clock C, or clock a 0 into Q through the D line. Thus,

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There are three ways to indirectly observe the clock line C: (1) set Q to 1 and clock
in a 0 from D, (2) set Q to 1 and synchronously apply RESET, or (3) set Q to 0 and
clock in a 1 from D while holding RESET to 0. Thus,
The D line can be observed at Q by holding RESET low and generating a falling
edge on the clock line C:

RESET can be observed by setting Q to a 1 and using RESET:

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Sequential Circuit Example

On circuit lines in this example, CC0, CC1, and CO are

shown as (CC0,CC1)CO and SC0, SC1, and SO are
shown as [SC0, SC1]SO below the combinational
measures. The observabilities are always shown in bold
to avoid confusion. The forward level numbers for logic
gates and flip-flops are shown cir cled over the gates.
For backward level numbers during observability
calculation, we just use the forward level numbers in
Figure shows the initial measures for the. Signals R and CL, and all of their decreasing order from 5 down to 1. For level numbering
fanouts, are set to (CC0,CC1)=(1,1) and [SC0, SC1]=[0,0] all other nodes flip-flops, we treat them like ordinary logic gates, and
particularly Q1, Q2 are set to (CC0,CC1)=(ꝏ,ꝏ) and [SC0,SC1]=[ꝏ,ꝏ]
ignore their feedback loops.

Initialization for computing sequential SCOAP measures

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Sequential circuit measures

after one iteration.
we start the input to output computation of controllabilities.
Thus the output of INVERTER 1 is set to
(CC0,CC1)=(2,2) and [SC0, SC1]=[0,0] INVERTER 2 is
more interesting, because the feedback loop means that
its measures must remain at ꝏ For AND gate 3, since 0
is a controlling value, we can determine CC0 and SC0
measures . However, its CC1 and SC1 measures remain
at ꝏ A similar situation arises at AND gate 5 . For NOR
gate 4,CC0(4)=min(CC1(R ),CC1(Q1),CC1(3))+1=min(1,
ꝏ, ꝏ)+1=2 Similarly SC0(4)=0.

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Figure below shows the situation after two iterations. CC0(7)=CC0(6)+CC1(CL)+CC0(CL)=7+1+1=9. The CC1,SC0
and SC1 measures for both FFs.
Now, output controllabilities of INVERTER 2 change to(ꝏ,6) and
(ꝏ,1) This allows AND gate 3’s output CC1 measure to
change to 9 and its output SC1 measure to change to 1. For
NOR gate 4, the output 1-controllabilities are now defined,
because all of its input 0-controllabilities have been defined,
so gate 4 has CC1=14 ad SC1=1. AND gate 5 cannot have its
output measures updated, because the 1-controllabilities of its
and inputs are still undefined. The 1-controllabilities of OR
gate 6 can now be defined, because its topmost input now
has defined 1-controllabilities. So, CC1(6)=15 and SC1(6)=1.
At this point, Figure above shows the situation where the
controllabilities of both D inputs to the flip-flops are now
completely defined.

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Figure below shows the situation after three iterations. flip-flop 7s output controllabilities to become (9,17) and
[1,2]. Flip-flop 8’s controllabilities become (5,11) and
[1,2]. INVERTER 2’s output controllabilities become
(12,6) and [2,1]. However, this causes no change in AND
gate 3’s output controllabilities. NOR gate 4’s CC1 stays
at 14, and AND gate 5’s CC1 is now defined as 27 and
its SC1 is now defined as 3. The changes at gates 4 and
5 now cause no change at gate 6: CC1 stays at 15.
Figure 6.15 illustrates the situation at this point.

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Sequential circuit final observability

measures.

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 Basics of CombinationalATPG

The only difficult step is computing CO from line CL to 7 which is • Functional vs Structural Test
CO=CO(Q)+CC1(CL)+CC0(CL)+CC0(D)+CC1(Q)=10+1+1+7 • ATPG
+17=36.
For same line
• Types of ATPG Algorithms
SO=SO(Q)+SC1(CL)+SC0(CL)+SC0(D)+SC1(Q)+1=1+0+0+0 • Fault propagation and Detection
+2+1=4 • Redundancy Identification
For the CO of the line from CL to line 8 • Fault cone and D-Frontier approach
CO=CO(Q)+CC1(CL)+CC0(CL)+CC0(D)+CC1(Q)=22+1+1+3
+11=38
Similarrly
SO=SO(Q)+SC1(CL)+SC0(CL)+SC0(D)+SC1(Q)+1=2+0+0+0
+2+1=5 Therefore,CO(CL)=min(36,38)=36 and
SO(CL)=min(4,5)=4

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Automatic test-pattern generation Definition of ATPG

Automatic test-pattern generation (ATPG) is the process of • ATPG algorithms inject a fault into a circuit, and then use a variety
generating patterns to test a circuit, which is described strictly of mechanisms to activate the fault and cause its effect to
with a logic level netlist (schematic.) propagate through the hardware and manifest itself at a circuit
output.
These algorithms usually operate with a fault generator program,
• The output signal changes from the value expected for the fault-free
which creates the minimal collapsed fault list so that the
circuit, and this causes the fault to be detected.
designer need not be concerned with fault generation.
• E-beam testing allows observation of internal circuit signals by
In a certain sense, ATPG algorithms are multi-purpose, in that “developing” a picture of the circuit that shows the internal nodes
they can generate circuit test-patterns, they can find redundant charged to logic 0 in one color and those charged to logic 1 in a
or unnecessary circuit logic, and they can prove whether one different color.
circuit implementation matches another circuit • This eliminates the need to propagate fault effects to primary
implementation. outputs (POs.) However, this method is impractically expensive, is
only used for very specialized applications

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Scan-Design for Microprocessor Testing

• Fault effects are propagated from an AND/NAND • A scan-chain inserter adds special-purpose MUX and
gate input to its output by setting other inputs to 1, clocking hardware to every circuit flip-flop for testing.
a non- controlling value for AND/NAND.
• In scan mode, the flip-flops are converted into a giant shift
• Fault effects are propagated from an OR/NOR gate
register, and the entire state of the microprocessor can be
input to its output by setting other inputs to 0, a non-
controlling value for OR/NOR. shifted out through a special test-mode port, scan_out.
• Fault effects are propagated from an XOR/XNOR • Desired initial flip-flop state can be serially shifted into
gate input to its output by setting all other inputs to 0 or flip-flops through a special test-mode port called scan_in.
1 as is convenient.
• Scan design coupled with combinational ATPG is the
• ATPG algorithms are valuable, in that they propagate most popular test method with microprocessors and other
an abnormal voltage reading from the internals of the
VLSI chip designers because it is very likely to generate a
circuit to a PO, where an ATE can examine the
voltage and determine whether it is correct. test set with close to 100% fault coverage.

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Scan-Design for Microprocessor Testing Search Space Abstractions

• The approach converts a difficult sequential circuit ATPG • All ATPG programs need a data structure
problem into a more tractable combinational circuit ATPG describing the search space for test patterns:
problem, at the expense of:
– Binary Search Trees
i. Using 5 to 20% of the chip area for the scan chain
hardware in large chips. – Binary Decision Diagrams
ii. Slowing down all flip-flops because of the added scan
chain MUX delays.
iii. Reserving one or more additional pins for
scan chain control.
iv. Lengthening the test-pattern sequence.

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Binary Search Trees Binary Search Trees

• The leaf nodes of the tree are labeled with the good
machine output that the corresponding input values will
cause.
• All ATPG algorithms implicitly search this tree to find
test patterns, and in the worst case, must examine the
entire tree to prove that a fault is untestable.

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Binary Decision Diagram Algorithm Completeness

• BDD – Follow the path from source to sink node – the • Definition: The algorithm is complete if it ultimately can
product of literals along the path gives the Boolean value search the entire binary decision tree, as needed, to
at the sink generate a test
• Rightmost path: AB C = 1 • Untestable fault – no test for it even after the entire tree
searched
• Problem: Size varies greatly
• Combinational circuits only – untestable faults are
with variable order
redundant, showing the presence of unnecessary
hardware

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Algorithm Completeness ATPGAlgebras:
Roth’s 5-Valued Algebras
• A test vector requires that a difference be maintained The ATPG algebra is a higher-order Boolean set notation with the purpose of
between the two machines representing both the “good” and the “failing” circuit (or machine) values
simultaneously. This has the advantage of requiring only one pass of ATPG
• It is computationally faster to represent both machines to determine signal values for both machines.
in the algebra, rather than maintaining them separately.
• Roth showed how multiple-path sensitization, required
to test certain combinational circuits, could be done with
his five-valued algebra given in Table next

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ATPG Algebra Roth’s and Muth’s Higher-Order Algebras

• Represent two machines, which are

simulated simultaneously by a computer
program:
▪ Good circuit machine (1st value)
▪ Bad circuit machine (2nd value)
• Better to represent both in the algebra:
▪ Need only one pass of ATPG to solve both
▪ Good machine values that preclude bad machine
values become obvious sooner and vice versa
• Needed for complete ATPG:
▪ Combinational: Multi-path sensitization, Roth Algebra
▪ Sequential: Muth Algebra -- good and bad machines may have
different initial values due to fault

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Types of ATPG Algorithms Exhaustive Algorithm

• Exhaustive • For the n-input circuit, generate all 2n input patterns

• Random pattern generation • Infeasible, unless the circuit is partitioned into cones of
• Symbolic-Boolean difference logic, with  15 inputs
▪ Perform exhaustive ATPG for each cone
• Path sensitization
▪ Misses faults that require specific activation patterns for
multiple cones to be tested

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Random-Pattern Generation Boolean Difference Symbolic Method
Use Shannon’s Expansion Theorem to characterize Boolean circuits. For example, an
• Flow chart for arbitrary Boolean function F(X1,X2, ….Xn) can be expanded about any variable, say
method X2 as:
• Use to get tests for
60-80% of faults,
then switch to D- Assuming logic function g = G (X1, X2, …, Xn)for the
algorithm or other fault site we express o/p as
ATPG for rest fj = Fj (g, X1, X2, …, Xn) 1jm
Xi = 0 or 1 for 1  i n
Notice that these output equations express the circuit outputs in terms of the
primary inputs Xi and the fault site signal g

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Example

The Boolean difference, or Boolean partial derivative, of a

circuit as:

They express the fault detection requirements for g s-a-0 at output fj as:

Equ 01

Equ 02

Equation 01 says that to test a stuck-at-0 fault at g, the logic gate G must
sensitize the fault site by driving it to logic 1. Equation 02 says that in order
to detect the fault, the Boolean difference of some output with respect to
the fault site g must be 1 (i.e., the output must change its signal value when
the fault site signal switches from 1 to 0.) Unfortunately, due to high
complexity the Boolean difference is not an efficient way to compute test
patterns for large circuits.
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Path Sensitization Methods Path Sensitization Methods

• Path sensitization at the logic gate level of • Test set by considering the individual faults on all wires in a
representation is currently the preferred ATPG method. circuit is not attractive from practical point of view.
• The approach consists of three steps: • Too many wires and too may faults.
i. Fault sensitization • A better alternative to deal with several wires that form a path.
ii. Fault propagation • Fault sensitization, in which a stuck-at fault is activated
iii. Line justification
by forcing the signal driving it to an opposite value from
the fault value.
• This is necessary to ensure a behavioral difference
between the good circuit and the faulty circuit.
• Fault sensitization is also known as fault activation or
fault excitation.

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Path Sensitization Methods Path Sensitization Methods

• Fault propagation, in which the fault effect is propagated • Line justification, in which the internal signal
through one or more paths to a PO of the circuit. assignments previously made to sensitize a fault or
• For some faults, it is necessary to simultaneously propagate its effect is justified by setting PIs of the
propagate the fault effect over multiple paths to test it. circuit.
• In general, the number of paths may rise exponentially in
the number of logic gates in the circuit.
• Fault propagation is also known as path sensitization

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Path Sensitization Method Circuit Example Path Sensitization Method Circuit

Example
1 Fault Sensitization Label PIs and POs with capital letters, and every other signal line in the
2 Fault Propagation circuit with a lower-case letter.
3 Line Justification Note that PI B (a fan-out stem) fans out to two AND gates, whose
outputs are h and i.
The fan-out branches from B to the inputs of the two AND gates are
labeled f and g.
It frequently happens that tests for faults on B are different from tests
for faults on f, which are also different from tests for faults on g.
That is why we must label every distinct line or wire of a signal net.
We generate a test for B stuck-at-0.
For fault sensitization, we set B to 1, and this leads to the signal
assignments f=D and g=D

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Path Sensitization Method Circuit Path Sensitization Method Circuit

Example Example
This results in the signal assignments A=1, j=0 and E=1.
Fault propagation requires us to select among three
Line justification now requires us to justify any internal signals where
scenarios: we assumed a value assignment.
In this case, the only one is j.
1. Propagation along the path f – h – k – L, or
We can assign i=1 to justify j=0 by backwards logic simulation of
2. Propagation along the path g– i– j– k– L, or inverter j.
However, AND gate i then needs to have an output of 1, but it already
3. Simultaneous propagation along both paths f– h– has input g=D, there is no way to get i=1 when an input already was
k– L and g– i– j– k– L. set to D.
Therefore, we backtrack and retract the assignment j=0 and try the
Choose the path f – h – k – L for propagation. alternative assignment j=1.
However, this immediately blocks fault propagation along path f – h –
This means that for every AND gate along the path, the k – L. We conclude that the only viable options may be scenarios 2
off-path inputs should be set to non-controlling values and 3 listed above.
(1), and similarly for every OR gate along the path the
off-path inputs should be set to 0.
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Path Sensitization Method Circuit Path Sensitization Method Circuit
Example Example
We choose scenario 3. We change our fault propagation approach, and We set C=1,h=0 and E=1 to propagate the fault. Forward logic
now make the assignments A=1 and C=1and E=1 to ensure fault simulation givesi=D, j=D’ and k=D’ It remains to justify h=0.
propagation.
This is achieved by backwards logic simulation for AND gate h,
Forward logic simulation from these assignments yields i=D, with input f=D by setting input A=0 The only test for B stuck-
h=D,j=D’ and k=1 since D or D’=1
at-0 is ABCE=0111 and this produces the output L=0 in the
The D-frontier is the cut-set separating the circuit portion labeled with good machine, and L=1 in the failing machine.
Xs from the portion labeled with D or D’ where we include only the
D or D’ signals closest to the outputs in the frontier.
Finally, L=1and the D-frontier has disappeared at OR gate k, which
means that the fault is untestable via these multiple paths. It only
remains to return and try fault propagation along path g– i– j– k– L.

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Path Sensitization Method Circuit Example Path Sensitization Method

Circuit Example
▪ Try path f – h – k – L blocked at j, since there is no way ▪ Try simultaneous paths f – h – k – L and
to justify the 1 on i
g – i – j – k – L blocked at k because D-frontier (chain
of D or D) disappears

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Path Sensitization Method

Circuit Example Basics of Combinational ATPG

▪ Final try: path g – i – j – k – L – test found. • Functional vs Structural Test

• ATPG
• Types of ATPG Algorithms
• Fault propagation and Detection

• Redundancy Identification
• Fault cone and D-Frontier
approach
• PODEM Algorithm
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ATPG Algorithms D-Calculus and D-Algorithm (Roth)

First algorithm was Roth’s D-Algorithm (D-ALG) which Definitions1:

established the calculus and algorithms for ATPG using D- The singular cover of a logic gate is the minimal set of input signal assignments needed
cubes. to represent essential prime implicants in the Karnaugh map of that logic gate, for
both output cases of 0 and 1. Figure shows an example. Table gives the singular
The next development was Goel’s PODEM algorithm.
cover for the AND and NOR gates in this circuit.
He efficiently used path propagation constraints to limit the
ATPG algorithm search space, and introduced the notion of
back-trace.
The third significant development was Fujiwara and Shimono’s
FAN algorithm.
They efficiently constrained the back-trace to speed up search,
and took advantage of signal information to limit the search
space.

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Defination2: The D-intersection operation D Algebra

Defined as the set of circumstances under which different cube

labelings for different logic gates can coexist in the circuit.
The rule is that if one cube assigns a specific signal value, then
other cubes must assign either that same signal value or X to
the signal.
Equations below give the simpler rules of cube intersection.

There are two kinds of D-cubes: (1) Those where only one input coordinate is D or
and (2) Those where multiple input coordinates are D or T

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Definition 3: D-frontier Definition 4: J-frontier

The D-frontier consists of all the gates in the circuit whose output value is x The J-frontier consists of all the gates in the circuit whose
and a fault-effect (D or D’)is at one or more of its inputs. In order for this to output values are known (can be any of the five values in
occur, one or more inputs of the gate must have a “don’t care” value. For
example, at the start of the D algorithm, for a target fault f there is exactly
the 5-valued logic) but is not justified by its inputs. Figure
one D (or D’) placed in the circuit corresponding to the stuck-at fault. All illustrates an example of a J-frontier.
other signals currently have a “don’t care” value. Thus, the D-frontier
consists of the successor gate(s) from the line with the fault f .Example:

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Definition 5:fault cone Definition 6: forward implication

The fault cone is the portion of a circuit whose signals are A forward implication results when the inputs to a logic gate
reach able by a forward trace of the circuit topology are significantly labeled so that the output can be
starting at the fault site. uniquely determined. Example:
Example:

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Definition 7:Backward implication Definition 8:Implication stack

Backward implication is the unique determination of all The implication stack is a push-down stack that records each
inputs of a gate for given output and possibly some of signal set in the circuit by the ATPG algorithm, and whether
the inputs. the alternate signal value has already been tried for that signal.
Example: This is an efficient way of representing which portion of the
circuit’s binary decision tree has already been traversed by the
ATPG algorithm, so that search of that tree portion is not
repeated. Example: (Refer circuit in next slide)

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OR and Not Operation Implication Table Example:

In the circuit assume that signals were set in the order A, C, E, and B.
Furthermore, assume that the ATPG algorithm first tried setting signal B to 1, and
that this failed, so B has been set, instead, to 0. Figure 7.15 shows the implication
stack.

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Backtrack Condition: Definition 9: Back-trace

The ATPG algorithm may decide to backtrack (or backup) when Back-trace is an operation used to determine which PI should be set to achieve
it finds one of the following conditions: an objective. It is most frequently implemented using Gold stein’s
combinational controllability and observability measures.
• The D-frontier becomes empty, meaning that there is no
possibility of propagating a fault effect through the circuit.
• A signal must be simultaneously set to both 0 and 1 in order to
satisfy the testing conditions for the test vector, but this is
obviously impossible.
When a backtrack occurs, the ATPG algorithm removes one or
more signal assignments from the implication stack, and then
selects the alternate assignment for a signal already on the
stack. This causes the binary decision tree to be explored in The circuit shows the objective J=1.
depth-first fashion For OR gate J, we wish to trace backwards through it and find the easiest way to
justify J=1 at the PIs.
We need only set one input of OR gate J to 1, so we should pick the easiest one to set
(i.e., the one with lowest CC1), which is the bottom one
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Idea of D Algorithm
That means that back-trace determines that satisfies the objective
1. Generate the fault
with the least effort.
If the objective were J=0, then matters would be different. 2. Propagate the fault to one of the output
To justify that objective, we would set all three inputs to OR gate 3. Back propagate to get consistent assignments for inputs
J to 0.
We should begin by picking the hardest sub-objective first, which
will be setting the top input to 0, since it has the highest
controllability difficulty for logic 0 (CC0.)
We achieve a 0 on the top input to OR gate J with the signal
assignments A=1 and B=1 and by tracing the hardest
backwards path first, followed by setting E=0.
This allows us to proceed to justifying the middle input of J to 0,
which we achieve with the assignment C=0. Finally we assign
D=0 to justify J=0.
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Step2:
Example to illustrate the 3 steps: Step -1

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Step -3 Example-2

Consider the circuit of Figure and assume that d stuck at 0.

Solution:

Assign b and c as 1,1. So the test vector is 0,1,1,0,0

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Example-3
Example 3 Fault A sa0
◼ Step 1 – D-Drive – Set A = 1

D
1 D

27
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Step 2 -- Example 3 Step 3 -- Example 3

◼ Step 2 – D-Drive – Set f = 0 ◼ Step 3 – D-Drive – Set k = 1

1
D
0 0
D D D D
1 D 1 D

28 29
 Step 4 -- Example 3 Step 5 -- Example 3
◼ Step 4 – Consistency – Set g = 1 ◼ Step 5 – Consistency – f = 0 Already set

1 1 1 1
D D
0 0
D D D D
1 D 1 D

30 31

Step 6 -- Example 3 D-Chain Dies -- Example 3

◼ Step 7 – Consistency – Set B = 0
◼ Step 6 – Consistency – Set c = 0, Set e = 0 ◼ Fault detected at PO, although D-Chain dies
X
1 1 1 1
0 D 0 D
0 0 0
0 0
D D D D
1 D 1 D

◼ Test cube: A, B, C, D, e, f, g, h, k, L

32 33

Steps for example-3

PODEM (Goel) Path Oriented Decision Making.
In the late 1970s, semiconductor DRAM memory was introduced
into IBM mainframe computers, and this memory required
error correction and translation (ECAT) circuits to raise its
reliability to acceptable levels.
Unfortunately, D-ALG failed to generate tests for these circuits,
because its search was too undirected.
ECAT circuits consists of XOR logic gate trees, where all
external gate inputs have to be set before an output signal is
defined.
Goel [258] introduced the PODEM* algorithm to deal with these
circuits. Many standard ATPG concepts (described earlier)
came from PODEM:

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 PODEM PODEM High-Level Flow
• Backtracing obtained a PI assignment given the initial
objective. 1. Assign binary value to unassigned PI
• PODEM used the length of paths between its initial objective 2. Determine implications of all PIs
and POs to measure the difficulty of sensitizing a path. 3. Test Generated? If so, done
• This is logic level of the logic gate at the start of the path,
4. Test possible with more assigned PIs? If maybe, go to Step 1
which was the minimum number of logic gates between the 5. Is there untried combination of values on assigned PIs? If
start of the path and any PO. not, exit: untestable fault
• Objectives were selected by level to pick the easiest objective 6. Set untried combination of values on assigned PIs using
to achieve. objectives and backtrace. Then, go to Step 2
• After objectives were selected, backtracing determined PI
assignments to justify these objectives.
• Determined using controllability measures.

36 37

Step 1: Define an objective (fault activation, D-drive, or

line justification)
Step 2: Backtrace from site of objective to PIs (use testability
measure guidance) to determine a value for a PI
Step 3: Simulate logic with new PI value
If objective not accomplished but is possible, then continue
back-trace to another PI (step 2)
If objective accomplished and test not found, then
define new objective (step 1)
If objective becomes impossible, try alternative back-
trace (step 2)
• Use X-PATH-CHECK to test whether D-frontier still there –
a path of X’s from a D-frontier to a PO must exist.

38
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• For selecting an objective, PODEM found the logic gate with • If all logic gate inputs had to be set to achieve the objective,
D or D on its inputs that was closest to a PO. PODEM back-traced through the hardest-to-control input first.
• If X-PATH-CHECK indicated that a path existed with
unassigned signals from that gate to a PO. • If controlling that input failed, it wasted no time trying easier-
• It would set the gate objective of obtaining a 1 on that gate to-control inputs.
output if it was an AND or an OR gate and a 0 if it was a
NAND or a NOR gate to propagate the D forward. • If only one logic gate input needed to be set to achieve the
• Opposite objectives were used to propagate D. objective, PODEM back-traced through the easiest-to-control
• Next, backtracing occurred by tracing backwards from the input.
objective.
• The selected input during back-tracing became the next
objective to satisfy.

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Example:
PODEM Objectives and Decisions for f Stuck-At-0

Consider the target fault f stuck-at-0. First, PODEM initializes all gate values
to x. Then, the first objective would be to set f =1. The back-trace routine
selects c=0 as the decision. After logic simulation, the fault is excited, together
with e = h = 0. The D-frontier at this time is g. The next objective is to advance
the D-frontier, thus get Objective() returns a =1. Because a is already a primary
input, back-trace() will simply return a =1. After simulating a = 1, the fault-
effect is successfully propagated to the primary output z, and PODEM is
finished with this target fault with the computed vector abc = 1X0.

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Example 2 : s sa1 Example 2 -- Step 2 s sa1

◼ Initial objective: Set r to 1 to sensitize fault
◼ Select path s – Y for fault propagation

sa1

45
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Example 2 -- Step 3 s sa1 Example 2 -- Step 4 s sa1

◼ Backtrace from r ◼ Set A = 0 in implication stack

1 1
0

sa1 sa1

46 47
Example 2 -- Step 5 s sa1 Example 2 -- Step 6 s sa1
◼ Forward implications: d = 0, X = 1 ◼ Initial objective: set r to 1
1 1
1 1
0 0
0 0
sa1 sa1

48 49

Example 2 -- Step 7 s sa1 Example 2 -- Step 8 s sa1

◼ Backtrace from r again ◼ Set B to 1. Implications in stack: A = 0, B = 1
1 1
1 1
0 0
0 0
sa1 1 sa1

50 51

Example 2 -- Step 9 s sa1 Backtrack -- Step 10 s sa1

◼ Forward implications: k = 1, m = 0, r = 1, q = 1, ◼ X-PATH-CHECK shows paths s – Y and s – u – v – Z
Y = 1, s = D, u = D, v = D, Z = 1 blocked (D-frontier disappeared)
1 1
1 1
0 0
0 0
1 0 sa1 D 1 sa1
1 1
D
D
1

52 53
 Step 11 -- s sa1 Backtrack -- s sa1
◼ Set B = 0 (alternate assignment) ◼ Forward implications: d = 0, X = 1, m = 1, r = 0,
s = 1, q = 0, Y = 1, v = 0, Z = 1. Fault not sensitized.
1
1 0
0 0
0
0 1
0 sa1 1 sa1
1
0
1
0
1

54 55

Step 13 -- s sa1 Step 14 -- s sa1

◼ Set A = 1 (alternate assignment) ◼ Backtrace from r again

1 1
1 1

sa1 sa1

56 57

Step 15 -- s sa1 Backtrack -- s sa1

◼ Set B = 0. Implications in stack: A = 1, B = 0 ◼ Forward implications: d = 0, X = 1, m = 1, r = 0.
◼ Conflict: fault not sensitized. Backtrack
1
1 0
1 1
0
0 0 1
sa1 1 sa1
1
0

1
0
1

58 59
 Step 17 -- s sa1 Fault Tested -- Step 18 s sa1
◼ Set B = 1 (alternate assignment) ◼ Forward implications: d = 1, m = 1, r = 1, q = 0,
s = D, v = D, X = 0, Y = D
0
1 1
1 1
1
1 sa1 1 1 sa1 D
D
0

D
D
X

60 61

PODEM’s objectives/implication stack

62 63

Backtrace (s,
vs) Pseudo- Challenges of Sequential ATPG
Code 1. FF/Latch states are uncontrollable and unobservable
v = vs;
while (s is a gate output) FF/Latches are unknown initial states.
if (s is NAND or INVERTER or NOR) v = v; 2. Long run time
if (objective requires setting all inputs) Comb ATPG complexity O(2number_of_PI)
select unassigned input a of s with hardest Sequential ATPG Complexity O(2number_of_PI x 9number_of_FF)
controllability to value v; 3. Large memory space required-Time frame expansion method
else 4.Low fault coverage-Much worse that combinational ATPG
select unassigned input a of s with easiest
controllability to value v;
s = a;
return (s, v) /* Gate and value to be assigned */;

64
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ATPG for Single-Clock Synchronous Circuits
A synchronous circuit consists of combinational logic and flip- The combinational logic has two types of inputs.
flops, and is often represented in the form shown in Figure. 1. Those at the top are external inputs known as primary inputs (PI).
The circuit in the large block is purely combinational. Some 2. The inputs on the left side, called pseudo-primary inputs (PPIs) or
outputs of this block feed a set of flip-flops, which control present state (PS), are supplied by the flip-flops.
some inputs of the block. Similarly, the combinational logic has two types of outputs.
Those at the bottom are externally observable and are known as
primary outputs (PO).
The outputs on the right are called pseudo-primary outputs (PPO) or
next state (NS) and feed into flip-flops
Input vectors are applied to PIs and observable outputs are produced at
POs. It is the lack of a direct contact with the PPI and PPO that makes
the detection of a fault in the combinational logic difficult.

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Time-frame expansion.

The combinational part of the circuit is modeled at the Boolean

gate-level and all single stuck-at faults are considered in it. Idea: Replicate circuits and connect time frames by wires.
Flip-flops are treated as ideal memory elements, whose clock In this method a model of the circuit is created such that tests can
signal is not explicitly represented. be generated by a combinational ATPG method.
Thus, no faults in the clock signal are modeled. This procedure is very efficient for circuits described at the
Similarly, internal faults of flip-flops are not modeled; their Boolean gate-level.
output and input faults are modeled as faults on input and Its efficiency degrades significantly with cyclic structure,
output signals of the combinational logic. multiple-clocks, or asynchronous circuitry.

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Time Frame Expansion

The general model for a sequential circuit is shown in Figure Fig illustrates an example of a sequential circuit which is unrolled
where flip flops constitute the memory/state elements of the into several time frames, also called an iterative logic array of
design. All the flip-flops receive the same clock signal, so no the circuit. For each time frame, the flip-flop inputs from the
multiple clocks are assumed in the circuit model. previous time frame are often referred to as pseudo primary
inputs with respect to that time frame, and the output signals to
feed the flip-flops to the next time frame are referred to as
pseudo primary outputs. Note that in any unrolled circuit, a
target fault is present in every time frame.

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Differences between combinational and Time frame expansion example
sequential circuits.
The first difference is that a test for a fault in a sequential circuit Step 1:Create the fault
may consist of several vectors. Step 2: Create time frame 0 by removing FF
A combinational ATPG, on the other hand, is capable of a0=1, y1=0 and Y1=D’
generating only a single vector for a target fault.
The second difference is due to the uninitialized (assumed to be
unknown) memory states of the sequential circuit.
A combinational ATPG can deal with unknown (X) signal states,
but we find that the five-value logic system, usually effective
for combinational circuits, is insufficient for sequential
circuits.

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Step 3: Fault effect propagate to time frame 1, Step 4: Fault activation back to time frame -1, a-1=0
a1=1.Evnthough fault is detected at Primary out we didn’t
justified PI zero.

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Serial Adder Example Examples which illustrate aspects of sequential circuits.

In the serial adder, When the nth bits An , Bn are applied to this
circuits, it produces the sum Sn and loads the carry Cn+1 in the
flip-flop. Thus , two 32 bits binary integers are added as follows:
Initialization – A 00 input is applied to initialize the flip-flop in
the 0 state. This corresponds to C0=0. The output at this time is
ignored.
Serial addition – Inputs (A0, B0), (A1, B1)…..,(A31, B31 ) are
applied as successive two bit vector while sum bits S0,
S1…..,S31 appear at the output. Then, a 00 input is applied to
force the final carry bit at the output as S32 while initializing the
flip-flop to 0 for the next addition.

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Example illustration
Test generation by time-frame expansion method
Consider the s-a-0 fault shown in serial adder Figure. To apply the combinational ATPG procedures we can thus
We assume that the state of the flip-flop is unknown. “unroll” the sequential circuit into a larger combinational
So we set Cn=X and apply the D-Algorithm procedure to the circuit. This unrolling is called “time frame expansion.” The
combinational logic. following example illustrates test generation.
The fault is activated by An= Bn=1 but cannot be propagated to
the output Sn which assumes the unknown value.
We can easily see that we should set Cn to 1 to propagate a D’ to
Sn. We should, therefore, precede this vector by one or more
initialization vectors to set the circuit in the required state.
Alternatively Cn=0 could also have , propagated the fault effect
to Sn though Cn=X will not work.

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For generating a two-vector test we use the expanded circuit model of we refer to the right-most block as time-frame 0. This contains the
primary output where the fault is actually detected.
Figure shown in previous slide.
The left-most block (time frame –1 in this case) has its state inputs in
Here, the combinational logic is repeated twice. the unknown (X) state.
The right block (time-frame 0) receives its state input from the left In general, they can be in any other given known state. The fault is
block (time-frame –1) in the same way as the carry signal was present in all frames. So, we must generate a combinational test that
routed in the combinational adder. will detect the multiple fault.
In Figure of slide 19, this test consists of four input bits all of which
In fact, this circuit performs the same function as that of serial adder are 1. The sequential circuit test is an initialization vector 11
figure. However, it takes only half the number of clock cycles followed by another 11 vector that produces a D at the output.
(though the clock period may have to be doubled) since two inputs Notice that the fault is activated in both time-frames, although that is
are applied simultaneously. Similarly, this test generation model of not always necessary.
the circuit can be expanded to any desired length. As we shall later For example, another test 00 followed by 11 (had we used the
see, the maximum length of this expansion has a limit. alternative choice of Cn=0 activates the fault only in time-frame 0.

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Use of Nine-Valued Logic Nine Valued Logic Example

A signal can assume different values in the fault-free and Figure Shows a circuit with two flip-flops, FF1 and FF2.
faulty circuits. Initially, the flip-flop states are unknown.
It is, therefore, convenient to denote both values as a FF2 is initialized after any input at A.
composite state. FF1 is initialized to 0 any time the A=0 input occurs and remains
In this system, a signal can assume any combination of the in that state thereafter. After the initialization of FF1, B tracks
three values (0,1,X) in the two circuits. A with one clock delay. We consider the s-a-1 fault on input A.
Thus a differing signal may be 0 in the fault-free circuit and In the faulty circuit the output B will be a constant 1 and the
X in the faulty circuit. We will designate it as 0/X . fault is thus detectable.
The following examples illustrate the advantage of the nine-
valued system. Consider a Test circuit.

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Test generation with five Nine-Valued Logic (Muth) 0, 1,
valued logic 0,1, D, D, X 1/0, 0/1, 1/X, 0/X, X/0, X/1, X

Figure (b) is a two time-frame construction of the test generation process with the five-
Figure 8.5(c) repeats the process with the nine-value system and finds that an
valued logic, showing that the fault cannot be detected. This is because the five-valued D-
input A=0 after the application of one clock detects the fault at B as 0/1. Most
calculus assumes that if the fault-free signal is in a known state then the faulty signal can
differ from it but should also be in a known state. In this example, we notice that the fault implementations of sequential circuit test generators use the nine-valued
does not allow initialization of FF1 and produces signal state 0/X, which is regarded as X in system.
the five-valued system. https://www.youtube.com/watch?v=DvzHnGjhO2E
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Implementation of Time-Frame Expansion Methods Implementation of Time-Frame Expansion Methods

Commonly used algorithms for sequential circuit test generation are If the test sequence for a single s-a-f contains n vectors:
backward state justification procedures.
Replicate combinational logic block n times Place fault in each
The construction of a test sequence for a given target fault begins with
the last vector, which detects the fault at a PO. block .
Accomplished in time-frame 0 (called the fault detection time-frame) Generate a test for the multiple stuck-at fault using
by input vector v0 and state vector s0. combinational ATPG with 9-valued logic.
The vector v0 is binary-valued and s0 is a nine-valued vector.
These are determined by a combinational ATPG algorithm and the
state vector s0 is justified in time-frame–1 by input v-1 and state s-1,
again by the combinational ATPG algorithm justification time-
frames.
This process continues until some time-frame–k such that S-k matches
a given initial state.

Test generation by backward state justification.

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Implementation of Time-Frames Expansion Methods Implementation of Time-Frames Expansion Methods

The initial state is determined in one of three ways, depending 3. Start with a known initial state.
upon specific implementation of the algorithm:
✓ Few circuits are designed to “power-up” in a known
1. Start with uninitialized state:
state.
✓ The initial state s-k is set to all Xs.
✓ Assumed that both fault-free and faulty circuits are in some ✓ It is not possible to simulate the asynchronous or
unknown states. analog power-up initialization circuitry by a logic or
2. Start with the final state of the previous tests. fault simulator.
✓ This is the case where some vectors are available that could ✓ Assume that both fault-free and faulty circuits start
not detect the target fault.
✓ The fault simulator starts with both fault-free and faulty
with a known binary-state.
circuits in unknown states. ✓ The vectors so produced are valid tests as long as the
✓ The new test sequence is concatenated to the previous fault does not interfere with the initialization circuitry
vector sequence.

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Implementation of ATPG Complexity of Sequential ATPG

• Select a PO for fault detection based on drivability analysis. Synchronous circuit: All flip-flops controlled by clocks; PI and
• Place a logic value, 1/0 or 0/1, depending on fault type and PO synchronized with clock:
number of inversions. Cycle-free circuit– No feedback among flip-flops: Test
• Justify the output value from PIs, considering all necessary generation for a fault needs no more than dseq + 1 time
paths and adding backward time-frames. frames, where dseq is the sequential depth.
• If justification is impossible, then use drivability to select • Cyclic circuit– Contains feedback among flip-flops: Need 9Nff
another PO and repeat justification. time-frames, where Nff is the number of flip-flops. •
• If the procedure fails for all reachable POs, then the fault is Asynchronous circuit– Higher complexity.
untestable.
• If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can
be justified, the fault is potentially detectable
max = Number of distinct vectors with 9-valued elements = 9Nff

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Cycle-Free Circuits

This classification is based on the connectivity structure of the dseq of the circuit is the maximum number of flip-flops on any
circuit. path between PI and PO.
The state of a flip-flop Fi is considered dependent on another flip- • Test sequence length for a fault is bounded by dseq + 1.
flop Fj if there exists a combinational path from Fj to Fi.
A test for a non-flip-flop fault in a cycle-free circuit can always
Dependence can be expressed by a directed graph, usually called
the s-graph. be found with at most dseq+1 time-frames, unless the fault is
untestable.
A cycle-free circuit is also called a feedback-free or pipeline
circuit.
Given a cycle-free structure, the fault-free circuit and the faulty
circuit with a non-flip-flop fault are always initializable.
Characterized by absence of cycles among flip-flops and a
sequential depth, dseq.

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Cycle-Free Circuit and s-graph Cyclic Circuits: Example

A circuit whose s-graph contains cycles is called cyclic.

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Modulo-3 Counter Adding Initializing Hardware

Cyclic structure– Sequential depth is undefined.

• Circuit is not initializable.
• No tests can be generated for any stuck-at fault.
• Expanding the circuit to 9Nff = 81, or fewer, time-frames
ATPG program calls any given target fault untestable.
• Circuit can only be functionally tested by multiple
observations.

• Functional tests, when simulated, give no fault coverage

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Clock Faults and Multiple-Clock Circuits Clock Faults and Multiple-Clock Circuits
so far has focused on single-clock circuits. A fault in the clock line disturbs the synchronization and in some
Assumption: ways makes the faulty circuit asynchronous.
one input vector is applied per clock cycle.
• Approach provides simplicity to test generation. • A synchronous method for modeling flip-flops with explicit
• However, there is a loss of generality: clock and other signals that may be either synchronous or
First, faults on the clock line are not modeled and hence no tests asynchronous.
were obtained for them. • These models are frequently used for simulation and test
Second, many circuits that contain multiple clocks cannot be handled
as such. generation of sequential circuits and allow faults to be
Third, some memory elements in certain circuits may not be modeled for flip-flop inputs.
controlled by the clock signal. • These do not allow modeling of faults inside flip-flops
In a synchronous circuit, all signals are synchronized with respect to
the clock signal. The clock signal provides the time reference.

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Clock Faults and Multiple-Clock Circuits

An explicit clock model of a flip-flop is shown in Figure. Figure shows a positive edge-triggered flip-flop.
• Ideal flip-flop is the same flip-flop we have been using for the Here, only when a rising edge occurs at CLK, D is propagated to
implicit single-clock case. Q. For all other states of CLK, the output Q retains its state.
• Logic in the shaded region is used for modeling the function of When explicit clock models of flip-flops are used,
the flip-flop. synchronous, and asynchronous clear and preset signals
• Faults inside this logic are usually not modeled. can be modeled.
• Flip-flop is shown with an asynchronous clear (CLR) signal

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 Asynchronous Circuits

Any number of clocks can be present in a circuit. A digital circuit is defined as combinational if its steady-state output is
• Clocks can even be gated by other signals or clock inputs of flip-flops can be completely determined by the present inputs.
fed by external or internal combinational signals. Thus, a combinational circuit does not store any data for the future time.
In actual implementation, these circuits contain logic gates without feedback signals.
• If the operation of the flip-flop is accurately modeled, then the test generator
will correctly deal with faults on clock, clear, and preset signals. Figure A sequential circuit, on the other hand, has combinational feedback which can store
signal states.
gives examples of different types of circuits.
Its output, therefore, depends on both primary inputs and internal states. The internal
states, in turn, may depend upon previous primary inputs.

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A General Asynchronous Circuit

The operation is termed asynchronous if: To isolate the combinational logic, split the asynchronous logic into
two parts:
i. Signals can change at any time. i. Feedback-free combinational logic
ii. Some signals may depend on the past inputs. ii. A set of delay elements synchronized with a fast model clock,
FMCK .
iii. Steady state signal values may depend on circuit FMCK runs much faster than the system clock CK.
delays. Its purpose is to repeatedly evaluate the combinational logic and
stabilize asynchronous signals before CK clocks the flip-flops, applies
new PIs, or observes POs.
A set of signals, called the feedback set, is found such that if the
corresponding interconnects are cut then the circuit will have no
feedback.
The minimum number of signals that must be cut is known as the
feedback index.

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Test Generation Model for Asynchronous Circuits Test Generation Model for Asynchronous Circuits
All combinational gates are assumed to have zero delay, these
delay elements hold the signal until all combinational signals
have been evaluated.
In Figure previous(slide) these delays are taken out in a separate
block (shown in ornage)
Thus, we have created a two-clock model for test generation. The
normal system clock CK controls all synchronous memory
elements (flip-flops.)
The modeling clock FMCK controls the asynchronous delays.
The FMCK clock is necessary because we have modeled the
logic with zero delays. A time-frame expansion type of test
generator deals with this circuit in two phases.
• Delays are taken out in a separate block (shown in orange).

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1. System Clock (CK) Phase Time-Frame Expansion

The operation of the circuit is synchronous with respect to clock

(CK).
Thus One input vector is generated for each period of CK.
The primary output is observed only once in the period.
In Figure shown next, the blocks C are time-frames of the
combinational logic and unshaded blocks correspond to the
CK-phases.
• The inputs to this block are the input vector, previous flip flop
states, or PPIs, and the states of the feedback delays.
• It produces a PO, and the next states of flip-flops (PPOs.)

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Fast Modeling Clock (FMCK) Phase

Two-phase Time-frame Expansion for Asynchronous Circuits

Following the system clock phase, which provides new inputs to

the combinational logic, a series of “fast” time frames exercise
the logic until signals become stable.
A small fixed number of time-frames is used (three).
If some signal does not become stable, then an oscillation can be
assumed and that signal is set to the unknown state.
During this phase, the PIs and the clocked flip-flop states are
held without change, and no PO is examined for fault detection

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Asynchronous Circuits
Sequential Circuit ATPG Simulation-Based Methods
✓ Asynchronous circuits continue to be difficult to test. Difficulties with time-frame method:
✓ Tools and techniques are only adequate for small circuits. ✓ Long initialization sequence
✓ The situation often encountered involves large synchronous circuits ✓ Difficult to guarantee initialization with three-valued logic
with a small amount of asynchronous circuitry embedded in the
combinational logic. ✓ Circuit modeling limitations
✓ Tests for faults in the clock circuitry require asynchronous ✓ Timing problems – tests can cause races/hazards
techniques. ✓ High complexity
✓ The difficulty of finding good tests for asynchronous circuits arises ✓ Inadequacy for asynchronous circuits
due to the inadequate treatment of delays.
Advantages of simulation-based methods:
✓ Analysis of races and hazards can improve the tests, but requires
additional computation. ❑ Advanced fault simulation technology
✓ Logic simulators are more advanced than test generators, when it ❑ Accurate simulation model exists for verification
comes to handling of delays. ❑ Variety of tests – functional, heuristic, random

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 Delay Test Delay Test Definition

◼ Delay test definition ◼ A circuit that passes delay test must produce correct outputs
◼ Circuit delays and event propagation when inputs are applied and outputs observed with specified
timing.
◼ Path-delay tests
◼ For a combinational or synchronous sequential circuit, delay
▪ Non-robust test
test verifies the limits of delay in combinational logic.
▪ Robust test
◼ Delay test problem for asynchronous circuits is complex and
◼ Path-delay fault and other fault models not well understood
◼ Transition Faults
◼ Summary

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Delay Fault detection Delay Test Problem

Two categories ◼ Figure shows a schematic of a digital system.

1. Global delay Fault: affect large area of the circuits. Can be ◼ Some inputs and outputs can be state variables connected to
detected by on chip process monitor flip-flops (FF) (not shown) and others are primary inputs (PI)
2. Local delay fault: affect small area of the circuit, can be and primary outputs (PO).
detected by delay testing. ◼ All input changes are synchronized with a clock signal and all
Delay fault needs two test patters as opposed to one pattern test outputs are expected to attain their final steady state values
for stuck at faults. within one clock period after the inputs change.
A two pattern test consists of a pair of test pattern(test vectors) ◼ For a correct operation the delay of the combinational logic
v1: initializes circuit test .v2:launch transition, propagate fault should not exceed the clock period.
effect to output.
Control the time T between v1 and v2 carefully.

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Digital Circuit Timing

Input Output Transient
Signal region ◼ Delay tests consist of vector-pairs.
Observation
changes instant ◼ All input transitions occur at the same time, the duration of the
transient region at the input is zero.
◼ Right edge of the output transition region (grey shaded area) is
determined by the last transition, or delay of the longest
Inputs

Comb. combinational path activated by the current input vector-pair.

logic ▪ Longest delay combinational path of the circuit is critical path.
◼ Manufactured circuit to function correctly, output transition region
for any input vector-pair must not expand beyond the clock period.
▪ Otherwise, the circuit is said to have a delay fault.
Outputs

Synchronized
With clock ▪ A delay fault means that the delay of one or more paths (not
necessarily the critical path) exceeds the clock period.
time
Clock period
9
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Circuit Delays Event Propagation Delays
• Single lumped inertial delay modeled for each gate
◼ Switching or inertial delay is the interval between input change and • PI transitions assumed to occur without time skew
output change of a gate: Path P1
▪ Depends on input capacitance, device (transistor) characteristics
and output capacitance of gate. 1 3
0 1
▪ Also depends on input rise or fall times and states of other inputs
▪ Approximation: fixed rise and fall delays (or min-max delay 2 4 6
range, or single fixed delay) for gate output.
P2 1

◼ Propagation or interconnect delay is the time a transition takes to

travel between gates: 2 3
0
▪ Depends on transmission line effects (distributed R, L, P3
C parameters, length and loading) of routing paths.
0 2 5
▪ Approximation: modeled as lumped delays for gate inputs.

12
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Propagation of Transitions
Single faulty path and Multiple faulty paths
◼ Examine the three activated paths: ◼ Consider two cases:
1. Path P1: A – H – K
◼ Single faulty path:
2. Path P2: B – E – Q – H – K
▪ Examine the output at 7 units of time.
3. Path P3: B – E – G – J – K
▪ As long as the delay of path P3 is 6 units or less, the output will have
◼ Input and output signals (irrespective of whether or not they are risen to logic 1 value irrespective of delay of path P1 or P2.
latched) are synchronized with a clock of period T.
▪ The delay faults of P1 and P2 will not be detected by this input
◼ Delays have been derived from the analysis of the design data vector pair.
(device parameters, routing capacitances, etc.), the critical path has ▪ If the delay of path P3 exceeds 7 units, due to some manufacturing
a delay of 6 units in the fault-free circuit. defect, then the last edge in the output will be shifted to the right and
◼ Path P3 is one of the two critical paths. we will observe a 0 instead of 1.
◼ If T = 7, any path will be faulty if its delay exceeds 7 units. ▪ Delay fault of path P3 is detectable by this vector-pair

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◼ Multiple faulty paths: Delay Test

▪ Suppose all three paths have more than 7 units of delay.
▪ Entire waveform at the output will be translated to the right by ◼ Delay test definition
more than 7 units and we will observe a failure. ◼ Circuit delays and event propagation
▪ If P1 is not faulty but P2 and P3 are faulty, then output will rise
at 2 units and will remain high beyond 7 units.
◼Path-delay tests
▪ It may fall depending on the relative delays of P2 and P3. ◼Non-robust test
▪ Observing at 7 units, there is no failure, in this case the fault of ▪ Robust test
P2 interferes with the detection of the fault of P3. ◼ Path-delay fault and other fault models
▪ This is because the present vector-pair is a “non-robust” test for ◼ Transition Faults
the delay fault of P3. ◼ Summary

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Path-Delay Test Non-robust Path-delay Test

◼ Important fault model used in delay testing. ◼ A test that guarantees to detect a path-delay fault, when no
◼ The delay defect in the circuit is assumed to cause cumulative other path-delay fault is present.
delay of a combinational path to exceed some specified duration. ◼ A path-delay fault for which a non-robust test exists is called
◼ The combinational path begins at a primary input or a clocked flip-
a singly-testable path-delay fault.
flop, contains a connected chain of gates, and ends at a primary
output or a clocked flip-flop. ◼ A non-robust path delay test applies a transition (two-
◼ The specified time duration can be the duration of the clock period vectors) at the input of the path and measures the output
(or phase), or the vector period. value after a specified interval (clock period.)
◼ The propagation delay is the time that a signal event (transition) ◼ For the test to be an effective measure of the path delay, the
takes to traverse the path. “expected or correct” output value must be uniquely
◼ Both switching delays of devices and transport delays of controlled by the transition propagating through the path.
interconnects on the path contribute to propagation delay.

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Path-Delay Test A non-robust test consists of a vector-

pair V1, V2, such that:
◼ Consider the path-delay fault ↓P3shown (bold lines). 1. The change V1→V2 initiates the appropriate transition at the
beginning of the path under test.
◼ Signals B, E, G, J, and K are called the on-path signals.
• For e.g., the vector-pair (V1, V2) = (010, 100) produces a
◼ Signals that are not in the path P3 but feed the gates on the
falling transition at B to test the fault ↓P3.
path are called off-path signals.
2. All off-path input signals for the path under test assume non-
◼ Thus, C and H are off-path signals for P3.
controlling values (0 when the signal feeds into an OR/NOR
gate, and 1, into AND/NAND gate) in the steady-state
following the application of the second vector V2.This condition
is known as static sensitization of a path.

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Path-Delay Test An Example of a Non-robust Test

◼ By definition of non-robust test, only a single path is faulty.

◼ All transitions arriving through other paths ending at the same
destination must arrive prior to completion of the clock period.
◼ At the end of the clock period, all signals other than the on-path
signals of the path under test must be in their steady-state.
◼ The off-path steady-state signals sensitize the entire path under test,
the path destination signal is controlled by the transition
propagating through the path.
◼ If the path delay exceeds the clock period, then the observed value ▪ AND gate has rise and fall delays of one unit each, shown as 1/1.
▪ The rise and fall delays of the inverter are 2/2 units.
at the path destination at the end of the clock period will differ from ▪ A vector-pair (0, 1) is derived to satisfy the conditions of a non-
the steady-state output due to V2, which is the correct expected robust test and is derived without the consideration of the specific
value. gate delays.

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Circuit Outputs

◼ Figure shows a hypothetical (though typical) output ◼ The initial value (0) is the steady-state output of V1 and the
waveform produced by combinational logic when a vector-pair final value is the steady-state output of V2.
(V1, V2) is applied at the input. If this logic is a part of a ◼ Each transition produced by the vector-pair can potentially
clocked sequential circuit, the output value at the end of the propagate through some path and produce a transition at the
clock period T(CK) is of interest. output at a time determined by the delay of that path.
◼ The transitions propagating through paths whose:
• Delays are smaller than T(CK) are shown as “fast transitions”.
• Delays greater than T(CK) are shown as “slow transitions”.
◼ If the delay of a path increases, the corresponding transition
at the output will move to the right.
◼ If the delay reduces, the transition will move to the left.

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Singly-Testable Paths (Non-Robust Test)

◼ When two neighboring transitions form a pulse, the pulse ◼ The delay of a target path is tested if the test
width equals the difference between the delays of the propagates a transition via path to a path destination.
corresponding paths. ◼ Delay test is a combinational vector-pair, V1, V2, that:
◼ If the pulse width is zero or negative (i.e., falling edge arrives ▪Produces a transition at path input.
earlier for a positive pulse), both transitions will disappear. ▪Produces static sensitization--All off-path inputs assume non-
don’t
◼ The position of an output event is determined by the delay of care • controlling states in V2.
the path the event travels through, while the existence of the V1 V2 Off-path inputs
V1 V2
event at the output depends upon the delays of other paths.

Target
path
• Static sensitization guarantees a test when the target path is the only faulty
path, test is, therefore, called non-robust.
• It is a test with minimal restriction. A path with no such test is a false path.
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Delay Test Robust Path-Delay Test

◼ Delay test definition ◼ A robust path-delay test guarantees to produce an incorrect

◼ Circuit delays and event propagation value at the destination if the delay of the path under test
exceeds a specified time interval (or clock period),
◼ Path-delay tests irrespective of the delay distribution in the circuit.
▪ Non-robust test ◼ A robust test is a combinational vector-pair, V1, V2, that
satisfies following conditions:

▪ Robust test
◼ Produce real events (different steady-state values for V1 and
V2) on all on-path signals.
◼ All on-path signals must have controlling events arriving via

◼ Path-delay fault and other fault models the target path.

◼ Transition Faults ◼ Concept of robust test is general – robust tests for other fault
models can be defined.
◼ Summary

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Robust path delay sensitization for rising and falling Signal Description
transitions
◼ Real events on target path. Controlling events via target • S0 and S1 are steady (without glitch) 0 and 1 values for both
path. vectors V1 and V2.
• U0 and U1 specify the final value as 0 and 1, respectively,
V1 V2 V1 V2
and leave the initial value as don’t care or X.
V1 V2
U1
V1 V2 U0 • F0 and R1 are falling and rising transitions on the on-path
U1 U0 signals.
U1/R1 U0/F0 U0/F0 • For an off-path signal, F0 and R1 are treated same as U0 and
U1/R1
U1, respectively.
S1
V1 V2 V1 V2 • In addition, XX is used to denote both vectors in the don’t
S0
S1
care state.
S0
U0/F0 U0/F0 U1/R1 • The value set (S0, U0, S1, U1, XX) is a five-valued algebra.
U1/R1

28
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A Five-Valued Algebra for Path-delay

Tests Test Generation for Combinational Circuits
◼ Signal States: S0, U0 (F0), S1, U1 (R1), XX. Generation of a test for a path-delay fault
◼ On-path signals: F0 and R1. requires placing the appropriate transition at
◼ Off-path signals: F0=U0 and R1=U1
the origin of the path and justifying the
required off-path inputs of all gates on the
path.
This is easily accomplished using the five-valued
algebra.

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Robust test generation. Robust Test Generation

Test for ↓P3 – falling transition through path P3: Steps A through E
E. Set input of AND gate to
S0 to justify S0 at output
XX S0 S0
U0 D. Change off-path input
C. F0 interpreted as U0;
propagates through U0 to S0 to Propagate R1
AND gate through OR gate
Consider the path-delay fault ↓P3 in as in figure. A. Place F0 at R1
1. Place a transition at the path origin, B = F0. path origin
Path P3
2. Propagate value F0 to line E, , C = U0 =>E = F0. F0
3. G = F0 =>J = R1.
4. F0 is interpreted as U0 for off-path logic, Q = U0.
XX F0 R1
5. Propagate value R1 from J to K, set H = S0 => K = R1.
6. Justify H = S0,set A = S0. U0 Robust Test:
7. Test is A = S0, B = F0, C = U0; or V1 = 01X, V2 = 000. B. Propagate F0 through OR gate; S0, F0, U0
also propagates as R1 through
NOT gate
10
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Non-robust test generation Non-Robust Test Generation

Let us try to generate a robust test for path-delay fault ↑P2 in Figure . For a non-robust test we change S0 and S1 to U0 and U1,
We proceed as follows: respectively (static sensitization.) Now the Step 5 requirement
becomes J = U0, which is consistent with Step 3. The non-
robust test is A = U1, B = R1, C = U0 (changed from S0); or
V1 = X0X, V2 = 110.

1. Place a transition at path origin, B = R1.

2. Propagate R1 to E, set C = S0.
3. R1 is interpreted as U1 for off-path logic, G = U1 => J = U0.
4. Q = R1, Propagate R1 to H, set A = U1.
5. H = R1, Propagate R1 to K, set J = S0 =>conflict since J = U0 in
step 3.
6. Since no step has any alternatives, aBITS
robust test is not possible.
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Non-Robust Test Generation Untestable path delay fault

Fault ↑P2 – rising transition through path P2 has no robust test.
C. Set input of AND gate to ◼ Consider the path-delay fault ↓P2 in Figure.
propagate R1 to output D. R1 non-robustly propagates ◼ A falling transition (F0) is placed at B and is easily
XX U1 through OR gate since off-
R1 path input is not S0
propagated to H by setting appropriate values on A and C.
R1 ◼ A forward implication sets the off-path input of the output
OR gate to U1 (i.e., controlling value in V2.)
Path P2 U1
A. Place R1 at ◼ This path-delay fault has no test.
path origin
R1
R1 U1 U0 Non-robust test requires
XX Static sensitization:
S0=U0, S1=U1
U0
B. Propagate R1 through OR gate;
interpreted as U1 on off-path signal; Non-robust test:
propagates as U0 through NOT gate U1, R1, U0

11
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Path-Delay Faults Path-Delay Faults

◼ A path for which both (rising and falling) path-delay faults (PDFs) ◼ Two PDFs (rising & falling transitions) for each physical path.
are singly (non-robustly) testable is called a testable path.
◼ Total number of paths is an exponential function of gates.
◼ A path having one singly testable PDF and one singly untestable
PDF is called a partially testable path. ◼ Critical paths, identified by STA, must be tested.
◼ When no non-robust test exists for both PDFs of a path, that path is ◼ Three types of PDFs:
called a singly-untestable path. ▪ Singly-testable – has a non-robust or robust test.
◼ Such a path can be eliminated by circuit transformations that ▪ Multiply-testable – a set of singly untestable faults that has a
preserve the logic function. non- robust or robust test.
◼ A combinational circuit may have paths whose delays cannot ▪ Untestable– PDF that is neither singly nor multiply testable.
affect the time of signal change at the output, these paths are called
false paths. ◼ A singly-testable PDF has at least one single-input
◼ The paths of singly-untestable PDFs are not always false paths. change (SIC) non-robust test.

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Transition Faults Transition Faults
◼ A transition fault on a line makes signal change on that line slow. ◼ Tests for transition faults can detect localized (spot) delay defects of
◼ The two possible faults are slow-to-rise and slow-to-fall types. large (gross) delay amounts.
◼ For detecting a slow-to-rise fault on a line, we take a test for a stuck-
◼ Because of sensitization of short paths these tests may fail to detect
at-0 fault on that line.
distributed defects, where small delay increases in a large number of
◼ This test will set the line to 1 in the fault-free circuit and propagate
gates cause a long path to fail.
the state of the line to a primary output.
◼ The advantages of the transition fault model are:
◼ Vector V2 and precede it with any vector V1 that sets the line to 0.
▪ Number of faults has an upper bound of twice the number of lines
◼ Vector-pair (V1, V2) is a test for the slow-to-rise transition fault on
the line. ▪ Tests are easy to generate
▪ S-a-f test generator can be modified to produce tests for transition faults
◼ V1 sets the line to 0 and V2 sets it to 1.
▪ Circuits that either have, or are modified to have, a high stuck-at fault
◼ V2 also creates an observation path to a primary output.
◼ If the line is slow to rise then that effect will be observed as a 0 at coverage also have high transition fault testability
the output instead of the expected value of 1. ◼ Transition fault tests have been used in the industry.

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Delay Test Methodologies Practical Considerations in Delay Testing

◼ Practical application of delay tests depends on the type of ◼ Timing correctness of VLSI circuits is as important as their
circuit under test and the DFT hardware used. logical correctness.
◼ The design of a VLSI chip is verified via timing simulation and
◼ Different test methodologies are: timing analysis.
1. Slow-Clock Combinational Test ◼ A careful timing design increases the manufacturing yield but
2. Enhanced-Scan Test cannot guarantee that every chip will function correctly.
3. Normal-Scan Sequential Test ◼ Tests developed for detecting stuck-at faults, when applied at a
slower than the rated-clock frequency, uncover many manufacturing
4. Variable-Clock Non-Scan Sequential Test defects.
5. Rated-Clock Non-Scan Sequential Test ◼ Results of timing analysis are used to improve the design and test:
1. Timing simulation
2. Critical path tests
3. Layout optimization

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Digital DFT and Scan Design

Timing simulation:
◼ Ad-Hoc DFT Methods
▪ Critical paths are identified by static timing analysis tool.
▪ Timing or circuit-level simulation using designer-generated ◼ Scan Design
functional vectors verifies the design. ▪ Scan Design Rules
2. Critical path tests:
• Critical path of a circuit is the longest delay combinational path between clocked
▪ Tests for Scan Circuits
flip-flops.
▪ Multiple Scan Registers
• Critical path delay determines the clock period.
• Tests of a chip normally include test vectors that propagate ▪ Overheads of Scan Design
signal transitions through critical paths.
3. Layout optimization: ▪ Design Automation
▪ Critical path data are used in placement and routing.
▪ Physical Design and Timing Verification of Scan
▪ Delay parameter extraction, timing simulation and layout
are repeated for iterative improvement. ◼ Partial-Scan Design
◼ Testing: Some form of at-speed test is necessary.

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Introduction

◼ A fault is testable if there exists a well-specified procedure to ◼ For a VLSI chip to be manufactured, we must have a
expose it, which can be implemented with a reasonable cost verified design and a set of tests.
using current technologies. ◼ Following questions characterize testing of complex
◼ Design for testability (DFT) refers to those design techniques systems:
that make test generation and test application cost-effective. ▪ Can tests that detect all faults be assured?
◼ The term DFT refers to a class of design methodologies which ▪ Can test development time be kept low enough to
put constraints on the design process to make test generation be economical?
and diagnosis easier. ▪ Can test execution time be kept low enough to be economical?
◼ No DFT approach is free from: ◼ DFT refers to those design practices that allow us to
▪ Manpower and tool costs answer the above questions in the affirmative.
▪ Area overhead and performance penalty ◼ No single DFT technique is effective for all kinds of circuits.

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Ad-Hoc DFT Methods Ad-Hoc DFT Methods

◼ Collections of ideas aimed at reducing the combinational explosion ◼ Good design practices learnt through experience are used as
guidelines:
of testing. ▪ Avoid asynchronous (unclocked) feedback
◼ Represent a bag of tricks developed over the years by designers to ▪ Make flip-flops initializable
avoid the overhead of a systematic approach to testing. ▪ Avoid gates with a large number of fan-in signals
▪ Provide test control for difficult-to-control signals
◼ Goal is to increase controllability, observability and/or
predictability. ◼ Design reviews conducted by experts or design auditing tools,
◼ Objective: Adherence to design guidelines and testability design reviews are:
▪ Manual analysis
improvement techniques.
▪ Conducted by experts
◼ Frequently multiplexers can be used to provide alternative
▪ Programmed analysis
signal paths during testing. ▪ Using design auditing tool
◼ A complete scan-based testing methodology is recommended for ▪ Programmed enforcement
all digital circuits. ▪ Must use certain design practices and cell types.

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Avoid asynchronous(un-clocked)feedback: Provide test control for difficult-to-control signals. Signals

A feedback in the combinational logic can give rise to oscillation such as those produced by long counters require many
for certain inputs. This makes the circuit difficult to verify and clock cycles to control and hence increase the length of
impossible to generate tests for by automatic programs. This is the test sequence. Long test sequences are harder to
because test generation algorithms are only known for acyclic generate.
combinational circuits.
Make flip-flops initializable. This is easily done by supplying
clear or reset signals that are controllable from primary inputs.
Avoid gates with a large number of fan-in signals. Large fan-in
makes the inputs of the gate difficult to observe and makes the
gate output difficult to control.

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 Ad-Hoc DFT Methods Scan Design

Disadvantages: ◼ The main idea in scan design is to obtain control and observability for flip-
◼ Ad-hoc techniques are useful for small designs. flops.
◼ Experts and tools not available. ◼ This is done by adding a test mode to the circuit such that when the circuit
◼ Test generation is often manual with no guarantee of high fault
is in this mode, all flip-flops functionally form one or more shift registers.
coverage. ◼ The inputs and outputs of these shift registers (also known as scan
◼ Design iterations may be necessary. registers) are made into primary inputs and primary outputs.
As the size and complexity of digital systems grew, an alternative form of ◼ Thus, using the test mode, all flip-flops can be set to any desired states by
DFT, known as structured DFT gained popularity. shifting those logic states into the shift register.
In structured DFT, extra logic and signals are added to the circuit so as to ◼ Similarly, the states of flip-flops are observed by shifting the contents of the
allow the test according to some predefined procedure. scan register out.
Apart from the normal functional mode, such a design will have one or ◼ All flip-flops can be set or observed in a time (in terms of clock periods)
more test modes. Commonly used structured methods are scan and built-in that equals the number of flip-flops in the longest scan register
self-test

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Adding Scan Structure Scan Path

◼ Creating a scan path consists of placing a multiplexer just ahead of

PI PO each flip-flop.
◼ One input to the 2:1 multiplexer (MUX) is driven by normal
Combinational SFF SCANOUT operational data while the other input is driven by the output of
another flip-flop.
logic
SFF ◼ Serial input of MUX is connected to a PI.
◼ One of the flip-flop outputs is connected to a PO pin.
SFF ◼ MUX control line is used as mode control:
▪ It can permit parallel load for normal operation or it can select serial
shift in order to enter scan mode.
▪ When scan mode is selected there is complete serial shift path from an
input pin to an output pin.
TC or TCK Not shown: ◼ Scan can be full-scan or partial-scan.
SCANIN CK or MCK/SCK feed all SFFs

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Scan Path Scan Design

◼ Circuit to have scan capability, designer uses only D flip-flops (DFF)

with one or more clock signals, all of which are controlled from
primary inputs.
◼ After circuit is functionally verified, DFFs are replaced by
scan flip-flops (SFF).
◼ A multiplexer and two new signals, scan-data SD and test control
TC, are added to the DFF.
◼ The original data input D is stored in the flip-flop when TC is
1 and SD is stored when TC is 0.
◼ In synchronous circuit, all feedback paths contain clocked flip-flops.
◼ Generation of sequences makes ATPG difficult.

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 Scan Flip-Flop (SFF) Level-Sensitive Scan Design
D Master latch Slave latch
TC
◼ Another popular design style is Level-sensitive scan design
Q (LSSD), uses two non-overlapping clock signals.
Logic
overhead ◼ Figure shows a scan flip-flop with two function clocks, MCK
and SCK.
MUX
SD Q ◼ When MCK is high, data D is latched in the master latch.
◼ When SCK is high, the state of master latch is copied in the
CK slave latch.
D flip-flop
◼ For a proper operation of a general sequential circuit, MCK
and SCK are never turned high, simultaneously.
CK Master open Slave open ◼ In the scan mode, MCK is held low and scan data SD is
t
latched in by using clocks TCK and SCK as master and slave
Scan mode, SD selected
clocks, respectively
TC Normal mode, D selected
t

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Level-Sensitive Scan Design Scan Design Rules

A circuit is designed to meet its functional requirements. After

the functional correctness of the design is verified, it is modified
to include the scan function.
In order to be able to make it scan-testable, the designer must
adhere to certain rules during the functional design. In general,
these rules depend upon the specific design environment, which
may dictate choices such as single versus multiple clocks, etc.
The following four rules, however, are found to be useful:
1. Use only clocked D-type flip-flop for all state variables.
2. At least one primary input pin must be available for test.
3. All flip-flop clocks must be controlled from primary inputs.
4. Clocks must not feed data inputs to flip-flop.
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Design Rules: Rule-2

Rule-1: ◼ If extra pins are not available, then any normal primary input
Only D-type master-slave flip-flops should be used. can be used as scan-in and any PO pin can be multiplexed as
This rule prohibits the use of other types of flip-flops (JK, scan-out
toggle, etc.) or other forms of asynchronous logic ◼ In Figure TC (test control) is the only pin added.
(unclocked RS latches, combinational feedback ◼ Primary input PI2 serves as SCAN IN and primary output
elements.) pin PO2 also outputs SCANOUT.
Rule-2:
At least one primary input pin must be available for test
. In general, flip-flops can be connected as multiple scan
registers each of which will require a scan-in and a
scan-out terminal.

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Rule-3 R-3 Correcting a Rule Violation

All flip-flop clocks must be controllable from primary inputs: ◼ All clocks must be controlled from Pis.
This rule is necessary for flip-flops to function as a scan register.
Some violations of this rule, if they exist, can be removed by a Comb.
logic D1 Q
simple work-around.
FF Comb.
Figure shows an example. Here the clock signal (CK) is gated by D2 logic
a combinational signal, D2. Thus, when D2 = 0, the clock is
inhibited and the flip-flop FF retains its state Q.
When D2 = 1, the clock CK stores D1 as the new state. In Figure
(b), the clock is applied directly to FF and a multiplexer is Comb.
logic
added to the combinational logic to regenerate data for FF.
Q
The two circuits are functionally identical and the modified circuit D1
D2 FF Comb.
satisfies the rule R-3. logic
CK

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Tests for Scan Circuits

Rule:4: ◼ Testing of scan circuits is done in two phases. The first phase tests
the scan register by a shift test. The circuit is set in scan mode by
Clocks must not feed data inputs of flip-flops: setting TC = 0. All flip-flops now form a shift register between
A violation of this rule can potentially lead to a race condition in SCANIN and SCANOUT. Scan register must be tested prior to
the normal mode. application of scan test sequences.
◼ A shift sequence 00110011 . . . of length nsff + 4 in scan mode
Thus the value captured in the flip-flop cannot be guaranteed to (TC=0) produces 0->0, 0->1, 1->1 & 1->0 transitions in all flip-
be the state of the signal produced by the combinational logic. flops and observes the result at SCANOUT output.
In scan design, flip-flops play a dual role. They capture ◼ Total scan test length: nsff + 4 + (nsff + 1) ncomb + nsff
combinational data in the normal mode and then carry the data =(ncomb + 2) nsff + ncomb + 4 clock periods.
out for observation in the scan mode. ◼ Example: 2000 scan flip-flops, 500 combinational vectors, total
The test procedure relies on the flip-flop correctly capturing data scan test length ~ 106 clocks.
in the normal mode and hence no race condition is permitted. ◼ Multiple scan registers reduce test length.

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In the second phase of testing, single stuck-at faults in the

combinational logic are targeted.
A combinational ATPG program is used to generate test vectors
assuming that all flip-flop outputs are completely controllable and all
flip-flop inputs are observable.
Figure (a next slide) shows this combinational ATPG scenario.
Three input vectors and the corresponding outputs are shown in the
figure.
Both input vector contains two parts, primary input parts, i1, i2, and
i3 and state variable parts, s1, s2, and s3.
Similarly, the corresponding outputs of the combinational logic
contain two parts, primary outputs, o1, o2, and o3, and next state
outputs, n1.n2 and n3 .
The combinational vectors are converted into scan sequences shown
in Figure (b) before they can be applied to the actual circuit.

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 Multiple Scan Registers
To reduce the time of scan test, sometimes flip-flops are arranged in multiple
scan registers. Each scan register requires separate SCANIN and SCANOUT
pins. If extra pins are not available, added fanouts from normal primary input
pins can provide SCANIN signals to scan chains. This is possible because the
normal primary inputs and SCANIN are never simultaneously used. Similarly,
the SCANOUT signals can be multiplexed with the normal primary output
pins under the control of the test control (TC) signal.
PI/SCANIN PO/
Combinational
M SCANOUT
logic U
SFF X

SFF
SFF

TC

CK

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Multiple Scan Registers Contd.. Overheads of Scan Design

◼ One or more additional I/O are required. The use of scan design has two types of penalties. The scan hardware
increases the chip size (area overhead) and slows the signals down
◼ With a given set of test patterns, test time per pattern is increased (performance overhead.) In the early stages of a design, it is useful
because of the need to shift the pattern serially into the scan path, to estimate the gate overhead.
total test time increases. ▪ Gate overhead = [4 nsff/(ng+10nsff)] x 100%,
where ng = comb. gates; nsff = flip-flops;
◼ A slower clock rate may be required because of the extra delay in ▪ Example: ng = 100k gates, nsff = 2k flip-flops, overhead = 6.7%.
the scan-path flip-flop or latches, resulting in a degradation in ▪ Accurate estimate must consider scan wiring and layout area.
performance. ◼ Performance overhead:
▪ performance penalty can be minimized by employing storage ▪ Multiplexer delay added in combinational path; approximately
cells that have no additional delay in series with data inputs. two gate-delays.
◼ Test generation costs can be significantly reduced. ▪ Flip-flop output loading due to one additional fanout
▪ can also lead to higher fault coverage. approximately 5 to 6%.
◼ Some designs are not easily realizable as scan designs. ▪ Scan design can reduce the clock speed by 5 to 10%.

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Area overhead: Scan design requires a significant amount of routing that can
Figure a shows standard cell and b shows scan layout. First, flip-flop
impact the chip area. The test control signal (TC) is routed to all flip-flops cells (uniformly distributed among cell rows and shown cross-
and the output of each flip-flop is routed to the scan data (SD) input of the hatched) are replaced by corresponding scan flip-flop cells.
next flip-flop in the scan register chain. The impact of scan routing on the These cells are wider due to the added multiplexer.
chip area increase can be reduced by: (a) flip-flop placement on the layout
Next, two types of interconnects are added. A test control (TC) signal
for optimum routing and (b) selecting the flip-flop order in the scan chain. feeds all scan flip-flop cells. As shown in Figure (b) by bold lines,
this takes at most one track in every alternate routing channel.
The second set of interconnects forms a chain between the SCANIN
and SCANOUT pins.
When flip-flops are suitably ordered, as the wires with small arrows
show, this is also accomplished by one track per alternate channel.
Thus, two tracks per alternate channel, or an average of one track per
channel, can accommodate the scan wiring. The track overhead can
go higher if the scan layout is not optimized.

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We will only consider the active area, which is the area of cells We will use the following notation:
and routing. The active area in Figure is a rectangle of linear
dimensions X and Y, which expand to X' and Y', respectively.
The increase in X is due to wider scan cells and that in Y is due
to the extra tracks used for the scan wiring. The cell width is
measured in a normalized unit called a grid.
Similarly, the channel height is measured in the number of tracks.

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Design Automation

The combined height of a cell row and one adjoining routing The full-scan design is considered the best DFT discipline.
channel is T+Tβ/(1-β)= T/(1- β) tracks. It can be completely automated using commercially available
Therefore, the number of routing channels=Y(1-β)/(yT) design tools.
The scan routing on average adds one track per routing channel. Over the years, it has gained wide-spread acceptability in system
Therefore Y’=Y+ry=Y+Y(1-β)/T. design environments. Figure (next slide) shows a typical
Upon substituting scenario of scan design.
DFT practically impacts every aspect of design. First, scan design
audits are applied during the design phase. Audit programs
analyze the topology of the circuit.

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A Flow-chart of Automated Scan Design

Behavior, RTL, and Logic Once the design is completed in the form of a verified netlist,
Rule design and Functional verification
violations design and test activities can proceed in parallel.
Scan design netlist
rule audits Automatic scan implementation consists of two phases.
Gate-level
netlist
First, all flip-flops are replaced by corresponding scan versions,
Combinational Scan hardware which are generally available in standard-cell libraries.
ATPG insertion
If the SFF module is not available in the library, then multiplexers
Combinational Scan
vectors netlist
can be added to all flip-flops in the netlist.
Scan sequence FF/Scan chain order Chip layout: Scan- The second phase in the scan implementation is to connect flip-
and test program chain optimization, flops into shift register chains. Chip layout programs optimally
generation timing verification
place flip-flops to minimize the routing area and delay.
Design and test
data for
Test program manufacturing Mask data

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 Physical Design and Timing Verification of Scan
Independent of the physical design, a combinational circuit netlist Physical design of a scan chain requires timing verification
is generated by removing flip-flops and clocks from the because its integrity is crucial to the application of scan tests.
audited netlist. Several problems should be checked:
Flip-flop output signals appear as pseudo-primary inputs (PPIs) ◼ Small delays in scan path and clock skew can cause race
and flip-flop input signals appear as pseudo-primary outputs condition.
(PPOs) in the combinational circuit. ◼ Large delays in scan path require slower scan clock.
A combinational ATPG program is used to generate test vectors ◼ Dynamic multiplexers can cause momentary shorting of D and
for all single stuck-at faults in this circuit. SD inputs.
Next, the combinational vectors and the flip-flop chain order ◼ Power dissipation during scan: Random signal activity in
information obtained from the layout are used to generate combinational circuit during scancan cause excessive power
scan-in and scan-out sequences. dissipation.

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Partial-Scan Design A Partial-Scan Method

◼ A subset of flip-flops is scanned. ◼ Select a minimal set of flip-flops for scan to eliminate
◼ Objectives: all cycles.
▪ Minimize area overhead and scan sequence length ◼ Alternatively, to keep the overhead low only long cycles may
yet achieve required fault coverage be eliminated.
▪ Exclude selected flip-flops from scan: ◼ In some circuits with a large number of self-loops, all cycles
▪ Improve performance other than self-loops may be eliminated.
▪ Allow limited scan design rule violations ◼ The structure graph (s-graph) of a sequential circuit
▪ Allow automation: clearly shows the difficulty caused by feedback.
▪ In scan flip-flop selection
◼ Each flip-flop is represented by a vertex in the s-graph.
▪ In test generation
▪ Shorter scan sequences

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Partial-Scan Architecture s-graph is a Directed Acyclic Graph (DAG)

PI PO

Combinational
circuit

CK1
FF

FF
CK2 SCANOUT
SFF
TC
SFF

SCANIN

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s-graph is a Directed Acyclic Graph (DAG)
▪ The structure graph (s-graph) of a sequential circuit clearly The DAG of Figure (b) can be levelized.
shows the difficulty caused by feedback. Vertices without any incoming edge are placed in level 1.
▪ Each flip-flop is represented by a vertex in the s-graph. A
directed edge from vertex i to vertex j means that a For any other vertex, the level is one higher than the level of the
combinational path from flip-flop i to flip-flop j exists. highest level vertex that feeds into it.
▪ Figure illustrates the construction of the s graph for a For example, vertex 6 is fed by 1 and 5, of which vertex 5
feedback-free circuit. Shaded regions marked as Cl, C2, C3, belongs to the highest level of 2.
and C4 are combinational logic blocks. Flip-flops FF1 through Thus, vertex 6 has a level 3. The maximum level in the s-graph (3
FF7 are represented by vertices 1 through 7 in Figure (b). in this example) is called the sequential depth.
▪ Primary inputs and primary outputs are not represented in the
s-graph. Since the circuit has no feedback, its s-graph is a
directed acyclic graph

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A sequential circuit with feedback and

its s-graph
▪ Notice that all flip-flops corresponding to level 1 vertices can be
directly controlled by a single vector applied at primary inputs.
▪ The control of a level 2 flip-flop requires that some flip-flops in
level 1 be controlled, and it will therefore require the application of
two vectors at primary inputs.
▪ Thus, a sequence of vectors that controls all flip-flops must be as
long as the sequential depth. In general, as the sequential depth
increases the length of the test sequence to detect a fault increases
proportionately.
▪ Also, a sequential ATPG program takes more time to produce a test
sequence for a target fault. The sequential depth of a purely
combinational circuit is 0.

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A Partial-Scan Method

▪ consider the circuit with added feedback paths from FF5 ◼ Complexity of a circuit with feedback can be reduced by
and FF7. scanning a selected set of flip-flops.
▪ The circuit does not have any combinational feedback ◼ A scan flip-flop is controllable and observable via a test
and hence is a proper synchronous sequential circuit. mode, its output is treated as a primary input and its input is
▪ The corresponding s-graph is shown in Figure (b). treated as a primary output.
▪ This is no longer a DAG as it contains several cycles. ◼ Vertices corresponding to scan flip-flops are deleted from the
Because of cycles, it is not possible to levelize the graph. s-graph.
▪ Hence, we cannot talk about a sequential depth or ◼ If we scan FF5 and FF7, then vertices 5 and 7 will be deleted
bound the length of sequences to control flip-flops. and the s-graph becomes acyclic with a sequential depth of 2.
▪ In general, the test length and ATPG run time for such ◼ Finding the smallest set of vertices is known as the minimum
circuits can be quite large feedback vertex set (MFVS) problem.

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A Partial-Scan Method Summary

◼ Partial-scan is a generalization of scan: ◼ Scan is the most popular DFT technique:

▪ Scan can vary from 0 to 100%. ▪ Rule-based design
▪ Elimination of long cycles can improve testability via sequential
▪ Automated DFT hardware insertion
ATPG. ▪ Combinational ATPG
◼ Advantages:
▪ Elimination of all cycles and self-loops allow
▪ Design automation
combinational ATPG.
▪ High fault coverage; helpful in diagnosis
▪ Partial-scan has lower overheads (area and delay) and
reduced test length. ▪ Hierarchical – scan-testable modules are easily combined into large
scan-testable systems
▪ Partial-scan allows limited violations of scan design rules, e.g., a
▪ Moderate area (~10%) and speed (~5%) overheads
flip-flop on a critical path may not be scanned. ◼ Disadvantages:
◼ Disadvantage: it requires the use of a sequential ATPG ▪ Large test data volume and long test time
▪ A slow speed test
program.

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 BIST Response Compaction

During BIST, it is necessary to reduce the enormous

number of circuit responses to a manageable size that
can be stored on the chip.
For example, consider a circuit with a hardware pattern
generator that computes 5 million test patterns during
testing, and where there are 200 POs.
The total number of responses will be
5,000,000x200=1,000,000,000 bits!
This amount of information cannot be economically stored
on the CUT, so the circuit responses must be
compacted.

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Definitions Definitions

Aliasing: Due to information loss, signatures of good and some Compression schemes, are impractical for BIST response
bad machines match. analysis, because they inadequately reduce huge
Compaction: Drastically reduce number of bits in original circuit volume of data, use only compaction schemes.
response during testing in which some information is lost. Signature analysis: A method of circuit response
Compression: Reduce # bits in original circuit response so that compaction during testing, whereby the entire good
no information lost so the original output sequence can be fully circuit response is compacted into a good machine
regenerated from the compressed sequence. signature. The actual circuit signature is generated
Signature analysis: A statistical property of a circuit, usually a during the testing process on the CUT, and then
number computed for a circuit from its responses during compared with the good machine signature to determine
testing, with the property that faults in the circuit usually cause whether the CUT is faulty
the signature to deviate from that of the good machine

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 Distinguish between compression and compaction.
Circuit response compression is lossless, because the original output sequence can
Transition Count Response Compaction: be completely regenerated from the compressed sequence.
A method of response compaction in which the number of Compaction, however, results in information loss, so regenerating the original
circuit response information is not possible.
transitions from 0 to 1 and 1 to 0 at circuit POs are Compression schemes, at present, are impractical for BIST response analysis,
counted to create a testing signature. because they inadequately reduce the huge volume of data, so we use only
compaction schemes.
Trivial schemes for response compaction are: In mathematical words, compression functions are invertible, but compaction
functions are not.
Parity checking, where we form parity across all circuit
Signature analysis is the process of compacting the circuit responses into a very
responses . small bit length number, representing a statistical circuit property, for
economical on-chip comparison of the behavior of a possibly defective chip
Ones counting, where we count the number of ones in the with a good machine chip.
output responses from the circuit. Also, the signature must preserve as much of the fault information contained in the
circuit output response before compaction as possible, and the circuitry used to
implement the compacter should be small .
All compaction techniques require that the fault-free circuit signature be known

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Example of transition counting response compaction

Some trivial schemes for response compaction are:

1. Parity checking, where we form parity across all circuit responses,
and
2. Ones counting, where we count the number of ones in the output
responses from the circuit.
Aliasing occurs when the compacted response of the bad machine
matches the compacted response of the good machine, and is always a
problem with compaction because information is lost.
In parity checking, aliasing frequently happens. Also, with ones
counting, it is possible to permute the placement of ones in the circuit’s
Karnaugh map, and still obtain a correct ones count, so it is also very
prone to aliasing and also requires significant arithmetic hardware

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The transition count C(R) is the number of times signals in the In order to maximize the test set fault coverage, in
circuit response R change during BIST. transition count testing we must make C(R0) the
Figure shows an example circuit with the fault a stuck-at-1. In transition count of the good machine, as large or as
Figure (a), we see the circuit responses to five test-patterns, small as possible.
where the faulty machine response is shown above the good
machine response. Transition count testing aliases less than ones counting,
because it not only checks for the correct number of
Figure (b) shows the sum of 0->1 and 1-0> transitions, with those
of the faulty machine shown above those of the good machine ones and zeroes in the circuit output response, but also
partially tests for the correct ordering of the ones and
In Figure (b) at PO x1, the good machine has a transition count
of 1, but the faulty machine count is 3. zeroes in the response.
One advantage of transition count compaction is that |C(R)|, the
number of bits to represent C(R), is
bits in R. ri is the circuit output response at time i. Then:

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LFSR for Response Compaction

Frohwerk introduced the LFSR for response compaction by signature The final state of the standard LFSR is not always the polynomial
analysis. remainder of this division, but is related to the true remainder
The signature is any statistical property of the circuit that is used for through a different state assignment.
checking its correct operation.
He used the data compaction method of the cyclic redundancy check The error detection hypothesis is that a faulty data stream
(CRC) code generator, which requires an LFSR hardware device. changes the output data stream, and hence the remainder of
In this method, the circuit output data stream is treated as a descending this polynomial division, which is used as the signature in this
order coefficient polynomial. compaction method.
The output response compacter LFSR performs polynomial division of The LFSR must be initialized to the seed value, and after data
this data stream polynomial by the characteristic polynomial of the
compaction, the signature must be observed and compared
LFSR.
with the known good-machine signature .
The final state of the modular LFSR is the polynomial remainder of this
division. The signature analyzer circuit is easily testable.

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Modular LFSR Response Compaction Example

Figure(previous slide) shows a modular LFSR that has an extra
XOR gate at the input to the flip-flop driving the least
significant bit X0. This XOR gate XORs the circuit output
response stream, “01010001” in this case, into the least
significant bit of the modular LFSR.
Before response compaction occurs, the LFSR flip-flops must be
initialized to all zeroes. Here, “01010001” The figure shows
how eight clock periods are simulated after the LFSR is
initialized to “00000.” is interpreted a

we see that the characteristic polynomial of this modular

LFSR is 1+x+x3+x5

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Signature by LFSR

Figure shows how 8 clock periods are simulated after the LFSR is
initialized to “00000”.
It also shows the long division of reversed data stream
polynomial by reversed charactistics polynomial of LFSR.

The remainder of the division,1+x2+x3 also matches the

remainder left after eight clock periods in the LFSR, because
only X0,X2 and X3 are ones.
Thus, we have agreement between the signature predicted by
polynomial division and the signature produced by logic
simulation.

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Signature by Polynomial Division Multiple-Input Signature Register (MISR)

In the example of PREVIOUS we see that one primary circuit

output required an LFSR for signature analysis with 5 flip-
flops and 3 XOR gates.
However, consider the case where the above circuit has 200
outputs. Then, we would need 200X5 flip-flops and more than
200X3=600 XOR gates. This is a serious hardware overhead.
Solution: MISR compacts all outputs into one LFSR
LFSR is linear – obeys superposition principle.

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Multiple-Input Signature Register

(MISR) Multiple input signature register
If we superimpose all of the responses of the 200 circuit outputs
in the same LFSR for response compaction, then the final
remainder will be the sum (under XOR logic arithmetic) of the
remainders due to all of the circuit outputs.
This is highly advantageous, as it reduces the flip-flop count from
1000 to 200 and the XOR gate count from more than 600 to
approximately 3+200.
The 200 added XOR gates are needed to XOR all of the circuit
outputs into different bits of the LFSR, where there must be
one bit for each circuit PO, called di
This new response compacter is known as a multiple-input
signature register (MISR),

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MISR Matrix Equation MISR Example

Figure shows a modular LFSR converted into a MISR, by XOR-

ing a different circuit primary output into each flip-flop
position.
The resulting signature, since this system is linear, is the XOR-
ing of the three different signatures due to the polynomial
division from each of the three POs.

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Modular MISR Example Multiple Signature Checking

It implements the following equation system: Use two different testing epochs:
1 st with a MISR with one polynomial .
2 nd with MISR with different polynomial
Reduces probability of aliasing.
Unlikely that both polynomials will alias for the same fault. Low
hardware cost:
A few XOR gates for the 2nd MISR polynomial and 2-1 MUX
to select between two feedback polynomials

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Built-in Logic Block Observer Built-in Logic Block Observer

• BILBO Combines functionality of the D flip-flop, a • Characteristic polynomial: 1 + x + … + xn

testing pattern generator, a testing response compacter, and
a scan chain function.
• The scan chain BILBO can be reset to zero by shifting in
an all-zero pattern into the BILBO in serial scan chain mode.
• NAND gates are used in this BILBO in order to accelerate
its speed over implementations with AND and OR gates.

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Modes of Operation of BILBO register BILBO Serial Scan Mode

• B1 B2 = “0 0”
• Dark lines show enabled data paths
Control Inputs Mode of Operation
B1B2
0 0 Serial scan chain

0 1 LFSR pattern generator

1 0 D FF (Normal)

1 1 MISR response compacter

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BILBO LFSR Pattern Generator Mode BILBO in D FF (Normal) Mode

• B1 B2 = “0 1” • B1 B2 = “1 0”

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BILBO in MISR Mode Example BILBO Usage

• B1 B2 = “1 1” • CUTs A and C: BILBO1 is MISR, BILBO2 is LFSR

• CUT B: BILBO1 is LFSR, BILBO2 is MISR

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Test-Per-Clock BIST Systems Test-Per-Clock BIST Systems

• New fault set tested during every clock period. • Figure (a) shows a test-per-clock system.
• The advantage of this BIST system is : Shortest possible • In Figure (b) there are large numbers of PIs, so it is feasible to
pattern length. apply an LFSR to a subset of these inputs.
• 10 million BIST vectors, 200 MHz test / clock • Serially shift the MSB coming out of the LFSR into a shift
• Test Time = 10,000,000 / 200 x 106 = 0.05 s register to provide pattern stimulation for the remaining inputs.
• Shorter fault simulation time than test / scan • The saving in test hardware is extremely minor.
• The shift register portion of the circuit has the same flip-flop
hardware as the LFSR, but it lacks the few XOR gates used to
form a LFSR feedback network.

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Test-Per-Scan BIST Systems Test-Per-Scan BIST Systems

• Each new set of faults that is tested requires one clock to • One problem in test-per-scan systems is that usually a new set
conduct the test and a series of shifts of the scan chain to of circuit input patterns is generated using a pseudo-random or
complete that test and read out all of the test results. exhaustive technique.
• Significantly more time required/test than test/clock. • However, because the input patterns are time shifted and
• Advantage: Judicious combination of scan chains and MISR repeated to the circuit through the scan chain, the patterns
reduces MISR bit width. become correlated.
• Disadvantage: Much longer test pattern set length, causes fault • Reduces the pattern effectiveness for fault detection, so very
simulation problems. frequently it is necessary to provide an input network of XOR
gates to phase shift the inputs and de-correlate them.

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STUMPS (Self-Test Using a MISR

Test Per Scan BIST
and Parallel Shift register)
In this LFSR generates pseudo-random patterns, which are then
PG Scan register PI and PO
disabled fed through full-scan chains (SR1, SR2, ..., SRn) on various chips
Comb. logic during test in the system-under-test.
The scan chains drive the inputs of these chips. The chip outputs
Scan register are collected in another scan chain, which is serially driven by all
BIST
BIST Go/No-go Comb. logic
of the chip outputs.
Control
enable signature The chip output scan chains then drive a MISR.
logic
Scan register The advantage of this system is that if there are collectively 5,000
Comb. logic
chip outputs, but they are sampled by 25 scan chains, each of
length 200, then the output MISR needs to have only 25 bit
RA Scan register positions in it, one for each scan chain, rather than 5,000.

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STUMPS Test-per-scan Testing System

A scan chain for the chip outputs requires only 1 flip-flop and one • SR1 … SRn – 25 full-scan chains, each 200 bits
MUX per output. • 5000 chip outputs, need 25 bit MISR (not 5000 bits)
However, a MISR for the chip outputs requires 1 flip-flop per
output, 1 XOR gate per output, reset hardware for the flip-
flops, and a number of XOR gates for the MISR feedback
network.
Again, because of the recent drastic decrease in hardware cost,
the hardware savings of STUMPS over a MISR may be less
important than they were a decade ago.

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Alternative Test-per-scan Systems Circular Self-Test Path System
In the CSTP configuration, all primary inputs and primary
outputs are reconfigured as external scan cells.
They are connected to the internal scan cells to form a circular
path.
If the entire circular path has n scan cells, then it corresponds to a
MISR with characteristic polynomial f(x) = 1+xn.
During self-test, all primary inputs are connected as a shift
register, whereas all internal scan cells and primary outputs are
reconfigured as a MISR.
The MISR consists of a number of self-test cells connected in
series, where in self-test mode, each self-test cell takes as input
from an XOR gate output of input Yi and its previous scan cell
output Xi−1, as shown in Figure b.

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Full-circular BIST Configuration

One requirement for the CSTP design is that all registers must be
initialized to known states prior to self-test.
After initialization of all registers, the circuit runs for a number of
clock cycles and then the final signature is read out for
analysis.
Because the characteristic polynomial, f(x)= 1+xn, is nonlinear,
the CSTP design can lead to low fault coverage

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Circuit Initialization Circuit Initialization (Continued)

• It is very important in random logic BIST to initialize all flip- • All such uninitializable flip-flops must then be initialized by
flops in the circuit when BIST is used with partial scan. adding master set or reset lines to them.
• Otherwise, X logic values in a 3-valued logic system will be • Another approach is to break all cycles (loops of flip-flops) in
clocked into the MISR. the circuit, and then apply a partial BIST pattern sequence that
synchronizes all flip-flops to a known state.
• In the real hardware, different chips will randomly initialize • Then, the response compacter can be turned on to compact the
their flip-flops to different values. circuit’s response.
• Initialization problems can be discovered by setting all flip- • If the BISTed circuit uses a full-scan chain, then it is important
flops initially to the X state, running the BIST cycle, and to initialize the flip-flops in scan mode before initiating BIST
simulating the system in a 3-valued logic simulator. • The initialization hardware significantly increases the chip
• If the MISR or other response compacter finishes the test area overhead of BIST.
session with bits in the X state, then initialization is not
correct.
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Device Level BIST

• It is necessary to isolate the BIST circuitry and the circuit-under-test One possibility for isolation is to loop back circuit outputs into
from normal system data during testing. circuit inputs .
• Inputs to the CUT can be isolated by multiplexers (known as the A signal from outside the circuit indicates that the circuit should
Input MUX) or by blocking gates. perform a self-test.
• The Input MUX switches input to the CUT from the normal system The test controller sets a series of loop backs on the chip to allow
inputs (port 0) to the BIST pattern generator (port 1.) data to circulate through the VLSI chip and not interfere with
• When blocking gates, such as AND gates, are used, a constant ‘0’ the rest of the system.
would be applied to the second AND gate input, to block the normal
The BIST procedure would exercise each VLSI chip using the
system input arriving from the first AND gate input.
loopback circuit. Then, the boundary scan chain can be used to
• Most importantly, note that neither the Input MUX nor the blocking
test the interconnections between the VLSI chips
gate will be thoroughly tested by the BIST hardware.

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Loop-Back Circuit System Test with Loop-Back

• Loop back outputs into inputs Alternatively, the interconnections can also be tested by sending
data from the test controller circuit through the sub-circuits,
looped I/O, and back to the test controller, as shown in Figure

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Test Point Insertion

• Test points can be used to increase the circuit’s fault coverage Figure below shows an example where one control point and one
to a desired level. Figure shows two typical types of test observation point are inserted to increase the detection
points that can be inserted. probability of a six-input AND-gate.
• A control point can be connected to a primary input, an
existing scan cell output, or a dedicated scan cell output.
• An observation point can be connected to a primary output
through an additional multiplexer, an existing scan cell input,
or a dedicated scan cell input.

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 Summary

By splitting the six-input AND gate into two fewer-input AND • Logic BIST system architecture:
gates and placing a control point and an observation point • Advantages: Higher fault coverage, At-speed test, Less system
between the two fewer input AND gates, we can increase the
test, field test & diagnosis cost
probability of detecting faults in the original six-input AND
gate (eg, output Y stuck-at-0 and any input Xi stuck-at-1), • Disadvantage: Higher hardware cost
thereby making the circuit more RP-testable. • BIST has overheads:
After the test points are inserted, the most difficult fault to detect • Input MUX, pattern generator, response compacter, test
is the bottom input of the four-input AND gate stuck-at-1. In controller, extra circuit delay, DFT to initialize circuit and test
that case, one of inputs X1,X2, and X3 must be 0, the control the test hardware
point must be 0, and all inputs X4X5, and X6 must be 1, • Architectures: BILBO, test / clock, test / scan.
resulting in a detection probability of 7/128=(
7/8×1/2×1/2×1/2×1/2) • LFSR pattern generator and MISR response compacter –
preferred BIST methods

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Summary

• Needs DFT for initialization, loop-back, and test points.

• BIST is gaining acceptance for testability insertion due to:
• Reduced chip area overhead (only 1-3 % chip area
for memory BIST)
• Allows partitioning of testing problem
• Random logic BIST, 13 to 20 % area overheads:
• Experimental method has only 6.5 % overhead

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