Department of Information Science and Engineering

VISVESVARAYA TECHNOLOGICAL UNIVERSITY

Belgaum, Karnataka-590014

DIGITAL DESIGN AND COMPUTER ORGANIZATION

Subject Code: BCS302

(As per Visvesvaraya Technological University Syllabus)

B.E- 3rd Semester

Prepared and Reviewed By

Prof. Meghana Sambare R

Assistant Professor

2024-25
 DIGITAL DESIGN AND COMPUTER
ORGANIZATION
[As per National Education Policy (NEP) scheme - Effective from the academic year 2021-22]

Semester III CIE Marks 50

Course Code BCS302 Exam Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2:0 Total Marks 100
Total Hours of Pedagogy 40 hours Theory + 20 Exam Hours 03
Hours of Practicals

LABORATORY OBJECTIVES

Course Objective:
● To understand the working of simulide simulator.

 To understand the syntax of Verilog HDL and Modelsim simulator.

Teaching-Learning Process (General Instructions)

These are sample Strategies; that teachers can use to accelerate the attainment of the various course outcomes.

1. Chalk and Talk

2. Live Demo with experiments
3. Power point presentation

PROGRAM SPECIFIC OUTCOMES (PSOs)

PSO1: Able to apply knowledge of information management and communication systems to provide secured
solutions for real time engineering applications.
PSO2: Apply best software engineering practices, modern tools and technologies to deliver quality products.
 PROGRAM OUTCOMES (POs)
Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an
engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems
reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering
sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and design system
components or processes that meet the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data, and synthesis of the information to provide
valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and
IT tools including prediction and modeling to complex engineering activities with an understanding of the
limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health,
safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering
practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions in societal
and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse
teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a member and leader in a team, to manage projects
and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent
and life-long learning in the broadest context of technological change.
 Rubrics for assessing student’s performance in Laboratory courses

The internals marks of lab for 2022 scheme is 15 Marks for Continuous Evaluation and 10 Marks for Lab Internals.
Continuous Evaluation for 2022 scheme:

Sl Parameters Mark 5 4 3 0
No
1. Writing Program/Logic 3 The student is The student is The student has The student is
(present able to write able to write the written not attempted
week’s/previous the program program with incomplete to write
week’s) without any minor logical program with program.
logical and error major logical
syntactical and syntactical
error and error
proper
indentation is
followed.
2. Implementation in the 5 Student is able Student is able Student is The student
target language with to execute, to execute the executed the has not
different inputs debug, and test program, but program executed the
the program for fails to debug, partially(fails to program.
all possible and test the meet desired
inputs/test program for all output)
cases. possible
inputs/test
cases.
3. Record 5 Student Student submits Student fails to The student
submits the the record on submit the does not
record on time time but not record on time . submit the
and, neatly documented record.
documented properly with all
with all possible
possible input/output
input/output samples.
samples.
4. Viva 2 Student Student answers Student Student fails
answers for for atleast 60% answers for to answer any
atleast 80% of of questions atleast 40% of question
questions questions
5. Internal Assessment 10
 DIGITAL DESIGN AND COMPUTER ORGANIZATION
Subject Code: BCS302
PRACTICAL COMPONENT OF IPCC :

Sl.NO Experiments

Given a 4-variable logic expression, simplify it using appropriate technique and simulate the same
1
using basic gates.

2 Design a 4 bit full adder and sub tractor and simulate the same using basic gates.

3 Design Verilog HDL to implement simple circuits using structural, Data flow and Behavioral model.

Design Verilog HDL to implement Binary Adder-Sub tractor – Half and Full Adder, Half and Full
4
Sub tractor.

5 Design Verilog HDL to implement Decimal adder.

6 Design Verilog program to implement Different types of multiplexer like 2:1, 4:1 and 8:1.

7 Design Verilog program to implement types of De-Multiplexer.

8 Design Verilog program for implementing various types of Flip-Flops such as SR, JK and D.
 Introduction to PSpice
In PSpice the program we run in order to draw circuit schematics is called CAPTURE. The program that will let us run
simulations and see graphic results is called PSPICE. You can run simulation from the program where your schematic is.
There are a lot of things we can do with PSpice, but the most important things for you to learn are

 Design and draw circuits

 Simulate circuits
 Analyze simulation results (Probe for older versions)

For this course you will not need the full capacity of CAPTURE. The devices that we will use are resistors, inductors,
capacitors and various independent/dependent sources. It is good to know that CAPTURE has extensive symbol libraries
and includes a fully integrated symbol editor for creating your own symbols or modifying existing symbols.

The main tasks in CAPTURE are

 Creating and editing designs
 Creating and editing symbols
 Creating and editing hierarchical designs
 Preparing your design for simulation

Procedure:
1. Run the CAPTURE program.
2. Select File/New/Project from the File menu.
3. On the New Project window select Analog or Mixed A/D, and give a name to your project then click OK.
4. The Create PSpice Project window will pop up, select Create a blank project, and then click OK.
5. Now you will be in the schematic environment where you are to build your circuit.
6. Select Place/Part from the Place menu.
7. Click ANALOG from the box called Libraries:, then look for the part called R. You can do it either by scrolling
down on the Part List: box or by typing R on the Part box. Then click OK.
8. Use the mouse to place the resistor where you want and then click to leave the resistor there. You can continue
placing as many resistors as you need and once you have finished placing the resistors right-click your mouse and
select end mode.
9. To rotate the components there are two options:
 Rotate a component once it is placed: Select the component by clicking on it then Ctrl-R
 Rotate the component before it is placed: Just Ctrl-R.
10. Select Place/Part from the Place menu. Connect source(STIM1) for supply.
11. Select Place/Wire and start wiring the circuit. To start a wire click on the component terminal where you want it to
begin, and then click on the component terminal where you want it to finish. You can continue placing wires until all
components are wired. Then right-click and select end wire.
12. .Once you have finished building your circuit, you can move on to the next step – prepare it for simulation.
13. Select PSpice/New Simulation Profile and type a name, this can be the same name as your project, and click
Create. Place the voltage markes at the input and output points.
14. The Simulations Settings window will now appear give the simulation time accordingly.
15. Now you are ready to simulate the circuit. Select PSpice/Run and wait until the PSpice finishes. Go back to
Capture and see the voltages and currents on all the nodes.
16. If you are not seeing any readout of the voltages and currents then select PSpice/Bias Point/Enable Bias Voltage
Display and PSpice/Bias Point/Enable Bias Current Display. Make sure that PSpice/ Bias Point/Enable is checked.
 LAB PROGRAMS
1. Given a 4-variable logic expression, simplify it using appropriate technique
and simulate the same using basic gates.

AIM: simplify given 4 variable logic expression using K-Map and simulate using
basic gates.

Theory: To minimize the given expression, we use Karnaugh maps technique. A

Karnaugh map (K-map) is a visual method used to simplify the algebraic expressions
in Boolean functions without having to resort to complex theorems or equation
manipulations. A K-map can be thought of as a special version of a truth table that
makes it easier to map out parameter values and arrive at a simplified Boolean
expression.A K-map is best suited for Functions with two to four variables.

F(A,B,C,D) = ∑m(3,7,11,12,13,14,15)

A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
 CIRCUIT:

OUTPUT:
 2. Design a 4 bit full adder and subtractor and simulate the same using basic
gates
Theory:
In Digital Circuits, a Binary Adder-Subtractor is capable of both the addition and subtraction
of binary numbers in one circuit itself. The operation is performed depending on the binary
value the control signal holds. It is one of the components of the ALU (Arithmetic Logic Unit).

As shown in the figure, the first full adder has a control line directly as its input(input carry
Cin), The input A0 (The least significant bit of A) is directly input in the full adder. The third
input is the exor of B0 and K. The two outputs produced are Sum/Difference (S0) and Carry
(C0).

If the value of K (Control line) is 1, the output of B0(exor)K=B0′(Complement B0). Thus the
operation would be A+(B0′). Now 2’s complement subtraction for two numbers A and B is
given by A+B’+Cin. This suggests that when K=1, the operation being performed on the four-
bit numbers is subtraction.

Similarly If the Value of K=0, B0 (exor) K=B0. The operation is A+B which is simple binary
addition. This suggests that When K=0, the operation is performed on the four-bit numbers in
addition.

Then C0 is serially passed to the second full adder as one of it’s outputs. The sum/difference
S0 is recorded as the least significant bit of the sum/difference. A1, A2, A3 are direct inputs to
the second, third and fourth full adders. Then the third input is the B1, B2, B3 EXORed with K
to the second, third and fourth full adder respectively. The carry C1, C2 are serially passed to
the successive full adder as one of the inputs. C3 becomes the total carry to the sum/difference.
S1, S2, S3 are recorded to form the result with S0.
 2a. 4 bit full adder

4 bit full adder Output

2b. 4- bit full subtractor

4 bit full adder-subtractor Output:

 Xilinx-ISE
Xilinx Tools is a suite of software tools used for the design of digital circuits implemented using Xilinx
Field Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD). The design
procedure consists of (a) design entry, (b) compilation and implementation of the design, (c) functional
simulation and (d) testing and verification. Digital designs can be entered in various ways using the above
CAD tools: using a schematic entry tool, using a hardware description language (HDL) – Verilog or
VHDL or a combination of both. In this lab we will only use the design flow that involves the use of
Verilog HDL.
The CAD tools enable you to design combinational and sequential circuits starting with Verilog HDL
design specifications.
The steps of this design procedure are listed below:
1. Create Verilog design input file(s) using template driven editor.
2. Compile and implement the Verilog design file(s).
3. Create the test-vectors and simulate the design (functional simulation) without using a PLD (FPGA or
CPLD).
4. Assign input/output pins to implement the design on a target device.
5. Download bitstream to an FPGA or CPLD device.
6. Test design on FPGA/CPLD device
A Verilog input file in the Xilinx software environment consists of the following segments:
 Header: module name, list of input and output ports.
 Declarations: input and output ports, registers and wires.
 Logic Descriptions: equations, state machines and logic functions.
 End: endmodule
 1. Creating a New Project

Xilinx Tools can be started by clicking on the Project Navigator Icon on the Windows desktop.
This should open up the Project Navigator window on your screen.
2. Opening a project

Select File->New Project to create a new project. This will launch the New Project Wizard
on the desktop. Fill up the necessary entries:
 Name: Write the name of your new project (E.g.: or_gate)
 Location: The directory where you want to store the new project
 Working Directory: The directory where all your project related files will be saved.
 Description: (Optional) A brief description of your project

Leave the top level module type as “HDL”.

Example: If the project name were “or_gate”, enter “or_gate” as the project name and then click “Next”
Clicking on NEXT should bring up the Project Settings window:

o Device Family: Family of the FPGA used. In this laboratory we will be using the
Spartan3E FPGAs

o Device: The number of the FPGA device. Note the device number on the FPGA
on the Digilent board! If you are unsure –ask the TA!

o Package: The type of package with the number of pins. The Spartan FPGA used
in this lab is packaged in C6DGQ (which is equivalent to CPG132) package. If
you are unsure, ask the T.A!
o Speed : The Speed grade is “-4”.
o Synthesis Tool: XST [VHDL/Verilog]
o Simulator: The tool used to simulate and verify the functionality of the design.
Choose ISim as the simulator.

Then click on NEXT to save the entries. The Project Summary window will show you a
summary of your project details. In this example we have used the project name “or_gate”. Pay
attention to the highlighted details in particular!
Click on ‘Finish’.

All project files such as schematics, netlists, Verilog files, VHDL files, etc., will be stored in a
subdirectory with the project name. A project can only have one top level HDL source file (or
schematic). Modules can be added to the project to create a modular, hierarchical design.
In order to open an existing project in Xilinx Tools, select File->Open Project to show the list
of projects on the machine. Choose the project you want and click OK.
If you would like to create a new source file, from the ISE window, right click on the project
name and choose ‘New source’ or click on the New source button on the toolbar You may
also choose Project-->New Source from the menu.
 3. Creating a Verilog HDL input file for a combinational logic design

In this lab we will enter a design using a structural or RTL description using the Verilog HDL.
You can create a Verilog HDL input file (.v file) using the HDL Editor available in the Xilinx
ISE Tools (or any text editor).

If adding an already existing source file (.v file) to the project, in the project Navigator window,
select Project -> Add Copy Source and browse through the disk for the source file.

If creating a new source file, in the Project Navigator window, select Project -> New Source.
A window pops up. (Note: “Add to project” option is selected by default. If you do not select it
then you will have to add the new source file to the project manually.)

Select Verilog Module and in the “File Name:” area, enter the name of the Verilog source file
you are going to create. Also make sure that the option Add to project is selected so that the
source need not be added to the project again. Then click on Next to accept the entries. This pops
up the following window.
In the Port Name column, enter the names of all input and output pins and specify the Direction
accordingly. A Vector/Bus can be defined by entering appropriate bit numbers in the MSB/LSB
columns. Then click on Next> to get a window showing all the new source information
Once you click on Finish, the source file will be displayed in the sources window in the Project
Navigator.
If a source has to be removed, just right click on the source file in the Sources in Project
window in the Project Navigator and select Remove in that. Then select Project -> Delete
Implementation Data from the Project Navigator menu bar to remove any related files.

4. Editing the Verilog source file

The source file will now be displayed in the Project Navigator window .The source file window
can be used as a text editor to make any necessary changes to the source file. All the input/output
pins will be displayed. Save your Verilog program periodically by selecting the File->Save from
the menu. You can also edit Verilog programs in any text editor and add them to the project
directory using “Add Copy Source”.

 Adding Logic in the generated Verilog Source code template:

A brief Verilog Tutorial is available in Appendix-A. For the language syntax and for
construction of logic equations please refer to Appendix-A.

The Verilog source code template generated shows the module name, the list of ports and
also the declarations (input/output) for each port. Combinational logic code can be added
to the verilog code after the declarations and before the endmodule line.

For example, an output z in an OR gate with inputs a and b can be described as,
assign z = a | b;
Remember that the variable names are case sensitive.
 5. Compilation and Implementation of the Design

The design has to be compiled and implemented before it can be checked for correctness, by
running functional simulation or downloaded onto the prototyping board. With the top-level
Verilog file opened (can be done by double-clicking that file) in the HDL editor window in the
right half of the Project Navigator, and the view of the project being in the Module view, the
Implement Design option can be seen in the Process Window. Design Entry Utilities and
Generate Programming File options can also be seen in the process view. The former can be
used to include user constraints, if any and the latter will be discussed later.

To compile the design, expand the Implement Top Module (Figure 10) by clicking on Process-
>Implement Top Module OR by right clicking on the design and choosing Implement Top
Module. It will go through steps like Check Syntax, Compile Logic, Interpret Feedbacks,
Reformat Logic and Optimize Hierarchy. If any of these steps could not be done or done with
errors, it will place a mark in front of that, otherwise a tick mark will be placed after
each of them to indicate the successful completion. If everything is done successfully, a
mark will be placed before the Synthesize-XST option. If there are warnings, one can see
mark in front the Console window present at the bottom of the Navigator window. Every
timethe design file is saved; all these marks disappear asking for a fresh compilation.
If there are no errors then the tool shows that the design has been synthesized successfully.

6. Functional Simulation of Combinational Designs

Creating a Testbench

To check the functionality of a design, we have to apply test vectors and simulate the circuit. In
order to apply test vectors, a testbench file is written. Essentially it will supply all the inputs to
the module designed and can check the outputs of the module. Example: For the 2 input OR
Gate, the test bench is created as follows:

1. Right click on the design (or_gate) and select New Source

2. From the new source wizard pop up, select Verilog Test Fixture and enter a
name for the test bench (eg: or_tb) in the File name field as shown in the Figure
and click Next.

3. The New source wizard will show the design that the test bench is associated with
(this should be the design that you wish to simulate- in this case, or_gate). Click
Next and then Finish.

4. The ISE project navigator will generate some boilerplate test bench code for you.
 Simulating and Viewing the Output Waveforms

In the process window right click on Simulate Behavioral Model and click on Run.
If the code is free of syntax errors, this will launch the ISim simulator window (Note; In case you
encounter an error when trying to launch the simulator, right click on the design and ensure that
“manual compile order’ is not checked). Also make sure that the test bench passes the syntax
checks. You will be able to observe the simulation waveforms as per the test stimulus in this
window.
3. Design Verilog HDL to implement simple circuits using Structural,Data
flow and Behavioral model.

INPUT OUTPUT
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

Y=AB

Structural :

module cktand(output Y, input A, B);

and(Y, A, B);
endmodule

Dataflow :

module andgate(output Y, input A, B);

assign Y = A & B;
endmodule

Behavioral :

module andgate(Y,A,B);
input A,B;
output Y;
reg Y;
always @ (A or B)
begin
if(A ==1 && B == 1)
Y = 1;
else
Y = 0;
end
endmodule
4. Design Verilog HDL to implement Binary Adder-Subtractor – Half
andFull Adder, Half and Full Subtractor.

Half Adder:

module half_adder(input a,b, output sum, cout );

assign sum = a ^ b ;
assign cout = a & b;
endmodule

INPUT OUTPUT
COU
A B SUM
T
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Half subtractor:

module half_sub(input a,b, output br,dif);

assign dif = a ^ b;
assign br = ~a & b;
endmodule
 INPUT OUTPUT
A B DIFF BC
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Full adder:

module full_adder(input a,b,c,output sum,cout);

assign sum = (a ^ b ^ c );
assign cout = (a & b ) | (b & c) | (a & c);
endmodule

INPUT OUTPUT
C COU
A B SUM
T
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Full subtractor :
module full_sub(input a,b,c,output br,dif);
assign dif = (a ^ b ^ c );
assign br = (~a & b ) | (b & c) | (~a & c);
endmodule

INPUT OUTPUT
A B C DIFF BR
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
5. Design Verilog HDL to implement Decimal adder

module bcdadder(a,b,carry_in,sum,carry);
input [3:0]a,b;
input carry_in;
output[3:0]sum;
output carry;
reg[4:0]sum_temp;
reg[3:0]sum;
reg carry;
always @ (a,b,carry_in)
begin
sum_temp = a+b+carry_in;
if(sum_temp > 9)
begin
sum_temp = sum_temp + 6;
carry = 1;
sum = sum_temp[3:0];
end
else
begin
carry = 0;
sum = sum_temp[3:0];
end
end
endmodule
 In the above diagram,

1. We take a 4-bit Binary-Adder, which takes addend and augend bits as an input with an
input carry 'Carry in'.
2. The Binary-Adder produces five outputs, i.e., Z8, Z4, Z2, Z1, and an output carry K.
3. With the help of the output carry K and Z8, Z4, Z2, Z1 outputs, the logical circuit is
designed to identify the Cout
4. The Z8, Z4, Z2, and Z1 outputs of the binary adder are passed into the 2nd 4-bit binary
adder as an Augend.
5. The addend bit of the 2nd 4-bit binary adder is designed in such a way that the 1st and the
4th bit of the addend number are 0 and the 2nd and the 3rd bit are the same as Cout. When
the value of Cout is 0, the addend number will be 0000, which produce the same result as
the 1st 4-bit binary number. But when the value of the C out is 1, the addend bit will be
0110, i.e., 6, which adds with the augent to get the valid BCD number.

Example: 1001+1000
1. First, add both the numbers using a 4-bit binary adder and pass the input carry to 0.
2. The binary adder produced the result 0001 and carried output 'K' 1.
3. Then, find the Cout value to identify that the produced BCD is invalid or valid using the
expression Cout=K+Z8.Z4+Z8.Z2.
K=1
Z8 = 0
Z4 = 0
Z2 = 0
Cout = 1+0*0+0*0
Cout = 1+0+0
Cout = 1
4. The value of Cout is 1, which expresses that the produced BCD code is invalid. Then, add
the output of the 1st 4-bit binary adder with 0110.
= 0001+0110
= 0111
5. The BCD is represented by the carry output as:
BCD=Cout Z8 Z4 Z2 Z1=1 0 1 1 1
6. Design Verilog program to implement Different types of multiplexer like
2:1,4:1 and 8:1.

2:1 MUX :
module mux2to1(D0, D1, S, Y);
output Y;
input D0, D1, S;
assign Y=(D0 & ~S) | (D1 & S);
or
assign Y=(S)? D1:D0;
endmodule

INPUT OUTPUT
S Y
0 D0
1 D1

4:1 MUX :

module mux4to1(output Y, input D0, D1, D2, D3, S0, S1);

assign Y = (D0 & ~S0 & ~S1) | (D1 & ~S0 & S1) | (D2 & S0 & ~S1) |
(D3 & S0 & S1);
endmodule
 INPUT OUTPUT
S0 S1 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

8:1 MUX :

module mux8to1(output Y, input D0, D1, D2, D3, D4, D5, D6, D7, S0, S1,
S2);

assign Y = (D0 & ~S0 & ~S1 & ~S2) | (D1 & ~S0 & ~S1 & S2) | (D2 &
~S0 & S1 & ~S2) | (D3 & ~S0 & S1 & S2) | (D4 & S0 & ~S1 & ~S2) | (D5
& S0 & ~S1 & S2) | (D6 & S0 & S1 & ~S2) | (D7 & S0 & S1 & S2);

Endmodule

INPUT OUTPUT
S0 S1 S2 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7
7. Design Verilog program to implement types of De-Multiplexer

1:8 DEMUX :

module demux1to8(d,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
input s,s0,s1,s2;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0 = (d & ~s0 & ~s1 & ~s2),
d1=(d & ~s0 & ~s1 & s2),
d2=(d & ~s0 & s1 & ~s2),
d3=(d & ~s0 & s1 & s2),
d4=(d & s0 & ~s1 & ~s2),
d5=(d & s0 & ~s1 & s2),
d6=(d & s0 & s1 & ~s2),
d7=(d & s0 & s1 & s2);
endmodule

INPUT OUTPUT
s0 s1 s2 d0 d1 d2 d3 d4 d5 d6 d7
0 0 0 d 0 0 0 0 0 0 0
0 0 1 0 d 0 0 0 0 0 0
0 1 0 0 0 d 0 0 0 0 0
0 1 1 0 0 0 d 0 0 0 0
1 0 0 0 0 0 0 d 0 0 0
1 0 1 0 0 0 0 0 d 0 0
1 1 0 0 0 0 0 0 0 d 0
1 1 1 0 0 0 0 0 0 0 d
1:4 demux :

module demux1to4(d,s0,s1,d0,d1,d2,d3);
input d,s0,s1;
output d0,d1,d2,d3;
assign d0 = (d & ~s0 & ~s1),
d1 = (d & ~s0 & s1),
d2 = (d & s0 & ~s1),
d3 = (d & s0 &s1);
endmodule

INPUT OUTPUT
s0 s1 d0 d1 d2 d3
0 0 d 0 0 0
0 1 0 d 0 0
1 0 0 0 d 0
1 1 0 0 0 d

1:2 demux :

module demux1to2(d,s,d0,d1);
input d,s;
output d0,d1;
assign d0 = (d & ~s),
d1 = (d & s);
endmodule
INPUT OUTPUT
s d0 d1
0 d O
1 0 d
8. Design Verilog program for implementing various types of Flip-Flops
suchas SR, JK and D

D Flip flop(POSITIVE EDGE TRIGRRED FLIP FLOP) :

module dff(D,CLK,Q);
input D, CLK;
output Q;
reg Q;
always @(posedge CLK)
begin
Q <= D;
end
endmodule

INPUT OUTPUT
COMMENTS
CLK D Q
↑ D D Q=D
NO
X D Q
CHANGE
SR FLIPFLOP :

module SR_flipflop ( input clk, rst_n, input s,r,output reg q,output q_bar )
always@(posedge clk) begin
if(!rst_n) q <= 0;
else begin
case({s,r})
2'b00: q <= q;
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= 1'bx;
endcase
end
end
assign q_bar = ~q;
endmodule

INPUT OUTPUT
COMMENTS
clk s r q
↑ 0 0 Q NO CHANGE
↑ 0 1 0 RESET
↑ 1 0 1 SET
↑ 1 1 x FORBIDDEN
JK FLIP-FLOP (POSITIVE EDGE TRIGGERED FLIP-FLOP) :

module JK_flipflop (input clk, rst_n,input j,k,output reg q, output q_bar);

always@(posedge clk) begin
if(!rst_n) q <= 0;
else begin
case({j,k})
2'b00: q <= q;
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= ~q;
endcase
end
end
assign q_bar = ~q;
endmodule

INPUT OUTPUT
COMMENTS
clk j k q
↑ 0 0 Q NO CNANGE
↑ 0 1 0 0
↑ 1 0 1 1
↑ 1 1 q’ TOGGLE