Computer Architecture Lec 8

Input/output

-External Devices

I/O operations are accomplished through a wide assortment of external devices that
provide a means of exchanging data between the external environment and the
computer. An external device attaches to the computer by a link to an I/O module
(Figure 8.1). The link is used to exchange control, status, and data between the I/O
module and the external device. An external device connected to an I/O module is
often referred to as a peripheral device or, simply, a peripheral.

Figure 8.1 Generic Model of an I/O Module

We can broadly classify external devices into three categories:

• Human readable: Suitable for communicating with the computer user
• Machine readable: Suitable for communicating with equipment
• Communication: Suitable for communicating with remote devices

Examples of human-readable devices are video display terminals (VDTs) and printers.
Examples of machine-readable devices are magnetic disk and tape systems, and
sensors and actuators, such as are used in a robotics application.

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Communication devices allow a computer to exchange data with a remote device,
which may be a human-readable device, such as a terminal, a machine-readable
device, or even another computer.

In very general terms, the interface to the I/O module is in the form of control, data,
and status signals. Control signals determine the function that the device will
perform, such as send data to the I/O module (INPUT or READ), accept data from the
I/O module (OUTPUT or WRITE), report status, or perform some control function
particular to the device (e.g., position a disk head). Data are in the form of a set of
bits to be sent to or received from the I/O module. Status signals indicate the state
of the device.

-Keyboard/Monitor

The most common means of computer/user interaction is a keyboard/monitor

arrangement. The user provides input through the keyboard. This input is then
transmitted to the computer and may also be displayed on the monitor. In addition,
the monitor displays data provided by the computer.
The basic unit of exchange is the character. Associated with each character is a code,
typically 7 or 8 bits in length. The most commonly used text code is the International
Reference Alphabet (IRA). Each character in this code is represented by a unique 7-
bit binary code; thus, 128 different characters can be represented. Characters are of
two types: printable and control.
Printable characters are the alphabetic, numeric, and special characters that can be
printed on paper or displayed on a screen. For keyboard input, when the user
depresses a key, this generates an electronic signal that is interpreted by the
transducer in the keyboard and translated into the bit pattern of the corresponding
IRA code. This bit pattern is then transmitted to the I/O module in the computer. At
the computer, the text can be stored in the same IRA code. On output, IRA code
characters are transmitted to an external device from the I/O module. The
transducer at the device interprets this code and sends the required electronic
signals to the output device either to display the indicated character or perform the
requested control function.

-Disk Drive

A disk drive contains electronics for exchanging data, control, and status signals with
an I/O module plus the electronics for controlling the disk read/write mechanism. In

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a fixed-head disk, the transducer is capable of converting between the magnetic
patterns on the moving disk surface and bits in the device’s buffer.
A moving-head disk must also be able to cause the disk arm to move radially in and
out across the disk’s surface.

Module Function

The major functions or requirements for an I/O module fall into the following
categories:

• Control and timing

• Processor communication
• Device communication
• Data buffering
• Error detection

During any period of time, the processor may communicate with one or more
external devices in unpredictable patterns, depending on the program’s need for I/O.
The internal resources, such as main memory and the system bus, must be shared
among a number of activities, including data I/O. Thus, the I/O function includes a
control and timing requirement, to coordinate the flow of traffic between internal
resources and external devices.
If the system employs a bus, then each of the interactions between the processor
and the I/O module involves one or more bus arbitrations. Processor
communication involves the following:

- Command decoding: The I/O module accepts commands from the processor,
typically sent as signals on the control bus. For example, an I/O module for a
disk drive might accept the following commands: READ SECTOR, WRITE
SECTOR, SEEK track number, and SCAN record ID. The latter two commands
each include a parameter that is sent on the data bus.

- Data: Data are exchanged between the processor and the I/O module over
the data bus.

- Status reporting: Because peripherals are so slow, it is important to know the

status of the I/O module. For example, if an I/O module is asked to send data
to the processor (read), it may not be ready to do so because it is still working
on the previous I/O command. This fact can be reported with a status signal.

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 - Address recognition: Just as each word of memory has an address, so does
each I/O device. Thus, an I/O module must recognize one unique address for
each peripheral it controls.

On the other side, the I/O module must be able to perform device communication.
This communication involves commands, status information, and data.
An essential task of an I/O module is data buffering. Whereas the transfer rate into
and out of main memory or the processor is quite high, the rate is orders of
magnitude lower for many peripheral devices and covers a wide range. Data coming
from main memory are sent to an I/O module in a rapid burst. The data are buffered
in the I/O module and then sent to the peripheral device at its data rate. In the
opposite direction, data are buffered so as not to tie up the memory in a slow
transfer operation. Thus, the I/O module must be able to operate at both device and
memory speeds. Similarly, if the I/O device operates at a rate higher than the
memory access rate, then the I/O module performs the needed buffering operation.
Finally, an I/O module is often responsible for error detection and for subsequently
reporting errors to the processor. One class of errors includes mechanical and
electrical malfunctions reported by the device (e.g., paper jam, bad disk track).
Another class consists of unintentional changes to the bit pattern as it is transmitted
from device to I/O module. Some form of error-detecting code is often used to
detect transmission errors. A simple example is the use of a parity bit on each
character of data. For example, the IRA character code occupies 7 bits of a byte. The
eighth bit is set so that the total number of 1s in the byte is even (even parity) or odd
(odd parity). When a byte is received, the I/O module checks the parity to determine
whether an error has occurred.

DIRECT MEMORY ACCESS

In processor, to transfer data between memory and an I/O module, and any data
transfer must traverse a path through the processor.
Thus, each I/O suffer from two inherent drawbacks:

1- The I/O transfer rate is limited by the speed with which the processor can
test and service a device.
2- The processor is tied up in managing an I/O transfer; a number of
instructions must be executed for each I/O transfer.

When large volumes of data are to be moved, a more efficient technique is required:
direct memory access (DMA).

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I/O CHANNELS AND PROCESSORS

The Evolution of the I/O Function

As computer systems have evolved, there has been a pattern of increasing

complexity and sophistication of individual components. Nowhere is this more
evident than in the I/O function. We have already seen part of that evolution. The
evolutionary steps can be summarized as follows:

1. The CPU directly controls a peripheral device. This is seen in simple

microprocessor- controlled devices.
2. A controller or I/O module is added. The CPU uses programmed I/O without
interrupts. With this step, the CPU becomes somewhat divorced from the
specific details of external device interfaces.
3. The same configuration as in step 2 is used, but now interrupts are employed.
The CPU need not spend time waiting for an I/O operation to be performed,
thus increasing efficiency.
4. The I/O module is given direct access to memory via DMA. It can now move a
block of data to or from memory without involving the CPU, except at the
beginning and end of the transfer.
5. The I/O module is enhanced to become a processor in its own right, with a
specialized instruction set tailored for I/O. The CPU directs the I/O processor
to execute an I/O program in memory. The I/O processor fetches and
executes these instructions without CPU intervention. This allows the CPU to
specify a sequence of I/O activities and to be interrupted only when the
entire sequence has been performed.
6. The I/O module has a local memory of its own and is, in fact, a computer in
its own right. With this architecture, a large set of I/O devices can be
controlled, with minimal CPU involvement. A common use for such an
architecture has been to control communication with interactive terminals.
The I/O processor takes care of most of the tasks involved in controlling the
terminals.
As one proceeds along this evolutionary path, more and more of the I/O function is
performed without CPU involvement. The CPU is increasingly relieved of I/O-related
tasks, improving performance. With the last two steps (5–6), a major change occurs
with the introduction of the concept of an I/O module capable of executing a
program. For step 5, the I/O module is often referred to as an I/O channel. For step

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6, the term I/O processor is often used. However, both terms are on occasion applied
to both situations. In what follows, we will use the term I/O channel.

Characteristics of I/O Channels

The I/O channel represents an extension of the DMA concept. An I/O channel has
the ability to execute I/O instructions, which gives it complete control over I/O
operations. In a computer system with such devices, the CPU does not execute I/O
instructions. Such instructions are stored in main memory to be executed by a
special-purpose processor in the I/O channel itself. Thus, the CPU initiates an I/O
transfer by instructing the I/O channel to execute a program in memory. The
program will specify the device or devices, the area or areas of memory for storage,
priority, and actions to be taken for certain error conditions. The I/O channel follows
these instructions and controls the data transfer.

Figure 8.5 I/O Channel architecture

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Two types of I/O channels are common, as illustrated in Figure 8.5. A selector
channel controls multiple high-speed devices and, at any one time, is dedicated to
the transfer of data with one of those devices. Thus, the I/O channel selects one
device and effects the data transfer. Each device, or a small set of devices, is handled
by a controller, or I/O module, that is much like the I/O modules we have been
discussing. Thus, the I/O channel serves in place of the CPU in controlling these I/O
controllers. A multiplexor channel can handle I/O with multiple devices at the same
time. For low-speed devices, a byte multiplexor accepts or transmits characters as
fast as possible to multiple devices. For example, the resultant character stream
from three devices with different rates and individual streams A1A2A3A4 . . .,
B1B2B3B4 . . ., and C1C2C3C4 . . . might be A1B1C1A2C2A3B2C3A4, and so on. For
high-speed devices, a block multiplexor interleaves blocks of data from several
devices.

DMA Function

DMA involves an additional module on the system bus. The DMA module (Figure 8.2)
is capable of mimicking the processor and, indeed, of taking over control of the
system from the processor. It needs to do this to transfer data to and from memory
over the system bus. For this purpose, the DMA module must use the bus only when
the processor does not need it, or it must force the processor to suspend operation
temporarily. The latter technique is more common and is referred to as cycle
stealing, because the DMA module in effect steals a bus cycle.

Figure 8.2 typical DMA Block Diagram

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When the processor wishes to read or write a block of data, it issues a command to
the DMA module, by sending to the DMA module the following information:
- Whether a read or write is requested, using the read or write control line
between the processor and the DMA module The address of the I/O device
involved, communicated on the data lines
- The starting location in memory to read from or write to, communicated on
the data lines and stored by the DMA module in its address register
- The number of words to be read or written, again communicated via the data
lines and stored in the data count register

The processor then continues with other work. It has delegated this I/O operation to
the DMA module. The DMA module transfers the entire block of data, one word at a
time, directly to or from memory, without going through the processor.
When the transfer is complete, the DMA module sends an interrupt signal to the
processor. Thus, the processor is involved only at the beginning and end of the
transfer.
Figure 8.3 shows where in the instruction cycle the processor may be suspended.
In each case, the processor is suspended just before it needs to use the bus. The
DMA module then transfers one word and returns control to the processor. Note
that this is not an interrupt; the processor does not save a context and do something
else. Rather, the processor pauses for one bus cycle. The overall effect is to cause
the processor to execute more slowly. Nevertheless, for a multiple-word I/O
transfer, DMA is far more efficient than interrupt-driven or programmed I/O.
The DMA mechanism can be configured in a variety of ways. Some possibilities are
shown in Figure 8.4. In the first example, all modules share the same system bus. The
DMA module, acting as a surrogate processor, uses programmed I/O to exchange
data between memory and an I/O module through the DMA module.

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Figure 8.3 DMA and Interrupt Breakpoint during an Instruction Cycle

Figure 8.4 Alternative DMA configurations

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This configuration, while it may be inexpensive, is clearly inefficient. As with
processor-controlled programmed I/O, each transfer of a word consumes two bus
cycles.
The number of required bus cycles can be cut substantially by integrating the DMA
and I/O functions. As Figure 8.4b indicates, this means that there is a path between
the DMA module and one or more I/O modules that does not include the system
bus. The DMA logic may actually be a part of an I/O module, or it may be a separate
module that controls one or more I/O modules. This concept can be taken one step
further by connecting I/O modules to the DMA module using an I/O bus (Figure
8.4c). This reduces the number of I/O interfaces in the DMA module to one and
provides for an easily expandable configuration. In both of these cases (Figures 8.4b
and c), the system bus that the DMA module shares with the processor and memory
is used by the DMA module only to exchange data with memory. The exchange of
data between the DMA and I/O modules takes place off the system bus.

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