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Day2_SV_Assignment_for_next_day

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4 views3 pages

Day2_SV_Assignment_for_next_day

Uploaded by

nareshsambhnani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SV Assignment

 Traffic Light Controller


Design a traffic light controller (single post) with the following specifications and verify its
correctness:

RED N1 ticks
N3 ticks

YELLOW GREEN
N2 ticks

o Three states (RED, GREEN, YELLOW) defined as enum data types in a separate package
o Create a state machine with initial state as RED and transition will be according to as
shown in the above diagram.
o Input:
 Clock
 Parameter structure containing counter values N1, N2 & N3
o Output:
 A signal representing state change
 A 2 bit signal containing value of state as below:
 2’b00 if state == RED
 2’b01 if state == GREEN
 2’b10 if state == YELLOW
 2’bxx if state == UNDEFINED
 Circular FIFO
Design a circular FIFO model with the following specifications:
o Write Data (Width & type parameterized)
o Read Data (Width & type parameterized)
o Clock & reset (1 bit signal each)
o Write & read enable (1 bit signal each)
o Structure containing status flags (internal variables)
 Empty flag (high when FIFO is empty else low)
 Over-write flag (high if overwrite else low)
Above FIFO model should be synthesizable (Look for info message in Precision run transcript
for inferred RAMs etc.). Also, verify its complete functionality using simulator by creating a test
bench. Probe the status registers also to check the intended behavior.

Design Functionality:

 Write: Writing mechanism is non-blocked. If FIFO is rolled over, it will write to the
previous written location and will set the overwrite flag high.
 Read: Read the oldest data in FIFO.

Test bench Functionality:

 Write for multiple clock cycles (Till first over-write happens)


 Read till FIFO is empty
 Write for 10 clock cycles
 Read till FIFO is empty
 Master & Slave interface
 Create three modules Master, Slave1 & Slave2 connected with interface
 Master and Slaves are doing communication through common clock
 Slave request for some processing using req signal and Master will process request after
sending acknowledge signal (ack). Only one request will be handled at a time by Master.
ack is a structure {request_received, request_processed} signifying 2 stage
acknowledgement.
 Request would be to invert the bits (byte type) as input and byte type as output
 If Master is busy, it will generate the busy signal

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