UNIT III

INTERFACING

Parallel communication interface (8255) – Serial communication interface (8251) – D/A and A/D Interface –
Programmable Timer controller (8254) – Keyboard /display controller (8279) – Programmable Interrupt controller
(8259) – DMA controller (8237).

2. Describe the internal block diagram of 8255 (December 2010) (or)

Parallel communication interface (8255)
(Programmable pe ripheral interface)
 The 8255 is a general purpose programmable I/O device used for parallel data transfer.
 It has 24 I/O programmable pins which can be grouped into three 8 bit parallel ports of Port A ,
Port B and Port C. It is TTL compatible.
 The eight bit ports of PORT C can be used as individual bits or be grouped into two 4 bit ports.
Cupper (Cu) and CLower (CL).
 The functions of 8255 are classified according to two modes. The Bit Set/Reset mode and the I/O
mode. The BSR mode is used to set or reset the bits in Port C.
 The 8-bit data bus buffer is controlled by the read/write control logic. The read/write control logic
manages all of the internal and external transfers of both data and control words.
 RD , WR , A1 , A0 and RESET are the inputs provided by the microprocessor to the READ/ WRITE
control logic of 8255.
 The 8-bit, 3-state bidirectional buffer is used to interface the 8255 internal data bus with the
external system data bus.
 This buffer receives or transmits data based on the execution of input or output instructions by the
microprocessor. The control word is also transferred through the buffer.

Functions of Pin:
The signal descriptions of 8255 are briefly presented as follows:
• PA7 -PA0 : These are eight port A lines that acts as either latched output or buffered input lines
depending upon the control word loaded into the control word register.
• PC7 -PC4 : Upper nibble of port C lines. They may act as either output latches or input buffers lines.
• This port also can be used for generation of handshake lines in mode 1 or mode 2.

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• PC3 -PC0 : Lower nibble of port C lines. They may act as either output latches or input buffers lines.
• This port also can be used for generation of handshake lines in mode 1 or mode 2.
• PB0 -PB7 : These are eight port B lines which are used as latched output lines or buffered input lines
in the same way as port A.
• A1 -A0 : These are the address input lines and are driven by the microprocessor.
• In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus, the A 0 and A1
pins of 8255 are connected with A1 and A2 of 8086 respectively.
• These address lines A1 - A0 are used for addressing any one of the four registers, i.e. three ports and
a control word register as given in table below.

A1 A0 Select

0 0 PA

0 1 PB

1 0 PC
1 1 Control register

• RD : This is the input line driven by the microprocessor and should be low to indicate read
operation to 8255.
• WR : This is an input line driven by the microprocessor. A low on this line indicates write
operation.
• CS : This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and WR
Signals.
• D0 -D7 : These are the data bus lines carry data or control word to/from the microprocessor.
• RESET : A logic high on this line, clears the control word register of 8255. All ports are set as
input ports by default after reset.

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 Fig-6: Pin diagram &Block diagram of 8255 Programmable Peripheral interface.
The 8255 consists of four sections namely,
 Data bus buffer
 Read/write control logic
 Group A control
 Group B control
Data Bus buffer:
• It is an 8-bit bidirectional Data bus.
• Used to interface between 8255 data bus with system bus.
• The internal data bus and Outer pins D0 -D7 pins are connected in internally.
• The direction of data buffer is decided by Read/Control Logic.

Read/Write Control Logic:

• This is getting the input signals from control bus and Address bus
• Control signal are RD and WR.
• Address signals are A0, A1and CS.
• 8255 operation is enabled or disabled by CS.
Group A and Group B control:
• Group A and B get the Control Signals from CPU and send the command to the individ ual control
blocks.
• Group A send the control signal to port A and Port C (Upper) PC7-PC4.
• Group B send the control signal to port B and Port C (Lower) PC3-PC0.
PORT A:
• This is an 8-bit buffered I/O latch.
• It can be programmed by mode 0 , mode 1 & mode 2 .
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PORT B:
• This is an 8-bit buffer I/O latch.
• It can be programmed by mode 0 and mode 1.
PORT C:
• This is an 8-bit Unlatched buffer Input and an Output latch.
• It is divided into two parts as Port C (Upper) PC7-PC4 & Port C (Lower) PC3-PC0
• It can be programmed by bit set/reset operation.

CONTROL WORD FORMATS:

There are two control word formats i) BSR mode ii) Input / Output mode

FOR BIT SET/RESET MODE:

• PC0-PC7 is set or reset as per the status of D0.

• A BSR word is written for each bit of Port C

Example:
• PC3 is Set then control register will be 0XXX0111.
• PC4 is Reset then control register will be 0XXX01000.
• X is a don‘t care.

FOR I/O MODE

The mode format for I/O as shown in figure

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 • The control word for both Mode 1 and Mode 2 are same.
• Bit D7 is used for specifying whether word loaded in to Bit set/reset mode or Mode definition word.
• D7=1=Mode definition mode.
• D7=0=Bit set/Reset mode.

Steps to communicate with peripherals through the 8255:

1. Determine the addresses of Port A, port B, port C and control register according to the chip select logic and
address lines A0 and A1.
2. Write a control word in the control register.
3. Write I/O instructions to communicate with peripherals through ports A, B and C.
Operation modes
BIT SET/RESET MODE:
• The PORT C can be Set or Reset by sending OUT instruction to the CONTROL registers.
• In BSR mode, individual bits of Port C can be used for applications such as on/off switch.
• The control word sets or resets one bit at a time.
• BSR control word does not alter any previously transmitted control word with bit D7=1. Thus the
I/O operations of Port A and Port B are not affected by a BSR control word.

I/O MODES:
 The I/O mode is divided into three modes as mode 0, mode 1, and mode 2.
o Mode 0 – Basic I/O mode
o Mode 1 – strobbed I/O mode
o Mode 2 – Bidirectional data transfer mode

MODE 0 (Simple input / Output):

• In this mode , port A and port B are used as two simple 8 bit I/O ports and port C as two 4 bit ports
used as individually (Simply).

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Features:
• Outputs are latched, Inputs are buffered.
• Ports do not have Handshake or interrupt capability.

MODE 1 : (Input/output with Hand shake)

• In this mode, input or output is transferred by hand shaking Signals. The handshaking signals are
exchanged between the microprocessor and peripherals.

The features of this mode include the following

1. Two ports (A and B) function as 8 bit I/O ports .They can be configured either as input or output ports.
2. Each port uses 3 lines from port C as handshake signals. The remaining 2 lines of PORT C can be used for
simple I/O operations.
3. Input and outputs data are latched.
4. Interrupt logic is supported.
In 8255, the specific lines from PORT C used for handshake signals vary according to the I/O function of a
port. Therefore input and output functions in Mode 1 are discussed separately.
Input control signal definitions (Mode 1 ):
• STB( Strobe input ) – If this line falls to logic low level, the data available at 8-bit input port is loaded into
input latches.
• IBF ( Input buffer full ) – If this signal rises to logic 1, it indicates that data has been loaded into latches,
i.e. it works as an acknowledgement.
• INTR ( Inte rrupt request ) – This active high output signal can be used to interrupt the CPU whenever an
input device requests the service. INTR is set by a high STB pin and a high at IBF pin.
INTE is an internal flag that can be controlled by the bit set/reset mode of either PC4(INTEA) or
PC2(INTEB) as shown in fig.
INTR is reset by a falling edge of RD input. Thus an external input device can be request the service of
the processor by putting the data on the bus and sending the strobe signal.

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Output control signal definitions (Mode 1) :
• OBF (Output buffer full ) – When this signal falls to low, indicates that CPU has written data to the
specified output port.
• ACK ( Acknowledge input ) – ACK signal acts as an acknowledgement to be given by an output
device. ACK signal, whenever low, informs the CPU that the data transferred by the CPU to the output
device through the port is received by the output device.
• INTR ( Interrupt request ) – Thus an output signal that can be used to interrupt the CPU when an
output device acknowledges the data received from the CPU.

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 MODE 2: Bi-directional I/O data transfer:

• This mode allows bidirectional data transfer over a single 8-bit data bus using handshake signals.
• In this mode, Port A can be configured as the bidirectional port and Port B is either in Mode 0 or
Mode 1.
• Port A uses 5 signals from Port C as handshake signals for data transfer. The remaining 3 signals
from Port C can be used either as simple I/O or as handshake for Port B.
.

************************************************************************

3.Explain in detail about Serial Communication Interface

Serial I/O Interfacing:

The MPU (Microprocessor Unit) selects the peripheral through chip select and uses the control signals.
Read to receive data and write to transmit data.

Transmission format:

 In synchronous format, receiver and transmitter are synchronized with the same clock and a block
of characters are transmitted along with the synchronization information. This format is generally
used for high speed transmission (more than 20 Kbits/second)
 The asynchronous format is character oriented. Each character carries the information of the start
and stop bits. Transmission starts with one start bit (low) followed by a character , and one or two
stop bits (high). It is used in low speed transmission less than 20Kbits/second.

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 Communication Modes:

Simplex - Data are transmitted in only one direction.

Example: Transmission from a microcomputer to a printer.

Duplex - Data flow in both direction

 Half Duplex - If the transmission goes one way at a time it is called half duplex. Ex.:
walky-talky
 Full Duplex – If both transmitting and receiving signals goes simultaneously, it is called
full duplex. Example: Transmission between computers.

Rate of transmission

The rate at which the bits are transmitted is called bits/second or Baud rate

For example 1200 baud = 1200 bits/second

It indicates1200 bits are transmitted in a second. For 1 bit it takes 1/1200 =0.83 ms.

Programmable serial Communication Interface (8251):

Programmable serial interface

The 8251 is a programmable USART (Universal Synchronous Asynchronous Receiver

Transmitter) is designed for Synchronous and Asynchronous serial communication packaged in a 28 pin
DIP.

The 8251 receives parallel data from the CPU and transmits serial data after conversion. This device also
receives serial data from the outside and transmits parallel data to the CPU after conversion.

Features of 8251
 Supports both synchronous and asynchronous modes of operation
 Synchronous baud rate – 0 to 64 K baud
 Asynchronous baud rate – 0 to 19.2 K baud
 Contains full duplex double buffered system
 Provides error detection to detect parity and framing errors
 28-pin DIP package, TTL compatible
 Single +5V supply
Block diagram of 8251:

 Intel 8251 A is a programmable Serial Communication interface IC. It is available in 28 pin Dual-In-Line
package. It is used for synchronous & asynchronous serial data communication. The functional block
diagram is shown below. It consists of 5 sections namely,
o Data bus buffer
o Read/Write control logic
o Modem control

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 o Transmitter section
o Receiver section
Data Bus Buffer:
 It is used to temporarily store the data which is to be transmitted (or) received. It consists of D 0 - D7 signals.
Read/Write Control Logic:
 It consists of 3 registers namely data bus buffer, control register and status register.
 Reset, CLK, C / D , R D , W R , C S signals are associated with this block, If C/D is high, the control
register is selected for writing control word.
 If C/D is low, then, the data buffer is selected for read/write operation.
 CS signal means chip select signal. It is generated by using unused address lines of processor. If it is low,
then the chip is activated. If Reset signal is high, then 8251 is forced to enter into the idle mode.
 CLK signal is used for 8251 to communicate with CPU.
 RD and WR signal are used for read & write operations.

Fig: BLOCK DIAGRAM OF 8251

MODEM Control
 This block is used to interface MODEM to 8251. It is used to provide data communication through
MODEM over the telephone cable.
Transmitter Section

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 The data which is to be transmitted is given by using D0 - D7 signals to the data bus buffer. Then, the data
is transferred to the Transmit Buffer. Here, the parallel data is converted to the serial data. It is transmitted
by using the signal TXD.
 This section consists of 2 registers namely transmit buffer register & output register. Transmit buffer is used
to hold the 8-bit data & output register is used to convert parallel data into serial data. If output register is
empty, then the data is transferred from buffer register to output register.
 If buffer register is empty, then TXRDY signal is asserted high. If output register is empty, then TXEMPTY
signal is asserted high.
 TXC signal is used to control the rate of transmission.
Receiver Section
 This section receives serial data from the signal RXD and converts that data into parallel data. It consists of
2 registers namely input register & buffer register.
 Input register receives the serial data & convert it into parallel. Buffer register is used to hold the previous
converted data. If input register loads parallel data into buffer register, then, the RXRDY signal is asserted
high.
 If RXD signal is low for a half of bit time, then it is assumed as start bit. So, following bits are loaded into
the buffer register.
 If RXC signal is used to control the rate of reception.
 During synchronous mode, the signal SYNDET/BRKDET is used to indicate the reception of synchronous
character.
 During asynchronous mode, SYNDET/BRKDET signal is used to indicate the break in the data
transmission.
Pin Description:
D 0 to D7 ( Data bus Buffer)
 This is bidirectional data bus which receives control word and transmits data from the CPU and sends
status words and received data to CPU.
RESET (Input te rminal)
 A "High" on this input forces the 8251 into "reset status." The device waits for the writing of "mode
instruction."
CLK (Input terminal)
 CLK signal is used to generate internal device timing. CLK signal is independent of RxC or TxC.
WR ( Write)
 This is the "active low" input terminal which receives a signal for writing transmit data and control words
from the CPU into the 8251.
RD (Read)
 This is the "active low" input terminal which receives a signal for reading receive data and status words
from the 8251.
C/D ( Control/Data)
 If C/D = low, data will be accessed. If C/D = high, command word or status word will be accessed.
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CS ( Chip Select)
 This is the "active low" input terminal which selects the 8251 at low le vel when the CPU accesses.

SYNDET/BD (Input or output terminal)

 This is a terminal whose function changes according to mode. In "internal synchronous mode." this
terminal is at high level, if sync characters are received and synchronized.
 DSR ( Data set ready)
This is an input port for MODEM interface. This is normally used to check if the Data set is ready when
communicating with a modem.
 DTR ( Data terminal ready)
This is an output port for MODEM interface. It is used to indicate that the device is ready to accept data
when the 8251 is communicating with a modem.
 CTS (clear to send)
This is an input terminal for MODEM interface which is used for controlling a transmit circuit. Data is
transmittable if the terminal is at low level.
 RTS ( Request to send data)
This is an output port for MODEM interface. It is used to indicate the MODEM that the receiver is
ready to receive a data byte from the MODEM.

Control Register
The 16 bit register for a control word consists of two independent bytes. The first byte is called the mode
instruction and the second byte is called the command instruction. This register can be accessed as an output
port when the C/D pin is high.
Status Register
This input register checks the ready status of a peripheral. This register is addressed as an input port when the
C /D is high. It has the same port address as the control register.

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 4. Draw the block diagram of 8279 Keyboard/Display controller and explain how to inte rface the
Hex Key Pad and 7-segment LEDs using 8279. (April 2010)
 It simultaneously drives the display of a system and interfaces a keyboard with the microprocessor.
 The keyboard display interface scans the keyboard to identify if any keys has been pressed and
sends the code of the pressed key to the microprocessor.
 It also transmits the data received from microprocessor to the display device.
PIN DIAGRAM OF 8279:
DATA BUS (D7-D0)
 All data and commands between the microprocessor and 8279 are transmitted on these lines.
RD (read):
 Microprocessor reads the data/ status from 8279.
WR (write):
 Microprocessor writes the data to 8279
A0:
 A high signal on this line indicates that the word is a command or status. A low signal indicates the
data.
RESET:
 High signal in this pin resets the 8279. After being reset, the 8279 is placed in the following modes
16 x 8 – bit character display – left entry
 Two key lock out

CS (Chip Select):
 A low signal on this input pin enables the communication between 8279 and the microprocessor.
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 IRQ (Interrupt Request):
 The interrupt line goes low with each FIFO/sensor RAM reads and returns high if there still
information in the RAM
SL0-SL3:
 The scan lines which are used to scan the key switc h or sensor matrix and the displays digits. These
lines can be either encoded (1 of 16) or decoded (1 of 4)
RL0-RL7:
 Input return lines which are connected to the scan lines through the keys or sensor switches.
SHIFT:
 It has an active internal pull- up to keep it high until a switch closure pulls it low.
CNTL/STB:
 For keyboard mode, this line is used as a control input and stored like status on a key closure.
 The line is also the strobed line to enter the data into the FIFO in the strobed input.
OUT A0 – OUT A3, OUT B0 – OUT B3:
 These two ports are the outputs for the 16x4 display refresh registers. These two ports may also be
considered as one 8 – bit port. The two 4 – bit ports may be blanked independently.
BD:
 This output is used to blank the display digit switching or by a display banking command.
BLOCK DIAGRAM OF 8279:
The 8279 has the following four sections.
 CPU interface section
 Keyboard section
 Scan section
 Display section
CPU INTERFACE SECTION:
 This section has bi-directional data buffer (DB0 –DB7), I/O control lines (RD, WR, CS, A0) and
Interrupt Request lines (IRQ).
 The A0 signal determines whether transmit/receive control word or data is used.
An active high in line IRQ is generated to interrupt the microprocessor whenever the data is available.
A0 RD WR Operation
0 0 0 MPU writes the data is 8279
0 0 1 MPU reads the data from 8279
1 1 0 MPU writes control word to 8279
1 0 1 MPU read status word from 8279

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KEYBOARD SECTION:
 This section has keyboard debounce & control, 8X8 FIFO/sensor RAM, 8 return lines (RL0 –
RL7) and CNTL/STB and shift lines.
 In the keyboard debounce and control unit, keys are automatically debounced and the keyboard
can be operated in two modes.
o Two keys lock out
o N – key roll over
Two-Key lockout mode:
 If two keys are depressed within the debounce cycle, it is a simultaneous depression. Neither key
will be recognized until one of the key is released. The final key released will be recognized and
entered.
N-Key Rollover mode:
 In this mode, each key depression is treated independently. If simultaneous depression occurs, then
keys are recognized and entered according to the order the keyboard scan found them.
 The 8X8 FIFO/sensor RAM consists of 8 registers that are used to store eight keyboard entries.
 The return lines (RL0-RL7) are connected to eight columns of keyboard.
 The status of shift and CNTL/STB lines are stored along with the key closure.
SCAN SECTION:
 This section has scan counter and four scan lines (SL0 – SL3).

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  These lines are decoded (by using 4 to 16 decoder) to generate 16 scan lines.
 Generally SL0 – SL3 are connected with the rows of a matrix keyboard.
DISPLAY SECTION:
 This section has two groups of outputs lines A0 – A3 and B0 – B3. These lines are used to send
data to display drivers.
 BD line is used blank the display. It also has 16X8 displays RAM.
Modes of operations of 8279

1. Input (Keyboard) modes

2. Output (Display) modes
Keyboard modes
 Scanned keyboard mode with N key rollover
In this mode, each key depression is treated independently. When a key is pressed, the debounce
circuit waits for 2 keyboards scans and then checks whether the key is still depressed. If it is still depressed,
the code is entered in FIFO RAM
 Scanned keyboard mode with 2 key lock out.
It Prevents 2 keys from being recognized if pressed simultaneously. If two keys are pressed within a
debounce cycle (simultaneously), no key is recognized till one of them remains closed, and the other is
released. The last key that remains depressed is considered as single valid key depression.

Display modes:
Left entry mode
The data is entered from the left side of the display unit.
Right entry mode
The first entry to be displayed is entered on the rightmost display.

Programming the Keyboard Inte rface :

 Before any keystroke is detected, the 8279 must be programmed.

 The first 3 bits of the number sent to the control port (11H) select
one of the 8 different control words.
Command Words of 8279

a) Keyboard Dis play mode set

The format of the command word is to select different modes of operation of 8279

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Control Word Description

First three bits given below select one of 8 control registers (opcode)

 000DDMMM
Mode set: Opcode 000.
DD sets displays mode.
MMM sets keyboard mode
DD field selects either:
• 8- or 16-digit display
• Whether new data are entered to the rightmost or leftmost display position.
b)Programmable clock
The clock for operation of 8279 is obtained by dividing the external clock input signal by a programmable
constant called prescaler.
 001PPPPP
• The clock command word programs the internal clock driver.
• The code PPPPP, is a prescalar that divides the clock input pin (CLK) to achieve the desired
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 • operating frequency, e.g. 100 KHz requires 010102 .

(c)Read FIFO/Sensor RAM

 010 AI X AAA
The read FIFO control word selects the address (AAA) of a keystroke from the FIFO buffer (000 to 111).
X - don‘t care
AI selects auto- increment for the address
d) Read Display RAM
This command enables a programmer to read the display RAM data.
 011 AI AAAA
The display read control word selects the 4 bit address AAAA points to the 16 byte display RAM position
that is to be read.
AI selects auto- increment for the address.
e) Write Display RAM
 100 AI AAAA
The display write control word selects the 4 bit address AAAA points to the 16 byte display RAM
positions that is to be written.
Display. Z selects auto- increment so subsequent writes go to subsequent display positions.

f)Display with inhibit blanking

 1010WWBB
The display write inhibit control word inhibits writing to either the leftmost 4 bits of the display (left W) or
rightmost 4 bits (right W).
BB works similarly except that they blank (turn off) half of the output pins.
g) Clear Display RAM
 1100CCFA
The clear control word clears the display, FIFO or both
Bit F clears FIFO and the display RAM status, and sets address pointer to 000.
If CC are 00 or 01, all display RAM locations become 00000000.
If CC is 10, --> 00100000, if CC is 11, --> 11111111.
h) End Interrupt/Error mode set
 1110E000
End of Interrupt control word is issued to clear IRQ pin to zero in sensor matrix mode
• Clock must be programmed first. If 3.0 MHz drives CLK input, PPPPP is programmed to 30 or
111102 .
• Keyboard type is programmed next. The previous example illustrates an encoded keyboard, external
decoder used to drive matrix.
• Program the operation of the FIFO.Once programmed never reprogrammed done, until a procedure is
needed to read prior keyboard codes .
To determine if a character has been typed, the FIFO status register is checked.

When the control port is addressed by the IN instruction, the contents of the FIFO status word is copied into
register AL:

5.Draw the functional block diagram of 8254 time r and explain the different modes of operation.
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 (April 2010)(Nov/Dec-2013)
Programmable Interval Time r: 8254

The 8254 is a programmable interval timer/counter is used for the generation of accurate time
delays ,controlling real-time events such as real-time clock, events counter, and motor speed and
direction control under software control.
After the desired delay, the 8254 will interrupt the CPU. This makes microprocessor to be free
the tasks related to the counting process and can execute the programs in memory, while the timer
device may perform the counting tasks. This minimize the Software overhead on the microprocessor.
It consists of three independent 16-bit programmable counters (timers),each with capable of
counting in binary or BCD with a maximum frequency of 10MHz.

Some of the other counter/timer functions common to microcomputers which can be

implemented with the 8254 are:

• Real time clock

• Event-counter
• Digital one-shot
• Programmable rate generator
• Square wave generator
• Binary rate multiplier
PIN DIAGRAM OF 8254:

PIN DESCRIPTION:
A1 A2 SELECTION
0 0 Counter 0
0 1 Counter 1

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 1 0 Counter 2
1 1 Counter 3

BLOCK DIAGRAM OF 8254:

DATA BUS BUFFER:
 This 3- state, bi-directional, 8-bit buffer is used to interface the 8254 to the system bus.
READ/WRITE LOGIC:
 The Read/Write logic accepts inputs from the system bus and generates control signals for the
other functional blocks of the 8254.
 A1 and A0 select one of the three contents counters or the control word register to be read
from/written into.
 A ―low‖ on the RD input tells the 8254 that the CPU is reading one of the counters.
 A ―low‖ on the WR input tells the 8254 that the CPU is writing either a control word or an initial
count.
 Both RD and WR are qualified by CS; RD and WR are ignored unless than 8254 has been selected
by holding CS low.

CONTROL WORD REGISTER:

 The control word register is selected by the read/write logic when A1, A0=11.
 If the CPU then does a write operation to the 8254, the data is stored in the control word register
and is interpreted as a control word used to define the operation of the counters.
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 The control word register can only be written to; status information is available with the
Read-Back command.
COUNTER 0, COUNTER 1, COUNTER 2:
 Each is a 16 bit down counter
 The counters are fully independent. Each counter may operate in a different mode.
 Each counter has a separate clock input, count enable (gate) input lines and output lines.
 The control word register is not a part of the counter itself, but its contents determine how the
counter operates.
OPERATIONAL MODES OF 8254:
 The 8254 can operate in six operating modes. They are,
Mode 0: Interrupt on Terminal count:
 Mode 0 is typically used for event countering.
 After the control word is written OUT is initially low, and will remain low until the counter
reaches zero.
 OUT then goes high and remains high until a new count or a new mode 0 control word is written
into the counter.
o GATE = 1 enables counting;
o GATE = 0 disables counting. GATE has no effect on OUT.
 After the control word and initial count (say n=4, m=5) are written to a counter, the initial count
will be loaded on the next CLK pulse.
 This CLK pulse does not decrement the count. So far an initial count of N, OUT does not go high
until N+1 CLK pulses after the initial count is written.
 This mode can be used as an interrupt.

Mode 1 – Hardware Retriggerable one-shot:

 OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the
one-shot pulse, and will remain low until the counter reaches zero.
 OUT will then go high and remain high until the CLK pulse after the next trigger. Thus generating
a one- shot pulse.

26 Dr.S.SIVASAKTHISELVAN / ECE
 After writing the control word and initial count, the counter is armed. A trigger results in loading
the counter and setting OUT low on the next CLK pulse, the starting the one-shot pulse.
 An initial count of N will result is a one-shot pulse ‗N‘ CLK cycles in duration.

Mode 2: Rate generator

 This mode function like a device – by – N counter
 It is typically used to generate a real time clock interrupt.
 OUT will initially be high. When the initial count has decremented to 1, OUT goes low for one
CLK pulse.
 Count and the process are repeated.

 Mode 3: Square wave mode:

 Mode 3 is typically used for baud rate generation.
 Mode 3 is similar to mode 2 except for the duty cycle of OUT, OUT will initially be high.
 When half the initial count has expired, OUT goes low for the reminder of the count.
 Mode 3 is periodic; the sequence above is repeated indefinitely.
 An initial count of N results in a square wave with a period of N CLK cycles.
 Mode 3 is implemented as follows:

EVEN COUNTS:
27 Dr.S.SIVASAKTHISELVAN / ECE
 OUT is initially high. The initial count is loaded on 1 CLK pulse and then is decremented by two
on succeeding CLK pulses.
 When the count expires OUT changes value and the counter is reloaded with the initial count.
 The above process is repeated indefinitely.
ODD COUNTS:
 For odd counts, OUT will be high for (N+1)/2 counts and low for (N-1)/2 counts.

Mode 4: Software triggered Strobe

 The output goes high on setting the mode.
 After terminal count, the output goes low for one clock period and then goes high again.
 In this mode the OUT is initially high; it goes low for clock period at the end of the count.
 The count must be reloaded for subsequent outputs.

Mode 5: hardware triggered strobe

 This mode is similar to mode 4, but a trigger at the gate initiates the counting.
 This mode is similar to mode 4, except that it is triggered by the rising pulse a t the gate.
 Initially the OUT is high and when the gate pulse is triggered from low to high, the count begins,
at the end of the count; the OUT goes low for one clock period.

28 Dr.S.SIVASAKTHISELVAN / ECE
Command word of 8254

Each counter may be programmed with a count of 1 to FFFFH. Minimum count is 1 all modes
except 2 and 3 with minimum count of 2.Each counter has a program control word used to select the way
the counter operates. If two bytes are programmed, then the first byte (LSB) stops the count, and the
second byte (MSB) starts the counter with the new count.

29 Dr.S.SIVASAKTHISELVAN / ECE
6.Discuss in detail about Programming and interfacing 8253
There may be two types of write operations in 8253

i) Writing control word into a control word register

ii) Writing a count value into a count register.
iii) The control word register accepts data from the data buffer and initializes the counter as
required.
iv) The control word register contents are used for
a) Initializing operating modes(Mode 0 to Mode 4)
b) Selection of counters (Counter0 to counter3)
c) Choosing binary/BCD counters
d) Loading the counter register

Read Operations

There are three possible methods for reading the counters:

• a simple read operation
• the Counter Latch Command
• the Read-Back Command
Simple read operation :
• The Counter which is selected with the A1, A0 inputs, the CLK input of the selected Counter
must be inhibited by using either the GATE input or external logic. Otherwise, the count may be in
the process of changing when it is read, giving an undefined result

Counter Latch Command:

• SC0, SC1 bits select one of the three Counters

• Two other bits, D5 and D4, distinguish this command from a Control Word

If a Counter is latched and then, sometime later, latched again before the count is read, the second
Counter Latch Command is ignored. The count read will be the count at the time the first Counter Latch
Command was issued.

30 Dr.S.SIVASAKTHISELVAN / ECE
Read-back control command

• The read-back control, word is used when it is necessary for the contents of more than one counter to
be read at a same time.

• Count : logic 0, select one of the Counter to be latched

• Status : logic 0, Status must be latched to be read status of a counter is accessed by a read from that
counter

Status register:

• shows the state of the output pin

• check the counter is in NULL state (0) or not
• how the counter is programmed

31 Dr.S.SIVASAKTHISELVAN / ECE
*************************************************************************

7. Explain in detail about Direct Memory Access (DMA Controller 8257)

Direct memory access (DMA) or DMA mode of data transfer is the fastest amongst all the modes of data
transfer. In this mode, the device may transfer data directly to/from memory without any interference from
the CPU.

THE DMA controller (8257) allows certain hardware subsystems to read/write data to/from memory
without microprocessor intervention, allowing the processor to do other work.

The device requests the CPU (through a DMA controller) to hold its data, address and control bus, so that
the device may transfer data directly to/from memory. The DMA data transfer is initiated only after
receiving HLDA signal from the CPU. For facilitating DMA type of data transfer between several devices,
a DMA controller may be used.

It is used in disk controllers, video/sound cards etc, or between memory locations. Typically, the CPU
initiates DMA transfer, does other operations while the transfer is in progress, and receives an interrupt
from the DMA controller once the operation is complete.

It contains Five main Blocks.

1. Data bus buffe r

2. Read/Control logic

3. Control logic block

4. Priority resolver

5. DMA channels.

32 Dr.S.SIVASAKTHISELVAN / ECE
Pin diagram of 8257:

Block diagram of 8257:

DATA BUS BUFFER:

33 Dr.S.SIVASAKTHISELVAN / ECE
  It contains tri-state, 8 bit bi-directional buffer.
 Slave mode, it transfers data between microprocessor and internal data bus.
 Master mode, the outputs A8-A15 bits of memory address on data lines (Unidirectional).

READ/CONTROL LOGIC:
 It controls all internal Read/Write operation.
 Slave mode ,it accepts address bits and control signal from microprocessor.
 Master mode, it generates address bits and control signal.
Control logic block:
It contains ,
1. Control logic
2. Mode set register and
3. Status Register.
CONTROL LOGIC:

Master mode,
It control the sequence of DMA operation during all DMA cycles.

 It generates address and control signals.

 It increments 16 bit address and decrement 14 bit counter registers.

 It activate a HRQ signal on DMA channel Request.

Slave mode it is disabled.

D 0 –D7

 it is a bidirectional ,tri state ,Buffered ,Multiplexed data (D0-D7)and (A8-A15).

 In the slave mode it is a bidirectional (Data is moving).

In the Master mode it is a unidirectional (Address is moving)

IOR

 It is active low, tri-state, buffered, Bidirectional lines.

 In the slave mode it function as a input line. IOR signal is generated by microprocessor to read
the contents 8257 registers.
 In the master mode it function as a output line. IOR signal is generated by 8257 during write
cycle
IOW
 It is active low, tri-state ,buffered ,Bidirectional control lines.
 In the slave mode it function as a input line. IOR signal is generated by microprocessor to write
the contents 8257 registers.

 In the master mode it function as a output line. IOR signal is generated by 8257 during read
cycle

CLK:
 It is the input line, connected with TTL clock generator.

34 Dr.S.SIVASAKTHISELVAN / ECE
  This signal is ignored in slave mode.
RESET:
 Used to clear mode set registers and status registers
A0-A3:
These are the tri-state, buffer, bidirectional address lines.
In slave mode, these lines are used as address inputs lines and internally decoded to access the internal
registers.
In master mode, these lines are used as address outputs lines, A0-A3 bits of memory address on the lines.
 It is active low, Chip select input line.
 In the slave mode, it is used to select the chip.
 In the master mode, it is ignored.
A4-A7:

These are the tristate, buffer, output address lines.

In slave mode ,these lines are used as address input lines.
In master mode, these lines are used as address outputs lines, A0-A3 bits of memory address on the lines.

READY:
 It is an asynchronous input line.
 In master mode,
When ready is high it receives the signal.
When ready is low, it adds wait state between S1 and S3

 In slave mode, this signal is ignored.

HRQ:
It is used to receiving the hold request signal from the output device.
HLDA:
 It is acknowledgment signal from microprocessor.

MEMR:
 It is active low, tristate, Buffered control output line.
 In slave mode, it is tristated.
 In master mode, it activated during DMA read cycle.
MEMW:
 It is active low, tristate, Buffered control input line.
 In slave mode, it is tristated.
 In master mode, it activated during DMA write cycle.
AEN (Address enable):
 It is a control output line.
 In master mode ,it is high
 In slave mode ,it is low
 Used it isolate the system address, data, and control lines.
ADSTB: (Address Strobe)
 It is a control output line.
 Used to split data and address line.
 It is working in master mode only.
 In slave mode it is ignore.
TC (Terminal Count):
 It is a status of output line.
 It is activated in master mode only.
 It is high, it selected the peripheral.
35 Dr.S.SIVASAKTHISELVAN / ECE
 It is low, it is free and looking for a new peripheral.
MARK:
 It is a modulo 128 MARK output line.
 It is activated in master mode only.
 It goes high, after transferring every 128 bytes of data block.

DMA controller

 A DMA controller is capable of becoming the bus master and supervising a transfer between an I/O
or mass storage interface and memory. While making a transfer, it must be able to place memory
address on the bus and send and receive handshaking signals in a manner similar to that of the bus
control logic. The purpose of a DMA controller is to perform a sequence of transfers (ie a block
transfer) by stealing bus cycles.
 A DMA controller is designed to service one or more I/O mass storage interfaces, and each
interface is connected to the controller by a set of conductors. A portion of a DMA controller for
servicing a single interface is called a channel.
 The general organization of a one channel DMA controller and its principal connection is shown in
figure. In addition to the usual control and status registers, each channel must contain an address
register and a byte (or word) count register.
 Initializing the controller consists of filling these registers with the beginning (or ending) address
of the memory array that is to be used as a buffer and the number of bytes (words) to be transferred
.For an input to memory, each time the interface has data to transfer it makes a DMA request. The
controller then makes a bus request and when it receives a bus grant, it puts the contents of the
address register on the address bus, sends an acknowledgement back to the interface, and issues I/O
read and memory write signals. The interface then puts the data on the data bus and drops its
request. When the memory accepts the data it returns a ready signal to the controller, which then
increments (or decrements) the address register, decrements the byte (word) count, and drops its bus
request.
 Upon the count reaching zero, the process stops and a signal is sent to the processor as an interrupt
request or to the interface to notify it that the transfers have terminated. An output is similarly
executed except that the controller issues I/O write and memory read signals and the data are
transferred in the other direction.

DRQ0-DRQ3 (DMA Request):

 These are the asynchronous peripheral request input signal.

 The request signals are generated by external peripheral device.

DACK0-DACK3:

 These are the active low DMA acknowledge output lines.

 Low level indicate that, peripheral is selected for giving the information (DMA cycle).

In master mode it is used for chip select

36 Dr.S.SIVASAKTHISELVAN / ECE
 HLDA becomes active to indicate the processor has placed its buses at high- impedance state as can be seen
in the timing diagram, there are a few clock cycles between the time that HOLD changes and until HLDA
changes
HLDA output is a signal to the requesting device that the processor has relinquished control of its memory
and I/O space one could call HOLD input a DMA request input and HLDA output a DMA grant signal

 Steps in a DMA operation

 Processor initiates the DMA controller gives device number, memory buffer pointer, called channel
initialization
 Once initialized, it is ready for data transfer.
 When ready, I/O device informs the DMA controller .DMA controller starts the data transfer process
 Obtains bus by going through bus arbitration
 Places memory address and appropriate control signals
 Completes transfer and releases the bus
 Updates memory address and count value
 If more to read, loops back to repeat the process
 Notify the processor when done typically uses an interrupt

Modes of DMA operation

Each channel may be put in one of four modes, with its current mode being determined by bits 7 and6 of
the channel‘s mode register. The four possible modes are

Single transfer mode (01)

After each transfer the controller will release the bus to the processor for at least one b y cycle, but will
immediately begin testing for DREQ inputs and proceed to steal another cycle as soon as a DREQ line
becomes active.

Block transfer mode (10)

DREQ need only be active until DACK becomes active, after which the bus is not released until the entire
block of data has been transferred.

37 Dr.S.SIVASAKTHISELVAN / ECE
Demand Transfer mode(00)
This is similar to the block mode except that DREQ is tested after each transfer. If DREQ is inactive,
transfers are suspended until DREQ once again becomes active, at which time the block transfer continues
from the point at which it was suspended. This allows the interface to stop the transfer in the event that its
device cannot keep up.

Cascade Mode (11)

In this mode 8237s may be cascaded so that more than four channels can be included in the DMA
subsystem. In cascading the controllers, those in the second level are connected to those in the first level by
joining HRQ to DREQ and HLDA to DACK, To conserve space, this mode will not be considered further.

In this mode
Single-cycle mode: DMA data transfer is done one byte at a time

Burst-mode: DMA transfer is finished when all data has been moved

a) Byte b) Burst c) Block

8. Write in detail about Analog to digital conversion (ADC)

•The process of analog to digital conversion is a slow process, and the microprocessor has to wait for the
digital data till the conversion is over. After the conversion is over, the ADC sends end of conversion
EOC signal to inform the microprocessor that the conversion is over and the result is ready at the output

38 Dr.S.SIVASAKTHISELVAN / ECE
 buffer of the ADC. These tasks of issuing an SOC pulse to ADC, reading EOC signal from the ADC and
reading the digital output of the ADC are carried out by the CPU using 8255 I/O ports.
•The time taken by the ADC from the active edge of SOC pulse till the active edge of EOC signal is called
as the conversion delay of the ADC.
• It may range anywhere from a few microseconds in case of fast ADC to even a few hundred milliseconds
in case of slow ADCs.
•The available ADC in the market use different conversion techniques for conversion of analog signal to
digitals. Successive approximation techniques and dual slope integration techniques are the most
popular techniques used in the integrated ADC chip.

General algorithm for ADC interfacing contains the following steps:

1. Ensure the stability of analog input, applied to the ADC.
2. Issue start of conversion (SOC) pulse to ADC
3. Read end of conversion signal to mark the end of conversion processes.
4. Read digital data output of the ADC as equivalent digital output.

• Analog input voltage must be constant at the inp ut of the ADC right from the start of conversion till
the end of the conversion to get correct results. This may be ensured by a sample and hold circuit
which samples the analog signal and holds it constant for specific time duration.
• The microprocessor may issue a hold signal to the sample and hold circuit. If the applied input
changes before the complete conversion process is over, the digital equivalent of the analog input
calculated by the ADC may not be correct.

ADC 0808/0809 :
• The analog to digital converter chips 0808 and 0809 are 8-bit CMOS, successive approximation
converters. This technique is one of the fast techniques for analog to digital conversion.

39 Dr.S.SIVASAKTHISELVAN / ECE
 • The conversion delay is 100μs at a clock frequency of 640 KHz, which is quite low as compared to
other converters. These converters do not need any external zero or full scale adjustments as they
are already taken care of by internal circuits.
• These converters internally have a 3:8 analog multiplexer so that at a time eight different analog
conversion by using address lines
• ADD A, ADD B, ADD C. Using these address inputs, multichannel data acquisition system can be
designed using a single ADC. The CPU may drive these lines using output port lines in case of
multichannel applications. In case of single input applications, these may be hardwired to select the
proper input.
• There are unipolar analog to digital converters, i.e. they are able to convert only positive analog
input voltage to their digital equivalent. These chips do not contain any internal sample and hold
circuit.If one needs a sample and hold circuit for the conversion of fast signal into equivalent digital
quantities, it has to be externally connected at each of the analog inputs.

• Vcc Supply pins +5V

• GND GND
• Vref + Reference voltage positive +5 Volts maximum.
• Vref_ Reference voltage negative 0Volts sminimum
 I/P0–I/P7 Analog inputs
• ADD A,B,C Address lines for selecting analog inputs.
• O7 – O0 Digital 8-bit output with O7 MSB and O0 LSB
• SOC Start of conversion signal pin
• EOC End of conversion signal pin
• OE Output latch enable pin, if high enables output
• CLK Clock input for ADC

40 Dr.S.SIVASAKTHISELVAN / ECE
Example: Interfacing ADC 0808 with 8086 using 8255 ports. Use port A of 8255 for transferring digital
data output of ADC to the CPU and port C for control signals. Assume that an analog input is present at
I/P2 of the ADC and a clock input of suitable frequency is available for ADC.

• Solution: The analog input I/P2 is used and therefore address pins A,B,C should be 0,1,0 respectively to
select I/P2. The OE and ALE pins are already kept at +5V to select the ADC and enable the outputs. Port C
upper acts as the input port to receive the EOC signal while port C
lower acts as the output port to send SOC to the ADC.

Port A acts as a 8-bit input data port to receive the digital data output from the ADC. The 8255 control
word is written as follows:
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 1 0 0 0

• The required ALP is as follows:

MOV AL, 98h ;initialise 8255 as
OUT CWR, AL ;discussed above.
MOV AL, 02h ;Select I/P2 as analog
OUT Port B, AL ;input.

MOV AL, 00h ;Give start of conversion

OUT Port C, AL ; pulse to the ADC
MOV AL, 01h
OUT Port C, AL
MOV AL, 00h
OUT Port C, AL
WAIT: IN AL, Port C ;Check for EOC by
RCR ; reading port C upper and
JNC WAIT ;rotating through carry.
IN AL, Port A ;If EOC, read digital equivalent
;in AL
HLT ;Stop

41 Dr.S.SIVASAKTHISELVAN / ECE
*************************************************************************

9. Explain in detail about Interfacing Digital to Analog Converters

• The digital to analog converters convert binary number into their equivalent voltages. The DAC
find applications in areas like digitally controlled gains, motors speed controls, programmable gain
amplifiers etc.
• AD7523 8-bit Multiplying DAC : This is a 16 pin DIP, multiplying digital to analog converter,
containing R-2R ladder for D-A conversion along with single pole double thrown NMOS switches
to connect the digital inputs to the ladder.

• The pin diagram of AD7523 is shown in fig the supply range is from +5V to +15V, while Vref may
be any where between -10V to +10V. The maximum analog output voltage will be any where
between -10V to +10V, when all the digital inputs are at logic high state.
• Usually a zener is connected between OUT1 and OUT2 to save the DAC from negative transients.
An operational amplifier is used as a current to voltage converter at the output of AD to convert the
current output of AD to a proportional output voltage.
It also offers additional drive capability to the DAC output.An external feedback resistor acts to
control the gain. One may not connect any external feedback resistor, if no gain control is required.
• EXAMPLE: Interfacing DAC AD7523 with an 8086 CPU running at 8MHZ and write an assembly
language program to generate a saw tooth waveform of period 1ms with Vmax 5V.
• Solution: Fig shows the interfacing circuit of AD 74523 with 8086 using 8255. program gives an

ALP to generate a saw tooth waveform using circuit.

ASSUME CS:CODE
CODE SEGMENT
START: MOV AL,80h ;make all ports output
OUT CW, AL
42 Dr.S.SIVASAKTHISELVAN / ECE
AGAIN: MOV AL,00h ;start voltage for ramp
BACK : OUT PA, AL
INC AL
CMP AL, 0FFh
JB BACK
JMP AGAIN
CODE ENDS
END START

• In the above program, port A is initialized as the output port for sending the digital data as input to
DAC. The ramp starts from the 0V (analog), hence AL starts with 00H. To increment the ramp, the
content of AL is increased during each execution of loop till it reaches F2H.
• After that the saw tooth wave again starts from 00H, i.e. 0V (analog) and the procedure is repeated.
The ramp period given by this program is precisely 1.000625 ms. Here the count F2H has been
calculated by dividing the required delay of 1ms by the time required for the execution of the
loop once. The ramp slope can be controlled by calling a controllable delay after the OUT
instruction

***************************************************************

10. Draw the block diagram of 8259A and explain how to program 8259A (April 2010).
Programmable Interrupt controlle r (8259)

Introduction:

For applications where we have interrupts from multiple source, we use an external device called a
priority interrupt controller ( PIC ) to the interrupt signals into a single interrupt input on the processor.
It accepts requests from the peripheral equipment, determines which of the incoming requests is of
the highest importance (priority), ascertains whether the incoming request has a higher priority value than
the level currently being serviced, and issues an interrupt to the CPU based on this determination.

43 Dr.S.SIVASAKTHISELVAN / ECE
Inte rrupt Request Register (IRR): The interrupts at IRQ input lines are handled by Interrupt Request
internally. IRR stores all the interrupt request in it in order to serve them one by one on the priority basis.
• In-Service Register (ISR): This stores all the interrupt requests those are being served, i.e. ISR keeps a
track of the requests being served.

Priority Resolver : This unit determines the priorities of the interrupt requests appearing simultaneously.
The highest priority is selected and stored into the corresponding bit of ISR during INTA pulse. The IR0
has the highest priority while the IR7 has the lowe st one, normally in fixed priority mode. The priorities
however may be altered by programming the 8259A in rotating priority mode.
• Inte rrupt Mask Register (IMR) : This register stores the bits required to mask the interrupt inputs. IMR
operates on IRR at the direction of the Priority Resolver.

• Interrupt Control Logic: This block manages the interrupt and interrupt acknowledge signals to be sent
to the CPU for serving one of the eight interrupt requests. This also accepts the interrupt acknowledge
(INTA) signal from CPU that causes the 8259A to release vector address on to the data bus.
• Data Bus Buffer : This tristate bidirectional buffer interfaces internal 8259A bus to the microprocessor
system data bus. Control words, status and vector information pass through data buffer during read or write
operations.
• Read/Write Control Logic: This circuit accepts and decodes commands from the CPU. This block also
allows the status of the 8259A to be transferred on to the data bus.
• Cascade Buffer/Comparator: This block stores and compares the ID‘s all the 8259A used in system.
The three I/O pins CASO-2 are outputs when the 8259A is used as a master. The same pins act as inputs
when the 8259A is in slave mode. The 8259A in master mode sends the ID of the interrupting slave device
on these lines. The slave thus selected, will send its preprogrammed vector address on the data bus during
the next INTA pulse.
• CS: This is an active- low chip select signal for enabling RD and WR operations of 8259A. INTA
function is independent of CS.
• WR: This pin is an active- low write enable input to 8259A. This enables it to accept command words
from CPU.
• RD: This is an active-low read enable input to 8259A. A low on this line enables 8259A to release status
onto the data bus of CPU.
• D0-D7 : These pins from a bidirectional data bus that carries 8-bit data either to control word or from
status word registers. This also carries interrupt vector information.
• CAS0 – CAS2 Cascade Lines: A signal 8259A provides eight vectored interrupts. If more interrupts are
required, the 8259A is used in cascade mode. In cascade mode, a master 8259A along with eight slaves
8259A can provide up to 64 vectored interrupt lines. These three lines act as select lines for addressing the
slave 8259A.
• PS/EN : This pin is a dual purpose pin. When the chip is used in buffered mode, it can be used as
buffered enable to control buffer transreceivers. If this is not used in buffered mode then the pin is used as
input to designate whether the chip is used as a master (SP =1) or slave (SP = 0).
• INT : This pin goes high whenever a valid interrupt request is asserted. This is used to interrupt the CPU
and is connected to the interrupt input of CPU.

44 Dr.S.SIVASAKTHISELVAN / ECE
• IR0 – IR7 (Interrupt requests) :These pins act as inputs to accept interrupt request to the CPU. In edge
triggered mode, an interrupt service is requested by raising an IR pin from a low to a high state and holding
it high until it is acknowledged, and just by latching it to high level, if used in level triggered mode.

A0
This input signal is used in conjunction with WR and RD signals to write commands into the various
command registers, as well as reading the various status registers of the chip. This line can be tied directly
to one of the address lines.

Inte rrupt Sequence in an 8086 system

The Interrupt sequence in an 8086-8259A system is described as follows:

1. One or more IR lines are raised high that set corresponding IRR bits.
2. 8259A resolves priority and sends an INT signal to CPU.
3. The CPU acknowledge with INTA pulse.
4. Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set and the corresponding
IRR bit is reset. The 8259 will also release a CALL instruction code (11001101 ) on to the 8 bit data bs
through its D7 D0 pins.
5. The CALL instruction will initiate a second INTA pulse. During this period 8259A releases an 8-bit
pointer on to a data bus from two more INTA pulses to be sent to the 8259 from the CPU group.

45 Dr.S.SIVASAKTHISELVAN / ECE
6.These two INTA pulses allow the 8259 to release its pro grammed subroutine address onto the data bits.
The lower 8 bit address is released at the first INTA pulse and the higher 8 bit address is released at the
second INTA pulse.
6. This completes the 3 byte CALL instruction released by the 8259. interrupt cycle. The ISR bit is reset at
the end of the second INTA pulse if automatic end of interrupt (AEOI) mode is programmed. Otherwise ISR
bit remains set until an appropriate EOI command is issued at the end of interrupt subroutine.

Command Words of 8259A

The 8259A accepts two types of command words generated by the CPU:

1. Initialization Command Words (ICWs):

Before normal operation can begin, each 8259A in the system must be brought to a starting pointed
by a sequence of 2 to 4 bytes timed by WR pulses.

2. Ope rational Command Words (OCWs):

These are the command words which command the 8259A to operate in various interrupt modes.
These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A anytime after initialization.

INITIALIZATION COMMAND WORDS (ICWS)

Initialization Command Words (ICW): Before it starts functioning, the 8259A must be initialized by
writing two to four command words into the respective command word registe rs. These are called as
initialized command words.
• If A0 = 0 and D4 = 1, the control word is recognized as ICW1. It contains the control bits for edge/level
triggered mode, single/cascade mode, call address interval and whether ICW4 is required or not.
• If A0=1, the control word is recognized as ICW2. The ICW2 stores details regarding interrupt vector
addresses. The initialization sequence of 8259A is described in form of a flow chart in fig 3 below.
• The bit functions of the ICW1 and ICW2 are self explanatory as shown in fig below.

46 Dr.S.SIVASAKTHISELVAN / ECE
ICW1 :
A write command issued to the 8259 with A0 =0 and D4 =1 is interpreted as ICW1,which starts the
initialization sequence It specifies
1.Single or Multiple 8259 s in the system
2.4 or 8 bit,interval between interrupt vector locations
3. The address bits A7 A5 of the CALL instruction
4. Edge triggered or Level triggered interrupts
5. ICW4 is needed or not

47 Dr.S.SIVASAKTHISELVAN / ECE
Once ICW1 is loaded, the following initialization procedure is carried out internally.
a. The edge sense circuit is reset, i.e. by default 8259A interrupts are edge sensitive.
b. IMR is cleared.
c. IR7 input is assigned the lowest priority.
d. Slave mode address is set to 7.
e. Special mask mode is cleared and status read is set to IRR.
f. If IC4 = 0, all the functions of ICW4 are set to zero. Master/Slave bit in ICW4 is used in the buffered
mode only.
In 8086 based system A15-A11 of the interrupt vector address are inserted in place of T7 – T3
respectively and the remaining three bits A8, A9, A10 are selected depend ing upon the interrupt level, i.e.
from 000 to 111 for IR0 to IR7.
ICW1 and ICW2 are compulsory command words in initialization sequence of 8259A as is evident
from fig, while ICW3 and ICW4 are optional.
The ICW3 is read only when there are more than o ne 8259A in the system, cascading is used (
SNGL=0 ).The SNGL bit in ICW1 indicates whether the 8259A in the cascade mode or not.
The ICW3 loads an 8-bit slave register. The detailed functions are as follows.
In master mode [ SP = 1 or in buffer mode M/S = 1 in ICW4], the 8-bit slave register will be set bit-
wise to 1 for each slave in the system
Ope ration Command Words:
 Once 8259A is initialized using the previously discussed command words for initialisation, it is
ready for its normal function, i.e. for accepting the interrupts but 8259A has its own way of
handling the received interrupts called as modes of operation.

 These modes of operations can be selected by programming, i.e. writing three internal registers
called as operation command words.
 In the three operation command words OCW1, OCW2 and OCW3 every bit corresponds to some
operational feature of the mode selected, except for a few bits those are either 1 or 0. The three
operation command words are shown in fig with the bit selec tion details.

OCW1
Issued with A0= 1,used to mask the interrupts. To enable all the IR lines, the command word is 00H.

48 Dr.S.SIVASAKTHISELVAN / ECE
  In OCW2 the three bits, R, SL and EOI control the end of interrupt, the rotate mode and their
combinations as shown in fig below.
 The three bits L2, L1 and L0 in OCW2 determine the interrupt level to be selected for operation, if
SL bit is active i.e. 1.
 The details of OCW2 are shown in fig.
 In operation command word 3 (OCW3), if the ESMM bit, i.e. enable special mask mode bit is se t to
1, the SMM bit is neglected. If the SMM bit, i.e. special mask mode. When ESMM bit is 0 the
SMM bit is neglected. If the SMM bit. i.e. special mask mode bit is 1, the 8259A will enter special
mask mode provided ESMM=1.

 If ESMM=1 and SMM=0, the 8259A will return to the normal mask mode. The details of bits of
OCW3 are given in fig along with their bit definitions.
Priority Modes

Fully Nested Mode

This mode is entered after initialization unless another mode is programmed. The interrupt requests are
ordered in priority from 0 through 7. After the initialization sequence, IR0 has the highest prioirity and IR7

49 Dr.S.SIVASAKTHISELVAN / ECE
the lowest. Priorities can be changed. When an interrupt is acknowledged the highest priority req uest is
determined and its vector placed on the bus.
0 1 2 3 4 5 6 7
IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

Highest priority Lowest Priority

Now if IR3 is made highest priority the priorities for other interrupt will also be automatically changed.
5 6 7 0 1 2 3 4
IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

Lowest priority Highest priority

End of Interrupt (EOI)

The In Service (IS) bit can be reset either automatically following the trailing edge of the last in sequence
INTA pulse (when AEOI bit in ICW1 is set) or by a command word that must be issued to the 8259A
before returning from a service routine (EOI command). An EOI command must be issued twice if in the
Cascade mode, once for the master and once for the corresponding slave.

Automatic Rotation(equal Priority): This is used in the applications where all the interrupting devices
are of equal priority.
• In this mode, an interrupt request IR level receives priority after it is served while the next device to be
served gets the highest priority in sequence. Once all the devices are served like this, the first device again
receives highest priority.
Specific rotation mode(Specific Priority)
The programmer can change the priorities by programming the bottom priority and the fixing all other
priorities.ie if IR4 is programmed as the lowest priority, then IR% will have the highest one.
• Automatic EOI Mode: Till AEOI=1 in ICW4, the 8259A operates in AEOI mode.
Special mask mode
• In the special mask mode, when a mask bit is set in OCW1,it inhibits further interrupts at that level
and enables interrupts from all other levels that are not masked. Thus any interrupts may be
selectively enabled by loading the mask register.
Poll command
• Service to devices is achieved by software using a poll command. So INTA sequence is not needed. It
is used to expand the number of priorities levels to more than 64.

50 Dr.S.SIVASAKTHISELVAN / ECE