Government Engineering College Thrissur

Department of Electronics and Communication Engineering

ECT 448
Low PowerVLSI Design
Gate level power analysis : Capacitive, internal and Static
power dissipation of gate level circuit
Resmi E.,
Assistant Professor in ECE
[email protected]
[email protected]
 Basics of Gate-level Analysis
• The most popular gate-level analysis is based on the so called event-driven logic
simulation.
• Events are zero-one logic switching of nets in a circuit at a particular simulation
time point.
• As one switching event occurs at the input of a logic gate, it may trigger other
events at the output of the gate after a specified time delay.
• Computer simulation of such events provides a very accurate pre-fabrication logic
analysis and verification of digital chips.
• Most gate-level simulation also supports other logic states such as, "unknown,"
"don't care" and "high-impedance," to help the designer to simulate the circuit in a
more realistic manner.
• Verilog and VHDL are two popular languages used to describe gate-level design.

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 Basics of Gate-level Analysis

• Many gate-level simulators are so mature that special purpose computer hardware
has been used to speed up the simulation algorithms.
• The idea is similar to the graphic coprocessor in a computer system. Instead of
using a general purpose CPU to execute the simulation program, special purpose
hardware optimized for logic simulation is used. This hardware acceleration
technology generally results in several factors of speedup compared to using a
general purpose computing system.

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 Basics of Gate-level Analysis

• Another technology that offers several orders of magnitude speedup in gate-level

analysis is called hardware emulation.
• Instead of simulating switching events using software programs, the logic network
is partitioned into smaller manageable subblocks.
• The Boolean function of each sub-block is extracted and implemented with a
hardware table mapping mechanism such as RAM or FPGA

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 Capacitive Power Dissipation
• Gate-level power analysis based on logic simulation is one of the
earliest power analysis tools developed.
• The basic principle of such tools is to perform a logic simulation of
the gate-level circuit to obtain the switching activity information.
• The information is then used to derive the power dissipation of the
circuit.
• A major advantage of gate-level power analysis is that the P = CV2f
equation can be computed precisely and easily.

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 Capacitive Power Dissipation
• In logic simulation, the switching activities of each node can be monitored to
determine its frequency. The power dissipated due to charging and discharging
capacitors can be easily computed.
• Each net i of a gate-level circuit is associated with a capacitance Ci and a
counter variable ti . As simulation progresses, a logic switching at net i
increments the counter ti. At the end of the simulation, the frequency of net i is
given by fi = ti/(2T) where T is the simulation time elapsed.
• The capacitive power dissipation of the circuit is

The simple gate-level power calculator is very useful in providing a quick estimate of
the chip power dissipation.
The capacitance of a node can be accurately extracted from the mask geometry at post
layout phase.

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 Internal Switching Energy
• The dynamic power dissipated inside the logic cell is called internal power, which
consists of short-circuit power and charging/discharging of internal nodes.

• The idea is to simulate the "dynamic energy dissipation events" of the gate with
SPICE or other lower-level power simulation tools.

• For example, in a NAND gate with inputs A, B and output Y, the logic event "A = 1,
B switches from 0 to 1" causes the output to switch from 1 to 0 and consumes some
amount of dynamic energy internally.
• The energy is caused by short-circuit current or charging/discharging of internal
nodes in the gate.
• The dynamic energy dissipation event can be easily observed during logic simulation.

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 Internal Switching Energy
• The computation of dynamic internal power uses the concept of logic events.
• Each gate has a pre-defined set of logic events in which a quantum of energy is
consumed for each event.
• The energy value for each event can be computed with SPICE circuit simulation.

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 Internal Switching Energy
• This energy accounts for the short-circuit current and charging or discharging of
internal nodes of the gate.
• With the energy associated with each event, we only need to know the occurrence
frequency of each event from the logic simulation to compute the power
dissipation associated with the event.
• The computation is repeated for all events of all gates in the circuit to obtain the
total dynamic internal power dissipation as follows

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 Internal Switching Energy

• E(g, e) is the energy of the event e of gate g obtained from logic gate characterization
and f(g, e) is the occurrence frequency of the event on the gate observed from logic
simulation.

• Note that the dynamic energy dissipation events not only depend on the Boolean
function of the gate, but also the implementation of the gate.

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 Internal Switching Energy
• Figure shows two different implementations of a two-input NAND gate. The
first implementation has only four energy dissipation events as shown but the
second implementation has two additional events due to the switching of its
internal nodes.

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 Static State Power
• In this case, the power dissipation depends on the state of the logic gate. For
example, a two-input NAND gate has four distinct states,

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 Static State Power
• Under different states, the transistors operate in different modes and thus the static
leakage power of the gate is different.
• The leakage power is primarily determined by the subthreshold and reverse biased
leakage of MOS transistors.
• During logic simulation, we observe the gate for a period T and record the fraction of
time T(g, s)/T in which a gate g stays in a particular state s.
• We perform this observation for all states of the gate to obtain the static leakage of
the gate and repeat the computation for all gates to find the total static power P stat as
follows

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 Static State Power

In the above equation, p(g, s) is the static power dissipation of gate g at state s
obtained from characterization. The state duration T(g, s) is obtained from logic
simulation.
It is the total time the gate g stays at state s. The static power p(g, s) depends
on process conditions, operating voltage, temperature, etc.

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Thank You

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