Bangladesh University of Engineering and

Technology Department of Electrical and Electronic

Engineering Dhaka-1205, Bangladesh

EEE 102

Electrical Circuits I Laboratory

Simulation Experiment #04

Name of the Experiment:

First Order DC Transients and Steady State RLC Circuit

Analysis

Name: Shahriar Tarek Mahmud Level: 1/Term: 1

Student ID: 2206054 Partner’s ID: 2206055
Date of Performance: 28 January 2024 Section: A2
Date of Submission: 17 February 2024
Name and designation of course teachers:
1. Dr. Md. Ziaur Rahman Khan, Professor
2. Elin Ranjan Das, Adjunct Lecturer
Objective:
➢ Demonstrating DC transient analysis of an RL circuit using Pspice
➢ Demonstrating DC transient analysis of an RC circuit using Pspice
➢ Demonstrating DC transient analysis of an RLC circuit using Pspice

Problem 1:

Circuit Diagram:

Circuit diagram: Problem 1 (RL Circuit)

Netlist Input:
Graph of I(L1):

Diagram: I(L1) vs Time graph

Theoretical Calculation:

For t > 0,

The equivalent resistance of the circuit, Req = (30 || 6) + 5 = 5+5 = 10 Ω

The inductance of the inductor, L = 2H

We know,
L 2
The time constant of the RL circuit, 𝜏 = = = 0.2 s
R 10
Observation:
We can see from the I(L1) vs Time graph generated by the Netlist code in Pspice that
by the time 1 second has elapsed, the current I(t) of the circuit almost reaches the
steady state current, I(∞) = 6A. This time duration is five times the time constant of
1
the circuit. Hence, the time constant, 𝜏 = = 0.2 s. This is the exact same value we
5
found after theoretical calculation. So, we can conclude that this experiment has been
done successfully.

Problem 2:

Circuit Diagram:

Circuit diagram: Problem 2(RC circuit)

Netlist Input:
V(t) graph:

Diagram: V vs Time graph (0s-9s)

Theoretical Calculation:

For t < 5s,

V(0-) = V(0+) = 0V

Req = 2 Ω
1
The time constant, 𝜏 = R × C = 2 × = 0.667s
3

𝑡
Hence, the voltage across the capacitor, Vc(t)= 15(1-ⅇ−𝜏 ) = 15(1-ⅇ−1.5𝑡 )

Vc(0.5) = 7.914 V
For, t > 5s,

V(5-) = V(5+) ≈ 15V

Req = 6 || 2 = 1.5 Ω
1
The time constant, 𝜏 = R × C = 1.5 × = 0.5 s
3

Here, at t = ∞, the capacitor acts like an open circuit.

And, the voltage across,
15+7.5
V(∞) = × 6 − 7.5 = 9.375V
2+6

𝑡−5
Hence, the voltage across the capacitor, Vc(t)= V(∞) + {V(5+) - V(∞)}× ⅇ− 𝜏

9.375 - 5.625ⅇ−2(t−5) V

Observation:
We can observe from the graph that the total operation of the circuit can be divided
into 2 parts. 1) t<5s and 2) t>5s. Before t<5s, the graph shows that V(t) reaches
V(∞) = 15V at 3.333 s, which is 5 times the time constant. So, the time constant, 𝜏
3.333
becomes = 0.667s. For the latter part, the graph demonstrates that it reaches the
5
then V(∞) = 9.375V at around 7.5s. The newer time constant is thus found to be =
7.5−5
= 0.5s. We also showed according to the graph, V(0.5) = 7.9198V. Afterwards,
5
we did the same thing only theoretically and saw that the results were almost
identical except for a few precision errors after the 2nd decimal digit. Thus, we can
conclude by saying that this experiment was also a success.
Problem 3:

Circuit Diagram:

Circuit Diagram: Problem 3(RLC Circuit)

Netlist Input:

IL vs Time Graph:

Circuit Diagram: Inductor Current vs Time graph

VC vs Time Graph:

Circuit Diagram: Capacitor Voltage vs Time graph

Theoretical Calculation:
1 1
Natural Frequency, ω0 = = = 2 rad.s-1
√LC √1×0.25

For R=1Ω,
R 1
Damping Factor, α = = = 0.5 rad.s-1
2L 2×1

Since, 𝜔0 > α, this is the case of underdamped condition.

For R=2Ω,
R 2
Damping Factor, α = = = 1 rad.s-1
2L 2×1

Since, 𝜔0 > α, this is also a case of underdamped condition.

For R=3Ω,
R 3
Damping Factor, α = = = 1.5 rad.s-1
2L 2×1

Since, 𝜔0 > α, this one is a case of underdamped condition as well.

For R=4Ω,
R 4
Damping Factor, α = = = 2 rad.s-1
2L 2×1

Since, 𝜔0 = α, this is a case of critically damped condition.

For R=5Ω,
R 5
Damping Factor, α = = = 2.5 rad.s-1
2L 2×1

Since, 𝜔0 < α, this is the case of overdamped condition.

Observation:
So far we have simulated a 2nd order Circuit (RLC) using Pspice Netlist where we
have connected an Inductor and a Capacitor in series coordination. We have added
a variable resistance R in series inside the circuit. We have swept the variable
resistance from 1Ω to 5Ω with 1Ω increment after each step. From the VC vs Time
plot, we can see that the graphs for resistances 1Ω, 2Ω, 3Ω are like decaying
sinusoidal curves suggesting they are of the underdamped oscillation type. For 4Ω
& 5Ω, the curves appear to be approaching steady state over time. We can assume
one of them to be of critically damped and overdamped cases respectively. Then,
we’ve also done theoretical calculations to find the natural frequency ω0 and
damping factor α for each case and compared them to each other to determine the
characteristic of the circuit. We’ve found 3 to be underdamped, one critically
damped and one overdamped. The results matched with the speculations we made
through observing the graph.
Discussion:
In this lab report, we conducted experiments with RC, RL, and RLC circuits, initially
simulating them in Pspice Netlist and subsequently solving for the circuit's
unknowns theoretically. The results exhibited a high degree of alignment, indicating
successful simulation of the circuits. However, it is important to note the presence
of precision errors within the results. Despite generally minor dissimilarities
between the simulation outcomes and theoretical calculations, caution is advised
when assigning values to circuit variables. Moreover, determining the time
constant(𝜏) from the graphs necessitated some degree of speculation, as we
identified a point in the graph where the curve appeared to approach steady state.
This method may display inaccuracies if not executed carefully. Additionally, when
analyzing the graphs of RLC circuits, we observed that the curves for critically
damped and overdamped oscillations often appeared similar, posing a challenge in
differentiation between them. However, the experiment concluded in alignment with
our expectations, ensuring its overall success.