New Modulation Method and Control Strategies for Power

Electronics Inverters
By

Mohsen Aleenejad
DPhil, University of Kansas, 2018
M.Sc., University of Tehran, 2013
B.Sc., Tehran Polytechnic University, 2010

Submitted to the graduate degree program in the Department of Electrical Engineering and
Computer Science and the Graduate Faculty of the University of Kansas in partial fulfillment of
the requirements for the degree of Doctor of Philosophy.

Chair: Dr. Reza Ahmadi

Dr. Glenn Prescott

Dr. Alessandro Salandrino

Dr. James Stiles

Dr. Huazhen Fang

Date Defended: 19 January 2018





ProQuest Number: 10745559




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 The dissertation committee for Mohsen Aleenejad certifies that this is the
approved version of the following dissertation:

New Modulation Methods and Control Strategies for Power

Electronics Inverters

Chair: Dr. Reza Ahmadi

Date Approved: 19 January 2018

ii
 Abstract

The DC to AC power Converters (so-called Inverters) are widely used in industrial applications.

The MLIs are becoming increasingly popular in industrial apparatus aimed at medium to high

power conversion applications. In comparison to the conventional inverters, they feature superior

characteristics such as lower total harmonic distortion (THD), higher efficiency, and lower

switching voltage stress.

Nevertheless, the superior characteristics come at the price of a more complex topology with an

increased number of power electronic switches. The increased number of power electronics

switches results in more complicated control strategies for the inverter. Moreover, as the number

of power electronic switches increases, the chances of fault occurrence of the switches increases,

and thus the inverter’s reliability decreases. Due to the extreme monetary ramifications of the

interruption of operation in commercial and industrial applications, high reliability for power

inverters utilized in these sectors is critical. As a result, developing simple control strategies for

normal and fault-tolerant operation of MLIs has always been an interesting topic for researchers

in related areas.

The purpose of this dissertation is to develop new control and fault-tolerant strategies for the

multilevel power inverter. For the normal operation of the inverter, a new high switching

frequency technique is developed. The proposed method extends the utilization of the dc link

voltage while minimizing the dv/dt of the switches. In the event of a fault, the line voltages of the

faulty inverters are unbalanced and cannot be applied to the 3-phase loads.

For the faulty condition of the inverter, three novel fault-tolerant techniques are developed. The

proposed fault-tolerant strategies generate balanced line voltages without bypassing any healthy

iii
and operative inverter element, makes better use of the inverter capacity and generates higher

output voltage. These strategies exploit the advantages of the Selective Harmonic Elimination

(SHE) and Space Vector Modulation (SVM) methods in conjunction with a slightly modified

Fundamental Phase Shift Compensation (FPSC) technique to generate balanced voltages and

manipulate voltage harmonics at the same time. The proposed strategies are applicable to several

classes of MLIs with three or more voltage levels.

iv
 Acknowledgements

First, I would like to thank my committee chair, Dr. Reza Ahmadi and my committee members,

Dr. Prescott, Dr. Salandrino, Dr. Stiles, and Dr. Fang for their guidance and support throughout

this research. I am always grateful for the support of my friends and colleagues through the up and

downs of these past few years. Special thanks go to, Hamid Mahmoudi and Seyyedmahdi

Jafarishiadeh, for their helps and collaborations. In addition, I would like to thank the department

faculty and staff for making my time at University of Kansas a great experience.

Finally, I am deeply in debt of my caring and loving wife, Negar. Her continuous encouragement

when the times got rough, are highly appreciated and duly remarkable.

v
 Dedication

To

My father, Arsalan and my mother, Soori.

vi
 Table of Contents

Chapter II: Literature Review ..................................................................................................... 8

2.1. Cascaded H-bridge Inverter ............................................................................................. 8

2.2. qZSId-CHB Inverter Topology ........................................................................................ 9

2.3. Conventional SVM:........................................................................................................ 11

2.4. Half-Wave Symmetrical Selective Harmonic Elimination ............................................ 14

2.5. Conventional Fundamental Phase Shift Compensation ................................................. 16

Chapter III: Proposed High Frequency Modulation Method ................................................ 20

3.1. Principles of Modulation Operation............................................................................... 20

3.2. Digital Implementation of the Proposed Modulation Method ....................................... 22

3.3. Linearity of the Proposed Modulation Method .............................................................. 25

3.4. Comparison of Switching Losses................................................................................... 28

3.5. Experimental Results and Comparative Analysis .......................................................... 29

Chapter IV: Proposed SHE based Fault-Tolerant Strategy ................................................... 38

Chapter V: Proposed SVM based Fault-Tolerant Strategy .................................................... 53

Chapter VI: Proposed Z-source based Fault-Tolerant Strategy ............................................ 69

6.1. Modulation Method ................................................................................................ 69

vii
 6.2. Minimizing Voltage Stress on Switches ................................................................. 70

6.3. Fault-Tolerant Strategy ........................................................................................... 72

Chapter VII: Conclusions and Future Research ..................................................................... 89

References ..................................................................................................................................... 92

viii
 Table of Figures

Figure 2.1 A 3-phase n-level CHB inverter. An H-Bridge cell …………………………...……….9

Figure 2.2. A 3-phase n-level qZSId-CHB inverter with m series connected H-bridge cells in each

phase ……………………………………………………………………….…………………….11

Figure 2.3. Space vector diagram of n-level ML inverter ………………………………………...12

Figure 2.4. General voltage waveform generated by a CHB Inverter with m series H-bridge cells,

(2m+1)-level voltage waveform …………………………………………………………………16

Figure 2.5. The phasor diagram of the phase voltages in a CHB Inverter in the faulty condition: (a)

the faulty cell is bypassed and the line-to-line voltages are unbalanced; (b) two additional cells are

bypassed, resulting in balanced operation with reduced voltage amplitude; and (c) the phase angles

are modified according to the proposed method to generate balanced line-to-line voltages with less

voltage reduction ………………………………………………………………………………...17

Figure 3.1. Sample phase voltage (blue waveform) generated by the proposed method using an 11

level inverter (normalized to the dc link voltage). The red waveform is the reference

function…………………………………………………………………………………………..21

Figure 3.2. Sample reference functions with 5 modulation segments which can generate up to 11

different voltage levels. From top to the bottom 1st segment generates 3 levels, 2nd segment

generates 5 levels, 3rd segment generates 7 levels, 4th segment generates 9 levels and 5th segment

generates 11 levels.……………………………………………………………………………….23

ix
Figure 3.3. Hardware prototype (a) The seven-level 3-phase CHB Inverter (b) Three series

connected H-Bridge cells in each phase..…………………………………………………………30

Figure 3.4. Inverter voltages generated by the proposed modulation method for M = 0.85 (a)

Inverter phase voltages (b) Inverter line voltages (c) Load voltages and (d) Harmonic

Spectrums.......................................................................................................................................34

Figure 3.5. Inverter voltages generated by the proposed modulation method for M = 0.95 (a)

Inverter phase voltages (b) Inverter line voltages (c) Load voltages and (d) Harmonic

Spectrums…………………………………………………………………………………...……35

Figure 3.6. Inverter voltages generated by the proposed modulation method for M = 1 (a) Inverter

phase voltages (b) Inverter line voltages (c) Load voltages and (d) Harmonic

Spectrums……………………………………………………………………………………...…36

Figure 3.7. Measured inverter’s load voltages vs. modulation index…………………………….37

Figure 3.8. Inverter voltages generated by the conventional switching methods for M =1. From

top to the bottom: inverter phase voltages, inverter line voltages, load voltages and harmonic

spectrum of the load voltage for (a) LSPWM (b) THPWM (c) SVM……………………………38

Figure 4.1. The experimental CHB inverter phase voltages in normal operation condition. (a)

Inverter’s phase voltages, (b) line-to-line voltages, and (c) load voltages………………………...44

Figure 4.2. The experimental CHB Inverter voltages in the event of a single fault at phase 'a'. Top:

Inverter phase voltages. Bottom: Harmonic spectrum of phase 'a' voltage……………………….45

x
Figure 4.3. The experimental CHB Inverter waveforms in the event of a single fault at phase 'a'

(first Scenario): (a) Inverter phase voltages, (b) line-to-line voltages, (c) load voltages, and (d) the

harmonic spectrum of the phase and load voltages………………………………………………46

Figure 4.4. The experimental CHB Inverter waveforms in the event of a fault at phase 'b' and a

fault at phase ‘c’ (second scenario). (a) Inverter phase voltages, (b) line-to-line voltages, (c) load

voltages, and (d) the harmonic spectrum of the load voltages…………………………………….48

Figure 4.5. The experimental CHB Inverter phase voltages in the event of double faults at phase

'a' (Third Scenario). (a) Inverter’s phase voltages, (b) line-to-line voltages, (c) load voltages, and

(d) the harmonic spectrum of the load voltages…………………………………………………..49

Figure 4.6. The experimental CHB Inverter phase voltages in the event of double faults at phase

'a' and double faults in phase ‘b’ (Fourth Scenario). (a) Inverter’s phase voltages, (b) line-to-line

voltages, (c) load voltages, and (d) the harmonic spectrum of the load voltages………………….51

Figure5.1 The elaborated space diagram and all of its possible space vectors for a seven-level

inverter one faulty cell in phase ‘a’ (the modified phase shift is α=130.5°)……………………….56

Figure 5.2. The modified space vector diagram of an n-level inverter in faulty condition. The axes

angles and rotating vector are modified according to the proposed method to generate balanced

line-to-line voltages with less voltage reduction………………………………………………….57

Figure 5.3. The modified space vector diagram of MLI in different faulty conditions: (a) one faulty

cell in phase ‘a’, (b) one faulty cell in phase ‘b’, and (c) one faulty cell in phase ‘c’. (Only one of

the switching redundancies for each space vector of normal operation is transferred to ‘abc’ plane

to decrease the complexity of the space vector diagrams)……………………...…………………58

xi
Figure 5.4. Comparison of the rotating reference vectors: (a) one faulty cell in phase ‘a’, (b) one

faulty cell in phase ‘b’, and (c) one faulty cell in phase ‘c’. The green path represents the normal

operation with n voltage levels in each phase. The blue path represents the faulty condition, the

faulty cell, and two healthy cells bypassed. The red path is the modified rotating vector according

to the proposed method. The black dots represent the space vectors in ‘abc’ plane and the red dots

represents the transformed dots in ‘abc’ plane……………………………………………………61

Figure 5.6. The experimental CHB inverter phase voltages in normal operation of the inverter (

t  t0 ), during a single fault ( t0  t  t1 ), and with a conventional fault-tolerant strategy ( t  t1 )…….63

Figure 5.7. The experimental CHB inverter voltages in the event of a single fault at phase 'a' (first

scenario): (a) inverter phase voltages, (b) inverter line voltages and (c) the harmonic spectrum of

the line voltages in post fault operation…………………………………………………………...65

Figure 5.8. The experimental CHB inverter voltages in the event of double faults at phases ‘b’ and

‘c’ (second scenario): (a) inverter phase voltages and (b) inverter line voltages, and (c) the

harmonic spectrum of the line voltages in post fault operation…………………………………66

Figure 5.9 .The experimental CHB inverter voltages in the event of double faults at phase ‘a’ (third

scenario): (a) inverter phase voltages and (b) inverter line voltages, and (c) the harmonic spectrum

of the line voltages in post fault operation………………………………………...……………...67

Figure 6.1. The modified PS-PWM strategy for qZSId-CHB inverter: (a) The switching logic for

the modified PS-PWM technique, (b) The generated switching signals for the ith cell; the reference

(blue sinusoidal waveform, mj) and carrier (triangular waveforms, c and c') signals that are used

xii
in the logic circuit to generate switching signals (square-wave signals, Si1, Si2, Si3 and Si4) for the

ith H-bridge cell are shown in this figure…………………………………………...……………..70

Figure 6.2. The phasor diagram of phase voltages in a qZSId-CHB inverter: The faulty condition

in which the faulty cell is bypassed. The phase angles are modified according to the FPSC strategy

to generate balanced line-to-line voltages and voltage gain is modified by changing the shoot-

through ratio to compensate for the line-to-line voltage reduction in the post-fault

condition…………………………………………………………………………………………75

Figure 6.3. Flowchart of the proposed fault-tolerant strategy……………………………………77

Figure 6.4. The prototype 3-phase seven-level qZSId-CHB inverter and 12 V

batteries…………………………………………………………………………………………..78

Figure 6.5. The qZSId-CHB’s voltages in normal operating condition: (a) Inverter’s phase

voltages, (b) line-to-line voltages, (c) load voltages, and (d) the dc link voltage of one H-Bridge

cell (the voltage across H-Bridge’s switches)…………………………………………………….79

Figure 6.6. The qZSId-CHB voltage and current waveforms in the event of a faulty switch in phase

‘b’ (first experiment): (a) Inverter’s phase voltages, (b) line-to-line voltages, (c) load voltages, (d)

dc link voltage of one H-bridge cell, (e) the harmonic spectrum of the load voltages, and (f) the

load currents…………………………………………………………………………...…………83

Figure 6.7. The qZSId-CHB voltage and current waveforms in the event of a faulty switch in phase

‘b’ and another faulty switch in phase ‘c’ (Second experiment): (a) Inverter’s phase voltages, (b)

line-to-line voltages, (c) load voltages, (d) dc link voltage of one H-bridge cell, (e) the harmonic

spectrum of the load voltages, and (f) the load currents…………………………………………85

xiii
Figure 6.8. The qZSId-CHB voltages in the event of two faulty switches in phase ‘b’ (Third

experiment): (a) Inverter’s phase voltages, (b) line-to-line voltages, (c) load voltages, (d) dc link

voltage of one H-bridge cell and (e) the harmonic spectrum of the load voltages………………...88

xiv
Chapter I: Introduction
The outstanding features of Multilevel Inverters (MLI) are making them extremely popular in

medium to high-level industrial applications [1-7]. Yet, MLIs suffer from having more complex

topologies with higher number of switches, which can potentially increase the chances of fault

occurrences and diminish their overall reliability [7-11]. Therefore, researchers have been very

active recently, developing simple modulation strategies and robust fault-tolerant schemes for

MLIs [12-14]. The published fault-tolerant techniques in the literature either modify the inverters

hardware topology after fault diagnosis [15, 16], or change the control algorithm to resolve the

situation [17-21]. Furthermore, some more involved techniques combine the two approaches to

further improve the operation of MLIs after fault occurrence [22].

The three main MLI topologies are Diode Clamped inverter [23-34], Flying Capacitor inverter

[35-46], and Cascaded H-Bridge (CHB) inverter [47-61]. The CHB inverters are particularly well

suited for hardware-based techniques due to their modular topology and cell redundancy [62, 63].

Another prominent technology developed recently to facilitate high power conversion is

impedance-source network [64]. The impedance-source networks overcome several limitations of

the conventional voltage/current source inverters and provide an efficient and flexible means of

power conversion between the source and load in a very wide range of power conversion

applications [65, 66].

Numerous power conversion topologies incorporating different types of impedance-source

networks have been proposed in the literature recently [67-72]. Among them, the MLIs

incorporating Z-Source Inverter (ZSI) networks [73, 74], quasi-ZSI (qZSI) networks [75, 76], or

qZSI with discontinuous input current (qZSId) networks [77, 78] are of utmost importance for

scholars in the area of high power conversion. These topologies provide an excellent opportunity
1
to marry the benefits of the MLIs with the flexibility provided by the impedance-source networks

to achieve the best of both worlds: lower Total Harmonic Distortion (THD) [79], higher efficiency

[80], and lower switching stress [81] combined with a wide range of ac output that can be lower

or higher than the input voltage [82-85]. In particular, the Z-Source networks can be easily fused

with CHB inverters to relieve the voltage gain requirements for H-bridge modules in a CHB [86].

This combination provides single-stage energy conversion with higher equivalent output Pulse

Width Modulation (PWM) frequency [87] while featuring an excellent boost function [88].

Therefore, higher inversion efficiency can be achieved while reducing the size of the output filter

and the number of H-bridge modules required to match the output voltage generated by a

conventional CHB [89]. The reduced number of H-bridge cells makes the system less expensive,

less complex, and more reliable [90].

Thanks to the development of these MLI topologies, many new modulation techniques have been

introduced in the literature recently [91]. These modulation methods can be classified based on

their switching frequency into two main groups: fundamental switching frequency methods and

high switching frequency PWM methods. Several categories of high frequency switching methods

have been reported in the literature lately [92-96]. However, switching techniques based on Carrier

Based PWM (CB-PWM) modulation and Space Vector Modulation (SVM) are the most prevalent

methods in industry [97].

CB-PWM techniques have drawn increasing interest in industrial applications recently, due to their

simple structure and decent performance [98]. Sinusoidal PWM (SPWM) technique, for instance,

is widely used in modern industrial drives [99]. This switching technique itself can be classified

into two major subcategories: the Phase-Shifted PWM (PSPWM) and Level-Shifted PWM

(LSPWM). In PSPWM, the carriers are arranged with horizontal phase shifts, while in LSPWM

2
the carriers are displaced vertically [100]. Similar to CB-PWM methods, the SVM-based

techniques have found a special place in industrial applications as well [101]. The SVM-based

techniques are particularly suited for digital implementation and offer several advantages such as

switching loss reduction [102], higher dc link voltage utilization [103], and lower THD generation

[104].

The fundamental switching frequency methods are well suited for high-power MLI due to the

decreased switching losses [105], leading to higher efficiencies [106]. Among all the reported

fundamental frequency methods in the literature, the two widely adopted techniques are Selective

Harmonic Elimination (SHE) [107] and Space Vector Control (SVC) [108]. Using SHE, switching

angles are calculated at the fundamental frequency, such that the desired fundamental voltage is

achieved while some specific low order harmonics of the voltage waveform are eliminated [109].

This method comes with the advantage of decreasing the THD of the inverter voltages; however,

it requires complex offline calculations [110].

One of the key targets of the researchers in the field of MLI modulation is increasing the utilization

of the dc link voltage while maintaining other performance criteria such as THD of the waveforms

and dv/dt of the switches at acceptable levels [111]. Increasing the utilization of the dc link means

increasing the fundamental of the generated inverter voltages, which increases the capacity of the

inverter for transferring power to the load [112]. This means switches with lower power ratings

can be used in the inverter’s topology [113]. The SHE method has one of the highest rates of dc

link utilization [114], however, the SHE solution cannot be found for the whole modulation range

and a large amount of storage space on the digital controller for storing the calculated switching

angles is needed [115]. Nevertheless, attempts to increase the utilization of the dc link voltage

usually lead to high voltage transition steps or increased THD levels (the first concern to be

3
addressed in this dissertation) [116].

Despite the improvements provided by MLIs, since the number of power electronic switches in a

MLI topologies is higher than that of a conventional inverter, the chances of fault occurrence on

the switches is higher, and thus the inverter’s reliability is relatively lower compared to

conventional inverters [117]. Several fault-tolerant operation schemes for MLIs have been recently

proposed in the literature. The works presented in [118-121] are examples of using additional

power devices and changing the inverter topology after fault diagnosis. On the other hand, the

works presented in [122-133] are examples of the methods that modify the control algorithm and

modulation technique in case of a fault occurrence. In [134-136], fault-tolerant methods based on

the CB-PWM technique are reported. In these papers, the phase shifts between the voltage

references are modified to generate balanced phase voltages. In [137], a fault-tolerant scheme

based on Fundamental Phase Shift Compensation PWM (FPSC-PWM) is presented. In this

method, the angles of the inverter phase voltages are modified by changing the phase shift angles

of the carrier signals. This leads to generation of balanced line voltages; however, it impedes the

natural elimination of the third order harmonics and thus deteriorates the line voltage THDs.

Similarly in [138-140], based on the fault type and the location of the faulty switches, the reference

modulation signals are revised in the CB-PWM method in a way that the reference signals are no

longer sinusoidal waveforms.

In addition to the CB-PWM methods, a few fault-tolerant strategies based on SVM have been

reported in the literature [141-143] as well. In [144], the redundant switching states of the MLI are

used to generate balanced line-to-line voltages in the event of one or more faulty switches. When

the faulty H-bridge cells are bypassed, some of the space vectors are not feasible anymore and

some other space vectors are reachable but lose some of their switching states (but not all of them)

4
[145]. Thus, the remaining available switching states are detected in this method and are applied

to the inverter to generate the balanced line-to-line voltage [144].

The strategy proposed in [145], is a combination of the hardware-based and control-based

techniques. The proposed strategy in [146], uses three electromechanical relays and three fast

operating fuses to add a dc offset to the voltages of the conventional CHB inverter. By adding the

dc offset to the conventional inverter, some of the lost space vectors can be restored and thus, the

fault-tolerant performance of the inverter can be improved compared to the proposed method in

[147]. This control scheme then uses a modified SVM method to generate balanced inverter

voltages. For renewable applications, a new active SVM based fault-tolerant control strategy for

single-phase faults is demonstrated in [148]. The presented SVM strategy relies on producing an

offset vector close to the reference vector and shifting the origin to this offset vector.

Some of the mentioned fault-tolerant strategies have already found their way into commercial

industrial drives [149]. For instance the “Siemens ROBICON Perfect Harmony” drives [150], a

family of medium voltage cell based inverters, utilize the redundancy of the power cells together

with the neutral shift control for fault-tolerant operation. Although researchers have developed

several valuable fault-tolerant methods, the development of fault-tolerant strategies that adopt

SVM techniques and exploit their acclaimed merits is not a well explored area. Moreover, just a

few works concerned with fault-tolerant operation of impedance-source based inverters, and those

are only concerned with conventional two-level ZSIs. Beyond that, no effort has been made to

control the THD of the waveforms in a faulty inverter by adopting SHE techniques and take their

proven advantages (the second concern to be addressed in this dissertation).

So far, two concerns of this dissertation is explained. Regarding these concerns, the first purpose

5
of this dissertation is to propose a new switching technique for MLIs that maximizes the utilization

of the dc link voltage while limiting the phase voltage transitions to one voltage level, thus

minimizing the dv/dt of switches. The proposed modulation method features a broad linear

operating range relative to a defined modulation index. This method is suited for digital

implementation and requires far less computational effort and storage space than conventional

digital methods such as SVM. Additionally, unlike the SVM, complex mathematical

transformations are not used in this method and it can be applied to the single-phase inverters as

well. Furthermore, using the proposed method, each phase of the 3-phase inverter can be

controlled independently for the fault-tolerant purposes. The inverter voltages generated using this

method have THD levels comparable to that of conventional methods such as SVM and SPWM.

The second purpose of this dissertation is to develop generalized fault-tolerant strategies based on

the SHE and SVM techniques for a MLIs with one or more faulty switches. According to the

number and location of the faulty switches, the faulty scenarios can be divided into two different

groups. In the first group, two of the inverter phases have the same number of operative cells, and

the third phase has more (for example, ‘a: 3 cells’, ‘b: 2 cells’ and ‘c: 2 cell’) or less number of

operative cells (for example, ‘a: 3 cells’, ‘b: 3 cells’ and ‘c: 2 cell’). In this group of scenario, the

fault-tolerant method generates load voltages that in per unit system of the inverter are almost

equal to the conventional FPSC-PWM method. However, since the base voltages of the SHE and

SVM techniques are more than the PWM method [151], the absolute value of generated voltages

by these methods in Volts are more than the FPSC-PWM method. The second group of faulty

scenarios has the completely asymmetrical phases (for example, ‘a: 3 cells’, ‘b: 2 cells’ and ‘c: 1

cell’).

In these scenarios, this fault-tolerant method generates load voltages that in per unit system of the

6
inverter are more than the conventional FPSC-PWM method. This is because of more flexibility

provided by the SHE technique in terms of degrees of freedom. In general, the SHE method

provides more sets of solutions for the completely asymmetrical faulty conditions, some of them

cannot be applied to the conventional PWM methods [152]. If these sets of solutions are used for

the PWM based fault-tolerant method, the generated load voltages contain low order harmonics

which exceeds the standard limits [153]. This technique makes better use of inverter capacity by

keeping all of healthy cells operational, limits the THD of the waveforms by eliminating a wide

range of low order harmonics using SHE, and forces the third order harmonics of the phase

voltages to cancel out naturally. This strategy introduces a half-wave symmetric SHE and

combines that with a slightly modified FPSC technique to manipulate both amplitude and angle of

the harmonics simultaneously in order to achieve the above mentioned properties. Although this

strategy is applicable to several classes of MLIs with three or more voltage levels, in this

dissertation, the operation of a seven-level CHB inverter is studied.

The structure of this dissertation is as follows: In chapter II, a review of CHB inverter and qZSId

is provided. Later, a brief introduction for the conventional SHE and SVM is given and the

principles of conventional FPSC technique are reviewed. In chapter III, a novel high frequency

switching method is proposed. In chapter IV, a fault-tolerant strategy based on half-wave

symmetric SHE is introduced. Chapter V introduces the proposed SVM based fault-tolerant

strategy. Chapter VI describes the application of a qZSId network in conjunction with a seven-

level CHB inverter and provides several experimental waveforms that verify the capabilities and

merits of this topology. Chapter VII concludes this dissertation and looks into some of the future

opportunities.

7
Chapter II: Literature Review
The focus area of the research work is the operation of the CHB inverter. In this chapter, the basic

principles of 1) CHB operation, 2) Z-source network connection, 3) SVM technique, 4) SHE

modulation, and 5) FPSC fault-tolerant method are explained in details.

2.1. Cascaded H-bridge Inverter

A CHB inverter features modular structure, simple physical layout, and more redundant switching

states than other multilevel topologies [154, 155]. Figure 2.1 illustrates the circuit topology of an

n-level CHB inverter. As pictured, each phase of this inverter is made up of m H-bridge cells.

Labelling the input terminal voltage of each H-bridge as Vdc, the output terminal voltage of each

H-bridge can be made equal to Vdc, 0, or -Vdc by properly firing the switches. To generate Vdc,

positive voltage, the switches S1 and S4 should be on, to have zero voltage, the switches S1 and S2

or S3 and S4 should be on and to have negative voltage the switches S2 and S3 should be on [24]. It

is worth noting that switches Si and Si+2 (i = 1, 2) operate in a complementary mode in each leg.

For example, if Si is ON, Si+2 is OFF; otherwise Si is OFF and Si+2 is ON.

Therefore, due to the series connection of m H-bridge cells in each phase of the CHB inverter, the

following n voltage levels (n = 2m+1) can be generated by each phase of this inverter:

mVdc , ...,  Vdc , 0, Vdc , ..., mVdc [13]. In this dissertation, all the inverter voltages are normalized to

Vdc hereinafter, and the voltage values are given in per unit (p.u.). For example, according to this

convention, the voltage levels generated by each phase of the inverter in p.u. are the following:

m, ..., 1, 0,1, ..., m .

8
 Phase C

Phase B

Phase A
Cell Am N

S1 S2 Load A
Vdc +
vam
-
S3 S4

S1 S2

Cell A2 Vdc +
va2
S1 S2 -
S3 S4
Vdc +
va2
-
S3 S4

Cell A1

S1 S2

Vdc +
va1
-
S3 S4 g

Figure 2.1 A 3-phase n-level CHB inverter. An H-Bridge cell

2.2. qZSId-CHB Inverter Topology

Various voltage-fed impedance-source configurations such as the traditional ZSI, qZSI, and qZSId

[28] can be readily combined with the CHB topology to enhance its fault-tolerant properties. The

qZSI, and qZSId topologies are derived from ZSI and qZSI to improve the performance and solve

the problems with traditional ZSIs. These new benefits extend qZSI, and qZSId topologies to

applications of renewable energy generation and motor drives [29]. It is revealed in [19], the qZSId

features lower voltage rating of both capacitors compared to the ZSI and qZSI [27]. In this

dissertation, a qZSId network is integrated into the traditional CHB inverter topology to assemble

a fault-tolerant CHB inverter with a very high degree of flexibility. The qZSId network is specially

selected due to the lower voltage rating requirement for its capacitors compared to the traditional

9
ZSI network [29]. Nevertheless, the proposed fault-tolerant strategy in this chapter can be applied

to a CHB inverter with any of the mentioned Z-Source networks.

Figure 2.2 illustrates the circuit diagram of the n-level qZSId based CHB inverter, referred to as

the qZSId-CHB inverter hereinafter. As pictured, the proposed qZSId-CHB inverter places a

qZSId network on the input side of each standard H-bridge cell. These modified H-bridge cells are

referred to as qZSId cells hereinafter. Each phase of the qZSId-CHB inverter is made up of m

qZSId cells ( n  2m  1 ). The qZSId cells exhibit two distinct categories of operating modes: Non-

shoot-through operating modes and shoot-through operating modes. The shoot-through states is

the event of two conducting switches on the same leg of H-bridge cell. In this condition, the

mentioned switches are not working in the complementary mode. When a qZSd cell is in a non-

shoot-through mode, it operates similar to a conventional H-bridge cell while also boosting the

input voltage to its H-bridge stage to [27],

1
Vdc  B  Vin   Vin (2.1)
1  2D

where D is the shoot-through duty ratio, B is the boost factor of the qZSId network, Vin is the input

voltage to the qZSId cell and Vdc is the input voltage to the H-bridge stage of the qZSId cell (see

figure 2.2). When a qZSId cell is in a shoot-through mode, the input terminal to the H-bridge stage

is short circuited, rendering the value of Vdc to zero.

In a shoot-through mode, the output terminal voltage of the qZSId cell is always equal to zero.

However, in a non-shoot-through mode, the output terminal voltage can be equal to Vdc, 0, or -Vdc

based on the status of conduction of the switches in the H-bridge stage. Therefore, due to the

10
 g
Cell Am Cell Bm Cell Cm
+ + +
+ + +
+ + +
vam
- vbm
- vcm
-

- - - - - -

Cell A2 Cell B2 Cell C2

+ + +
+ + +
+ + +
va2
- vb2
- vc2
-

- - - - - -

Cell A1 Cell B1 Cell C1

+ + +
+ + +
+ + +
va1
- vb1
- vc1
-

- - - - - -

A B C

Load C
Load A

Load B

n
Figure 2.2. A 3-phase n-level qZSId-CHB inverter with m series connected H-bridge cells in each phase.

series connection of m qZSId cells in each phase of the qZSId-CHB inverter, the following n

voltage levels can be generated by each phase of the inverter: m, ..., 1, 0, 1, ..., m .

2.3. Conventional SVM:

The SVM method generates the inverter’s switching signals based on the instantaneous position

of a rotating reference vector in the voltage vector space of the inverter. The space vector diagram

of an n-level inverter is illustrated in figure 2.3. Each dot in this figure represents a voltage vector

[25]. The voltage vectors are related to inverter phase-ground voltages. The relationship in the a-

b-c and stationary α-β reference frames is [28],

11
 β -axis
b-axis

Vz V* Vy

Vx

ωt α -axis a-axis

1)
3(n
2

c-axis
Figure 2.3. Space vector diagram of n-level ML inverter.

2 2
j j
V  Vag  Vbg e 3  Vcg e 3  V g  jV g (2.2)

where Vag , Vbg , and Vcg are the phase-ground voltages of the inverter in the a-b-c reference frame

and Vqg and Vdg are the phase-ground voltages in a stationary α-β reference frame. These voltages

are related to the inverter’s switching states (Sa, Sb, Sc) according to [17],

Vag   Sa 
   1  
Vbg    n  1   Sb  (2.3)
Vcg   
 Sc 
 

 1
V g  3(n  1) (2S a  Sb  Sc )

 (2.4)
 V g  1
( Sb  S c )
 3(n  1)

12
The switching states Sa, Sb, and Sc are defined for the ‘a’, ‘b’, and ‘c’ phases respectively. Each

switching state has a range from -m to m in order to represent the complete number of switching

levels. It is worth mentioning that some switching states are redundant meaning that they produce

the same voltage vectors.

The rotating reference vector is illustrated in figure 2.3 in red color. This vector can be defined

as,

* 3
V  Me jwt (2.5)
2

where M is the modulation index and wt is the phase angle of the phase-ground voltages.

According to (2.5), in conventional SVM the reference vector follows a circular path as illustrated

in figure 2.3 in red color. The SVM algorithm finds the three nearest voltage vectors to the

⃗⃗⃗𝑥 , ⃗⃗⃗
reference vector (𝑉 ⃗⃗⃗𝑧 in figure 2.3) in each step and switches between the three identified
𝑉𝑦 and 𝑉

voltage vectors during one switching period (Tsw). The amount of time spent at each vector (Tx,

Ty, Tz) is found from [12],

 * 
 Re{Vx } Re{V y } Re{Vz }   TswRe{V }
 T
  
x 
 Im{Vx } Im{V y } Im{Vz } Ty   TswIm{V *} (2.6)
    
 1 1 1  Tz   Tsw


 

Finally, the SVM algorithm decides on the sequence of switching between the three voltage

vectors and chooses an appropriate switching state for generating each voltage vector among the

redundant states that lead to the same vector. Both decisions are made according to the specific

performance targets for the switching strategy such as harmonic distortion reduction, common

mode voltage control, and switching loss minimization.

13
 2.4. Half-Wave Symmetrical Selective Harmonic Elimination
The SHE modulation technique can be utilized to make a MLI such as the one shown in figure 2.1

to generate ac voltages with favorable harmonic properties. The SHE method uses the Fourier

analysis of the voltages of the inverter to calculate the aforementioned switching angles. For each

modulation index, the Fourier coefficient of the fundamental harmonic of the output voltage is set

to the desired value, while coefficients for undesired low order harmonics are set to zero. This

yields a system of nonlinear equations that needs to be solved numerically for switching angles

[17].

In SHE terminology, the voltage level transition arrangement identifies the number of switching

transitions and the voltage levels to be generated at each transition instance [14]. Higher number

of switching transitions provides more flexibility for manipulation of the harmonic properties of

the generated voltages, however, it nullifies the low frequency switching advantage that comes

inherently with SHE, resulting in increased switching power losses [17]. Contrariwise, lower

number of switching transitions leads to less flexibility for manipulation of the harmonic

components of the waveforms [48]. Consequently, to increase the degree of freedom without

introducing too many switching instances to the generated voltage, in this proposal the half-wave

symmetry is utilized for the switching functions instead of the conventional quarter-wave

symmetry. In addition to the increased degree of freedom, by implementing half-wave symmetric

SHE, not only the amplitude of each individual harmonic but also the phase angle of the harmonics

can be manipulated. This property is particularly important in this work.

A general (2m+1)-level voltage waveform with half-wave symmetry and l switching angles (𝜑1

to 𝜑𝑙 ) is illustrated in figure 2.4. As pictured, the envisioned voltage level transitions can include

different number of voltage transitions between adjacent voltage levels. The corresponding
14
Fourier coefficients for the (2m+1)-level voltage waveform of figure 2.4 can be found from [12,

38]


Vout  a0   An  cos  nwt  n  . (2.7)
n 1

where a0 is the DC offset of the voltage waveform, and An and  n are the amplitude and phase

angle of nth harmonic component, respectively. The amplitude and phase angle of voltage

waveform can be found by,

 A  a 2  b2
 n n n

 1  bn 
.
 n  tan   (2.8)
  an 

where an and bn are the Fourier coefficients of phase voltages,


 1
2 
an  Vout cos(nwt )dt n  0,1, 2,...

 
. (2.9)
 b  1 V sin(nwt )dt
 n 2  out
n  1, 2,3,...
 

where w is the angular frequency and n is the order of harmonic component. Using (2.9) for the

general waveform presented in figure 2.4, the Fourier coefficients can be found as,

 2 l
 n n   f sin(n f )
a 
 f  1
 f 1 for the voltage transition to a higher level
  . (2.10)
  f  1 for the voltage transition to a lower level
k
b  2
 n n 
 f cos(n f )
f 1

15
 Vout

+mVdc
+(m-1)Vdc
+(m-2)Vdc

+(q)Vdc
+(p)Vdc

+Vdc
T/2 T
φ φ φ φ φ φ t
φ φ
k l

φ
1 h i j
-Vdc φ φ φ 2 h+1 i+1 j+1 k+1
l-1

φ φ i+2 j+2

-(p)Vdc
-(q)Vdc

-(m-2)Vdc
-(m-1)Vdc
-mVdc

Figure 2.4. General voltage waveform generated by a CHB Inverter with m series H-bridge cells, (2m+1)-level
voltage waveform.

where the voltage waveform is normalized to Vdc. In (2.10), f is fth switching angle,  f is the

sign coefficients for fth switching angle and l is the number of switching angles defined in each

half-period of phase voltage.

2.5. Conventional Fundamental Phase Shift Compensation

In a MLI with one or more faulty switches, the faulty phase of the inverter fails to reach all n

feasible voltage levels. This leads to the generation of unbalanced line-to-line voltages. The

phasor diagram of figure 2.5(a) elaborates on the operation of the Inverter in this condition.

In this example, the number of operative power cells in the phases ‘a’, ‘b’ and ‘c’ are Ma, Mb and

Mc, respectively. The conventional solution to the problem of unbalanced line-to-line voltages is

16
 Vbg = Mb p.u. -d-axis -d-axis

Vbg = Ma p.u.

θab = 120º
Vbc

θbc = 120º
θab = 120º
q-axis q-axis
θbc = 120º

θca = 120º Vag = Ma θca = 120º Vag = Ma

Vbc p.u. p.u.

Vcg = Ma
p.u.

Vcg = Mc
p.u.
(a) (b)
-d-axis

Vcg = Mc p.u.

θbc θca q-axis

θab
Vcg = Mc Vbc Vag = Ma
p.u. p.u.

(c)
Figure 2.5. The phasor diagram of the phase voltages in a CHB Inverter in the faulty condition: (a) the faulty cell is
bypassed and the line-to-line voltages are unbalanced; (b) two additional cells are bypassed, resulting in balanced
operation with reduced voltage amplitude; and (c) the phase angles are modified according to the proposed method to
generate balanced line-to-line voltages with less voltage reduction.

to bypass additional switches in the healthy phases of the inverter, thus reducing the reachable

voltage levels by these phases. This results in balanced operation; however, it renders some H-

bridge cells nonoperational, resulting in curtailment of achievable inverter voltage. The phasor

diagram of figure 2.5(b) illustrates the Inverter voltages in this condition.

17
One of the well-known PWM fault-tolerant strategies to mitigate this problem is the FPSC method

[27]. This method does not bypass any additional H-bridge cells, but instead modifies the phase

angles of the line-ground voltages ( ab , bc , ca in figure 2.5) to generate balanced line-to-line

voltages. Figure 2.5(c) demonstrates how modifying the phase angles can lead to balanced line-

to-line voltages. According to this figure, although the amplitudes of the phase voltages (

Vag , Vbg , Vcg ) are not equal, by properly adjusting the phase angles ( ab , bc , ca ), the amplitudes of

the line-to-line voltages ( Vab ,Vbc ,Vca ) are all made equal. As a result, each of the modified phase

angles ( ab , bc , ca ), are unique values. The FPSC strategy makes better use of the Inverter

capacity and thus generates higher line-to-line voltage amplitudes in comparison to the

conventional bypass method.

The phase angles that result in balanced line-to-line voltages can be found by solving the following

set of equations for  ab , bc , and  ca [27],

Vag2  Vbg2  2VagVbg cos ( ab )  Vbg2  Vcg2  2VbgVcg cos (bc ),

 2
Vbg  Vcg  2VbgVcg cos (bc )  Vcg  Vag  2VcgVag cos ( ca ), .
2 2 2
(2.11)

 ab  bc   ca  360


To clarify how the modified phase angles can be derived from (2.11) a special case of previous

example is investigated. For instance, in the event of k faults in phase ‘a’, the faulty H-bridge cells

in this phase are bypassed, limiting the obtainable voltage levels by phase ‘a’ to –m' to m' p.u

(where m' = m - k). As mentioned before, the obtainable voltage levels by the healthy phases

ranges from –m to m p.u. Setting Vag, Vbg, and Vcg respectively to m', m, and m p.u. in (2.11), yields

the modified phase angles required to generate balanced line-line voltages, ab  ca   and

18
bc   . In general, if two of the phases have the same number of operative cells, the modified

phase angles between the third phase and those two phases must be equal ( ab  ca   ).

19
Chapter III: Proposed High Frequency Modulation Method
This chapter presents a new high frequency switching method for MLIs. The proposed method

extends the utilization of the dc link voltage while minimizing the dv/dt of the switches. It features

a broad linear operating range and can be implemented digitally with minimal computational

effort. In this chapter, first, the proposed modulation method is introduced and its principles of

operation are discussed. Next, the digital implementation of the method is provided. Then, the

mathematical proof of linear operation of the proposed method is offered. Finally, several

experimental results are provided to evaluate the performance of the proposed method and to

compare its operation to conventional methods [108].

3.1. Principles of Modulation Operation

The proposed modulation method generates a phase voltage comprised of a high frequency

rectangular component riding on top of a lower frequency quasi-square shaped reference function.

A normalized sample phase voltage with eleven levels generated by the proposed method for a

MLI is illustrated in figure 3.1. The fundamental amplitude of the generated phase voltage depends

on both the shape of the reference function and the duty cycle of the high frequency rectangular

component. These two parameters are set corresponding to a modulation index defined between

zero and one, in a way that the proposed method provides a broad linear operation range for the

inverter [108].

In the proposed method, for an n-level inverter the entire modulation range ([0, 1]) is divided into

(n  1) 2 segments of the same length and a specific reference function is defined for each segment.

The reference functions are defined such that the utilization of the dc link voltage is maximized in

any modulation index, the dv/dt of the switches is always the minimum possible value (one voltage

20
 6 T2 T2

Inverter Phase Voltage and the Reference Function

V1* V2*
4
T1 T1
V2* V1*
2

-2

T2 T2
-4

T1 T1
-6
Ts0Ts1 Ts2 Ts3 TSG/2 TsG
Figure 3.1. Sample phase voltage (blue waveform) generated by the proposed method using an 11-level inverter
(normalized to the dc link voltage). The red waveform is the reference function.

level transition), and the even-order harmonics of the phase voltages are eliminated naturally. To

eliminate the even order harmonics, the reference functions need to have half-wave symmetry.

Maximizing the fundamental component of the inverter voltage and minimizing the dv/dt of the

switches pose a tradeoff between how fast the phase voltage can climb to the peak value and how

long the peak value can be [108].

If the phase voltage climbs very fast to the peak value, the duration of the peak value is increased,

thus increasing the utilization of the dc link voltage. However, in this condition the dv/dt of the

switches are also increased, which is undesirable. In order to optimize the dc link utilization vs.

the dv/dt of the switches, the defined reference functions feature staircase shaped rising or falling

edges with the steps of two voltage levels. However, according to figure 3.1, in each voltage level

the high frequency rectangular waveform is added to the reference function in a way that the actual

phase voltage steps up or down for only one voltage level at any voltage transition. This guarantees

that the phase voltage transition is always the minimum possible value (one level) [108].

21
On the other hand, the duration of each plateau of the rising or falling staircase is defined to be

equal to a single update time of the modulation algorithm, thus maximizing the speed of climb or

descent of the phase voltage to its peak value. This will maximize the duration of the peak value

of the phase voltage and, correspondingly, the utilization of the dc link voltage. Sample reference

functions for the MLIs, which can generate up to eleven levels are pictured in figure3.2. These

modulation references can be used for MLIs with different number of voltage levels [108].

For instance, all the five modulation references are used in an 11-level inverter to generate a wide

linear modulation range, although only first four and first three of these modulation references are

used in the 9-level and 7-level inverters, respectively [108].

3.2. Digital Implementation of the Proposed Modulation Method

Digital implementation of certain conventional modulation techniques such as SVM can be highly

computationally intensive and thus demand for the use of high speed digital controllers. In such

cases, due to complexity of the mathematical calculations, the source code for the modulation

algorithm needs to go through several optimization passes to minimize the execution time. To

alleviate this issue, recently several researchers have been seeking to devise fast SVM methods

[38, 49], however, the problem has not been completely addressed yet [108]. The proposed

modulation method can be implemented using a low cost digital controller with minimal

computational effort. To implement this method for variable frequency applications, an update

time (Ts) much shorter than the period of the generated phase voltage (T0) is defined in the

algorithm for updating the reference voltage. The update instances are shown in figure 3.2 as (Ts0,

Ts1, …, TsG). The number of update instances in each period is [108],

22
 i=1 i=2

0 < M < 0.2 0.2 < M < 0.4

5 5
4 4
3 3 Ss2
2 Ss1 2
1 1
0 0
-1 -1
-2 -2
-3 -3
-4 -4
-5 -5

Ts0 Ts1 Ts2 Ts3 TSG/2 TsG Ts0 Ts1 Ts2 Ts3 TSG/2 TsG

T0/2
T0/2
i=3 i=4

0.4 < M < 0.6 0.6 < M < 0.8

5 5 Ss4
4 Ss3 4
3 3
2 2
1 1
0 0
-1 -1
-2 -2
-3 -3
-4 -4
-5 -5

Ts0 Ts1 Ts2 Ts3 TSG/2 TsG Ts0 Ts1 Ts2 Ts3 TSG/2 TsG

T0/2 T0/2
i=5

Ss5 0.8 < M < 1

5
4
3
2
1
0
-1
-2
-3
-4
-5

Ts0 Ts1 Ts2 Ts3 TSG/2 TsG

T0/2
Figure 3.2. Sample reference functions with 5 modulation segments which can generate up to 11 different voltage
levels. From top to the bottom 1st segment generates 3 levels, 2nd segment generates 5 levels, 3rd segment generates 7
levels, 4th segment generates 9 levels and 5th segment generates 11 levels.

23
 T0
G . (3.1)
Ts

The update time ( Ts ) should be defined such that G is an integer and multiple of four, to be able

to implement the algorithm using a digital controller and generate a quarter-wave symmetric

waveform. The reference function associated with the ith segment of the modulation index can be

generated by [108],

H  k  0  k  G / 4 1
 i
H G / 2 1  k  G / 4  k  G / 2 1
 i
F k    (3.2)
 Hi  k   G / 2    G / 2   k   3G / 4   1
i

 H G 1  k   3G / 4   k  G  1
 i

where,

 2k  1 2k  1  i .
i   i
H k  (3.3)
 2k  1  i

The high frequency rectangular component can then be imposed on the reference function to

generate the final switching function by switching between two voltage levels during the time

between two update instances. The voltage levels V1* and V2* that the inverter should switch

between are [108],

 Fi (t )  1 Fi (t )  0
V1  
 Fi (t )  1 Fi (t )  0 (3.4)

V  Fi (t )
2

the duration of generating each voltage level is found from [108],

24
  M max  M
T1  M  M  Ts
 max min
 (3.5)
T  M  M min .T
 2 M max  M min s

where T1 and T2 are the durations of V1* and V2* , respectively, M is the modulation index, and Mmin

and Mmax are the boundaries of the ith segment of the modulation index [108],

i 1
M min 
n 1
2
(3.6)
i
M max 
n 1
2

While generating the first and third quarter of the phase voltage, in each sampling time the inverter

generates V1* before V2* , whereas, while generating the second and fourth quarter of the phase

voltage, the inverter generates V2* before V1* . This mechanism is adopted to ensure that the

voltage transition is always limited to one level, as well as to preserve the quarter-wave symmetry

of the waveform. The waveform of figure 3.1 clearly demonstrates this concept [108].

3.3. Linearity of the Proposed Modulation Method

In a typical industrial setup such as motor drive system, due to several high level processes that

need to be serviced by the digital controller in addition to implementing the modulation method,

it is imperative that control of the inverter voltage through the modulation be as simple as possible.

Particularly it is very important that the relation between the output voltage and the modulation

index be of linear type because it eliminates the need for complex non-linear control methods.

Additionally, when a inverter operates in non-linear modulation region, its THD increases

25
significantly and the inverter losses increase as well. The proposed modulation technique provides

a broad linear modulation range for MLIs [108].

To demonstrate the linear relationship between the modulation index and the amplitude of the

fundamental harmonic of the generated voltages, the following equality is evaluated [17]:

f (M   )  f (M ) f (M )  f (M   )
 (3.7)
(M   )  M M  (M   )

where f ( M ) is the amplitude of the fundamental harmonic of the phase voltage, and  is a very

small value. Simplifying (3.7) yields [108],

2 f (M )  f (M   )  f (M   )  0 (3.8)

thus, validating (3.8) is equivalent to validating (3.7). In this chapter, (3.8) is validated for the 5th

segment of the modulation index for an 11-level inverter. The same procedure can be followed

for other segments to prove the overall linearity [108].

The Fourier transform of the phase voltage implies [47, 48],

4Vdc cos(T1 )  cos(T1  T2 )  cos(2T1  T2 )  cos(2T1  2T2 )  cos(3T1  2T2 ) 

f (M ) 
   cos(3T1  3T2 )  cos(4T1  3T2 )  cos(4T1  4T2 )  cos(5T1  4T2 ) 
(3.9)

according to (3.5) for an 11-level inverter with G = 20 [108],


T1  T2  Ts  (3.10)
10

and [108],

26
 
T1 
2
1  M  (3.11)

Therefore, the f ( M ) can be simplified to [108],

   
cos(1)  cos( )  cos( 2 )  cos( )  cos(3 ) 
4Vdc  10 5
f (M )    (3.12)
  3 2 
  cos( 10 )  cos( 4 )  cos( 5 )  cos(5 ) 

where [108],

 
i  1  M    i 1 (3.13)
2 10

Similarly f ( M   ) and f ( M   ) can be found [108],

      
cos(1  )  cos( )  cos( 2  )  cos( )  cos( 3  ) 
4Vdc  2 10 2 5 2
f (M   )    (3.14)
  3  2  
 cos( )  cos( 4  )  cos( )  cos( 5  )
 10 2 5 2 

      
 cos(1  )  cos( )  cos( 2  )  cos( )  cos(3  ) 
4V 2 10 2 5 2
f (M   )  dc   (3.15)
  3  2  
 cos( )  cos( 4  )  cos( )  cos( 5  )
 10 2 5 2 

Substituting (3.12), (3.14), and (3.15) in (3.8) and simplifying the results using trigonometric

identities results in [108],

2 f (M )  f (M   )  f (M   ) 
8Vdc    (3.16)
 1  cos( )   cos(1 )  cos( 2 )  cos( 3 )  cos( 4 )  cos( 5 ) 
  2 

27
For any M and small values of 𝜀 [108],

  
lim 1  cos( ) 0
2 
 0
(3.17)


Which, according to (3.16), results in [108],

2 f (M )  f (M   )  f (M   )  0 (3.18)

3.4. Comparison of Switching Losses

The switching losses in power electronic devices are resulting from energy dissipation during the

turn-on and turn-off commutations. As a result, the switching losses are directly proportional to

the rate of occurrence of commutations (thus switching frequency) in power inverters. The

switching losses make up for a considerable amount of the total energy loss in power inverters. In

particular, the efficiency of the MLIs controlled by high frequency modulation methods can be

reduced significantly due to high amounts of switching losses [108].

In case of PWM methods, the effective switching frequency in each power electronic device is

constant regardless of the modulation index. The total number of commutations in each cycle of

the fundamental voltage in each phase of a CHB inverter can be found from [23],

fc
Ncomm  4m (3.19)
f0

where fc, f0 and m are the carrier frequency, fundamental frequency and the number of H-bridge

cells [108].

In case of SVM methods, the number of switching commutations depends heavily on the goal of

the switching strategy. The goal of the switching strategy can be minimization of the switching
28
losses, minimization of THD of the voltage, or etc. [22]. To achieve the goal of minimization of

the switching losses, the number of voltage transitions in each update time is limited to two

instances while for minimization of THD the number of voltage transitions is set to three. The

minimum number of switching commutations in a CHB inverter operating with SVM modulation

with the goal of minimization of the switching losses can be found from [13],

T0
Ncomm  .2.m  G.2.m (3.20)
Ts

With the proposed modulation method, the number of voltage transitions in each update time is

constant for the whole modulation range except for a small number of modulation indices.

According to (3.4), using the proposed method, the number of voltage transitions is equal to two

instances in each update time, except for when M is equal to Mmin or Mmax, resulting to T1 = Ts and

T2 = 0 or vice versa. In these cases, there is no voltage transition. Therefore, using the proposed

method, in the worst-case scenario in which there are no instances of no transitions, the maximum

number of the switching commutations can be calculated from (3.20) as well. As a result,

fc
assuming that is equal to G, it can be concluded that using the proposed method the maximum
f0

number of switching commutations in the worst-case scenario is equal to the minimum number of

commutations using the SVM method, and is half the number of commutations using the PWM

methods [108].

3.5. Experimental Results and Comparative Analysis

The performance of the proposed modulation algorithm is evaluated experimentally using a 7-

level 3-phase CHB inverter. In this work, the dc link terminal of each H-bridge cell of the

constructed CHB inverter is connected to a 48V dc supply. Since the highly inductive loads can

29
 (a) (b)
Figure 3.3. Hardware prototype (a) The seven-level 3-phase CHB Inverter (b) Three series connected H-Bridge
cells in each phase [108]

reduce the THD of the current, it is more valuable to evaluate the THD of the voltage waveforms.

Therefore, the output terminals of the CHB inverter are connected to a 3-phase resistive load to

see the voltage waveforms with no filtering effect [12]. A TMS320F28335 Digital Signal

Processor (DSP) from Texas Instruments (TI) is employed to implement the proposed modulation

method. The experimental setup is pictured in figure 3.3. Several experiments are performed

using this system to fully explore the operation of the proposed modulation method [108].

In the first experiment, the goal is to generate a 50 Hz voltage with a modulation index of 0.85.

The update time of the algorithm is set to 1 millisecond to make the G in (3.1) equal to 20. For a

7-level inverter, the modulation range is divided into (n  1) 2  3 segments with the length of

0.33. Therefore, for a 0.85 modulation index, a reference function associated with the third

segment (i=3) is shaped using (3.2), (3.3). The V1* and V2* are determined at the beginning of

each update instance using (3.4), based on the shaped reference function. The durations of

30
generating V1* and V2* are found using (3.4), (3.5) as T1 = 0.55 and T2 = 0.45 milliseconds,

respectively. The resulting inverter phase, line, and load voltages, along with their harmonic

spectrums, are illustrated in figure 3.4. Due to the inferior quality of the waveforms in a scope

shot, the actual raw data from the oscilloscope were exported to MATLAB to generate this figure.

According to figure 3.4, the amplitude of the fundamental harmonic of the load voltage is equal to

151.44 V. Additionally, the THD of the load voltage is calculated to be 15.74%. Inspecting the

stair shaped rising or falling edges of the phase voltages closely reveals that the voltage transitions

are limited to only 48 V steps (one inverter level). This confirms the effectiveness of the proposed

method in minimizing the dv/dt of the inverter switches [108].

The second and third experiments are similar to the first one except that the modulation index

is changed to 0.95 and 1, respectively. The resulting waveforms are shown in Figs. 3.5 and 3.6.

According to these figures, for modulation index of 0.95, amplitude of the fundamental harmonic

of the load voltage is equal to 167.56 V and THD is 13.04%, while these values for modulation

index of 1 are equal to 175.68 and 11.7%. To investigate the linear operation range of the proposed

algorithm, a range of voltages associated with a range of modulation indices are generated using

the proposed method. For each modulation index, the amplitude of the fundamental harmonic of

the load voltage is measured and the results are plotted in figure 3.7. According to this plot, the

generated voltage increases linearly by increasing the modulation index. This confirms the broad

linear operation range of the proposed modulation algorithm [108].

To confirm the effectiveness of the proposed modulation method for higher utilization of the

dc link voltage, its performance is compared to three widely used conventional modulation

methods for multilevel inverters. The three selected conventional modulation methods are

31
LSPWM, Third Harmonic injection PWM (THPWM), and SVM. These three methods are

implemented on the same experimental setup, and the resulting waveforms for a modulation index

of 1 are reported in figure 3.8. According to this figure, the amplitude of the fundamental harmonic

of the load voltage for the three methods are equal to 143.94 V, 166.48 V, and 164.88 V,

respectively. Clearly, these voltages are less than the load voltage of 175.68 V generated using

the proposed method for a modulation index of 1. This confirms higher utilization of the dc link

voltage using the proposed algorithm [108].

To further validate this result and gain more insight about the operation of the proposed

method, the three selected conventional methods are compared with the proposed method at

several modulation indexes and the results are reported in TABLE I. According to the data

reported in the last row of the table, in the maximum modulation index, the generated load voltage

using the proposed method is 7% higher than the voltage generated by the SVM and THPWM

methods and 22% higher than the voltage generated by the LSPWM method. This confirms the

wider modulation range of the proposed method compared to the conventional methods.

Additionally, according to the table, at high modulation indices the proposed method generates

higher load voltages with less or marginally lower THDs compared to conventional methods. For

instance, in the maximum modulation index (M = 1) the load voltages generated using the proposed

method, the SVM and the LSPWM are respectively 175.68 V, 164.88 V and 143.94 V, while the

THDs of these voltages are respectively 11.71%, 12.63% and 10.37%. Note that the generated

voltage by LSPWM method has the lowest THD by a narrow margin, however the voltage

generated by the proposed method is significantly (22%) higher than the voltage generated by

LSPWM. At lower modulation indices the proposed method generates higher voltages as well;

however, the THDs are a bit higher than THPWM and LSPWM. For example, when M = 0.85, the

32
load voltages generated using the proposed method, SVM and LSPWM are respectively 151 V,

142 V and 122 V, while the THDs of these voltages are respectively 15%, 14% and 12%. The

THD of the voltage generated using the proposed method is 1% higher than the voltage generated

by SVM and 3% higher than the voltage generated by LSPWM, however, the voltage level is

respectively 9 V and 19 V higher than the voltages generated by SVM and LSPWM [108].

In very low modulation indices the THD of the voltages generated by the proposed method can

be slightly higher or lower than the THDs of the voltages generated by the other methods, however,

the amplitude of the generated voltages is always higher than that of the other methods. Finally,

it is worth noting that the multilevel inverters are usually operated only in high modulation indices

[12]. Nevertheless, because of simple digital implementation it is possible to use the proposed

method only in high modulation indices to reach to higher voltage levels and shift to conventional

methods for lower modulation indices to reach to better THDs [108].

TABLE I. PERFORMANCE COMPARISON FOR THE PROPOSED METHOD VS. FOUR CONVENTIONAL SWITCHING
1
METHODS. THE AMPLITUDE OF THE FUNDAMENTAL HARMONIC OF THE GENERATED LOAD VOLTAGES (𝑉𝑎𝑛 ), AND
THE CALCULATED THD AND DF1 FOR THESE VOLTAGES AT SEVERAL MODULATION INDICES (M) ARE COMPARED
[108].
SHE SVM THPWM LSPWM
M
𝑽𝟏𝒂𝒏 [V] THD [%] DF1 𝑽𝟏𝒂𝒏 [V] THD [%] DF1 𝑽𝟏𝒂𝒏 [V] THD [%] DF1 𝑽𝟏𝒂𝒏 [V] THD [%] DF1
0.1 20.6 96.1 .721 20.5 105.6 .687 20.5 106.4 .685 18.3 120.5 .638
0.2 37 41.7 .923 36.8 46.1 .908 36.8 44.7 .913 31.9 49.2 .897
0.3 54.9 29.3 .959 54.5 35.3 .943 54.6 33.6 .948 46.5 39.1 .931
0.4 71.2 24.7 .970 70.7 26.3 .967 70.8 24.5 .971 60.1 25.5 .969
0.5 - - - 85.3 26.8 .966 85.4 19.5 .981 74.7 22.8 .975
0.6 103.8 18.9 .982 103.1 22.2 .976 103.2 17.7 .984 88.3 17.6 .985
0.7 - - - 117.7 19.1 .982 117.8 15.9 .987 103.3 15.2 .988
0.8 - - - 134.1 17.3 .985 134.1 13.1 .991 115.6 14.4 .989
0.85 144.7 10.7 .994 143.8 15.9 .987 143.8 12.3 .992 122.4 14.2 .990
0.9 151.2 10.3 .994 150.2 15.5 .988 150.3 12 .993 130.2 13.2 .991
0.95 158.6 13.9 .99 157.5 14.2 .990 157.5 11.4 .994 137 12.6 .992
1 167.6 9.64 .995 166.3 13.4 .991 166.5 10.7 .995 143.9 11.6 .993
The Proposed Method
M 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.85 0.9 0.95 1
𝟏
𝑽𝒂𝒏 21 39 58 72 90 107 123 141 152 158 168 176
THD 111.2 50.7 28.6 31.8 27.6 22.1 18.2 18.9 16.8 15.7 13.9 12.5
DF1 .668 .891 .961 .953 .964 .976 .983 .982 .986 .987 .990 .992

33
 600 600

400

Invertter Phase Voltages

200
400
0

-200
200
-400

-600
0 0.005 0.01 0.015 0.02
0 (a)
600

400
Invertter Line Voltages

-200
200

0
-400
-200

-400

-600
0 0.005
-600
0 0.005 0.01
0.01 0.015 0.015
0.02 0.02
(b)
400

300
Invertter Load Voltages

200

100

-100

-200

-300

-400
0 0.005 0.01 0.015 0.02
(c)
Harmonic Distortion Phase 'a'
200
Harmonic Spectrum of the Voltages

100

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Harmonic Distortion Line 'ab'
400

200

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Harmonic Distortion Load 'a'
200

100

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000

(d)
Figure 3.4. Inverter voltages generated by the proposed modulation method for M = 0.85 (a) Inverter phase voltages
(b) Inverter line voltages (c) Load voltages and (d) Harmonic Spectrums [108].

34
 600

400

Invertter Phase Voltages

200

-200

-400

-600
0 0.005 0.01 0.015 0.02
(a)
600

400
Invertter Line Voltages

200

-200

-400

-600
0 0.005 0.01 0.015 0.02
(b)
400

300
Invertter Load Voltages

200

100

-100

-200

-300

-400
0 0.005 0.01 0.015 0.02
(c)
Harmonic Distortion Phase 'a'
200
Harmonic Spectrum of the Voltages

100

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Harmonic Distortion Line 'ab'
400

200

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Harmonic Distortion Load 'a'
200

100

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000

(d)
Figure 3.5. Inverter voltages generated by the proposed modulation method for M = 0.95 (a) Inverter phase voltages
(b) Inverter line voltages (c) Load voltages and (d) Harmonic Spectrums [108].

35
 600

400

Invertter Phase Voltages

200

-200

-400

-600
0 0.005 0.01 0.015 0.02

(a)
600

400
Invertter Line Voltages

200

-200

-400

-600
0 0.005 0.01 0.015 0.02
(b)
400

300
Invertter Load Voltages

200

100

-100
Frequency (Hz)
-200

-300

-400
0 0.005 0.01 0.015 0.02

(c)
Harmonic Distortion Phase 'a'
200
Harmonic Spectrum of the Voltages

100

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Harmonic Distortion Line 'ab'
400

200

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Harmonic Distortion Load 'a'
200

100

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000

(d)
Figure 3.6. Inverter voltages generated by the proposed modulation method for M = 1 (a) Inverter phase voltages (b)
Inverter line voltages (c) Load voltages and (d) Harmonic Spectrums [108].

36
 180
160
140

Inverter Load Voltage

120
100
80
60
40
20 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0.1
Modulation Index
Figure 3.7. Measured inverter’s load voltages vs. modulation index [108].

600 600 600

400 400 400

Invertter Phase Voltages

Invertter Phase Voltages

Invertter Phase Voltages

200 200 200

0 0 0

-200 -200 -200

-400 -400 -400

-600 -600
0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02 -600
0 0.005 0.01 0.015 0.02

600 600
600

400 400 400

Invertter Line Voltages

Invertter Line Voltages

Invertter Line Voltages

200 200 200

0 0 0

-200 -200 -200

-400 -400 -400

-600 -600 -600

0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02
400 400 400

300 300 300

Invertter Load Voltages

Invertter Load Voltages

Invertter Load Voltages

200 200 200

100 100 100

0 0 0

-100 -100 -100

-200 -200 -200

-300 -300 -300

-400 -400
0 0.005 0.01 0.015 0.02 -400 0 0.005 0.01 0.015 0.02
0 0.005 0.01 0.015 0.02
Harmonic Distortion Load 'a' Harmonic Distortion Load 'a' Harmonic Distortion Load 'a'
200 200 200
Harmonic Spectrum of the Load Voltage

Harmonic Spectrum of the Load Voltage

Harmonic Spectrum of the Load Voltage

180 180 180

160 160 160

140 140 140

120 120 120

100 100 100

80 80 80

60 60 60

40 40 40

20 20 20

0 0 0
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz) Frequency (Hz) Frequency (Hz)

(a) (b) (c)

Figure 3.8. Inverter voltages generated by the conventional switching methods for M =1. From top to the bottom:
inverter phase voltages, inverter line voltages, load voltages and harmonic spectrum of the load voltage for (a)
LSPWM (b) THPWM (c) SVM [108].

37
Chapter IV: Proposed SHE based Fault-Tolerant Strategy
This chapter presents a generalized fault-tolerant strategy to improve the performance of the 3-

phase CHB inverter with faulty cells. The proposed fault-tolerant strategy combines the FPSC

method with half-wave symmetrical SHE to rebalance the inverter voltages and limit the THD of

the waveforms. In this chapter, the main idea is presented as to adjust the phase angles of the

fundamental harmonic of the line-ground voltages while equalizing the amplitudes and phase shifts

of the third order harmonics and eliminating some higher order harmonics. The proposed fault-

tolerant strategy uses the increased degree of freedom provided by half-wave symmetrical SHE to

adjust phase angles and eliminate a wide range of lower order harmonics for limiting the THD of

the inverter voltages in the faulty conditions [109].

To generate balanced line-to-line voltages, the phase shifts between the fundamental harmonics of

the 3-phase voltages should be adjusted according to the obtained values from (2.11) (goal 1).

However, to ensure that the third order harmonics in the phase voltages will cancel out naturally

in the line-to-line voltages, their amplitudes should be made equal and the phase shifts between

them should be made equal to zero degrees (goal 2). Additionally, the amplitude of the remaining

undesirable lower order harmonics should be zeroed (goal 3) [109].

As mentioned before, generating half-wave symmetric voltage waveforms it is possible to

manipulate both amplitude and angle of harmonics and generate unique switching functions for

each phase of the inverters. In order to address the first goal, the following system of equations

can be assembled to adjust the amplitude and angle of the fundamental harmonics according to the

requirements set forth before [109],

38
  M a
 2  A1 phase ( a )

 M b
  A1 phase ( b ) (4.1)
 2
 M c
  A1 phase ( c )
 2

1 phase ( a )  1 phase (b )   ab


1 phase (b )  1 phase ( c )  bc (4.2)

 1 phase ( c )  1 phase ( a )  ca

Where Ma, Mb, and Mc are the modulation indices for the phases ‘a’, 'b', and 'c' by considering the

number of operative cells in each phase of the inverter. By substituting these values into (2.11) the

revised phase shifts between the phase voltages of the inverter are calculated (  ab , bc , and  ca )

for the faulty scenario [109].

The next goal is to manipulate the amplitude and phase of the third order harmonics. As

mentioned, the amplitudes of the third order harmonics need to be made equal, while the phase

shift between them needs to be set to zero degrees. This can be done by solving (4.1)-(4.2) in

conjunction with the following equations [109],

 A3 phase ( a )  A3 phase (b )  A3 phase ( c )


3 phase ( a )  3 phase (b )  0 (4.3)

3 phase ( c )  3 phase ( a )  0

The third goal is to eliminate as much low order harmonics as possible. The low order harmonics

up to the (l-1)th order can be eliminated by solving (4.1)-(4.3) in conjunction with the following

equations [109],

39
 An phase( a )  An phase(b)  An phase( c)  0 for n  5, 7,9,..., l  1 (4.4)

As a result, to reach the three aforementioned goals at the same time, (4.1)-(4.4) should be solved

simultaneously for the switching angles [109].

As mentioned previously, the set of switching angles for each phase is unique to that phase;

therefore, the switching angles for phase 'a' are denoted as (𝛼1 to 𝛼𝑙 ), phase 'b' as (𝛽1 to 𝛽𝑙 ), and

phase 'c' as (𝛾1 to 𝛾𝑙 ) hereinafter. Equations in (4.1)-(4.4) need to be solved according to some

boundary constraints on the switching angles [109],

0   k   k 1  180 k  1, 2,3,..., l (4.5)

0  k  k 1  0  180 k  1, 2,3,..., l (4.6)

0   k   k 1  0  180 k  1, 2,3,..., l (4.7)

The inequality in (4.5) rationalizes that the switching angles for phase 'a' are to be distributed

consecutively in a half period of the switching function starting from zero degrees. Inequalities in

(4.6) and (4.7) convey the same idea except that the starting points for phase 'b' and 'c' (𝛽0 and 𝛾0)

are unknown and thus need to be found while solving (4.1)-(4.4). Nevertheless, since the angle of

fundamental harmonics of phases 'b' and 'c' are being set respectively 𝜃𝑎𝑏 and 𝜃𝑐𝑎 degrees apart

from that of phase 'a', it is expected that the values of 𝛽0 and 𝛾0 be found close to 𝜃𝑎𝑏 and −𝜃𝑐𝑎

degrees [109].

Although it is possible to solve (4.1)-(4.4) according to the constraints in (4.5)-(4.7), the problem

of unknown range of switching angles for phase 'b' and 'c' increases the required computational

40
effort significantly. To alleviate this problem and reduce the overall complexity, an innovative

way of reformulating (4.1)-(4.4) is devised. To reformulate the problem, the three switching

functions for the 3-phases are defined in the range of 0° to 180° and the fundamental harmonics

are placed at the same angle for solving. This is equivalent to making the following modifications

to the original formulation [109],

1 phase ( a )  1 phase (b )  0

 (4.8.a)
1 phase ( c )  1 phase ( a )  0
0   k   k 1  180

0   k   k 1  180 k  1, 2,3,..., l  1 (4.8.b)
0      180
 k k 1

The obtained switching functions are then shifted for 𝜃𝑎𝑏 and −𝜃𝑐𝑎 degrees respectively, to shift

the fundamental harmonics to the desired angles (𝜃𝑎𝑏 and −𝜃𝑐𝑎 ). However, to maintain the phase

shift between the third order harmonics at zero degrees after shifting the switching functions, (4.1)-

(4.4) need to be further modified prior to solving [109].

Subsequent to shifting the obtained switching functions for 𝜃𝑎𝑏 and −𝜃𝑐𝑎 degrees, the third order

harmonics of phase 'b' and 'c' will be placed at 3 × 𝜃𝑎𝑏 and −3 × 𝜃𝑐𝑎 degrees, respectively.

However, it is desirable that these harmonics be placed at ± 360° after shifting. As a result, it is

possible to adjust the angle of these harmonics prior to shifting, such that after shifting, the angles

end up at ± 360°. Adjusting the angles prior to shifting can be carried out according to the

following general formula for the third order harmonic of a waveform [109],

𝜃𝑛𝑒𝑤 = 𝜃𝑜𝑙𝑑 ± 3 × 𝜃𝑠ℎ𝑖𝑓𝑡 (4.9)

Where 𝜃𝑠ℎ𝑖𝑓𝑡 is the amount of desired phase shift of the phase voltages (𝜃𝑎𝑏 for phase ‘b’ and 𝜃𝑐𝑎

41
for phase ‘c’), 𝜃𝑜𝑙𝑑 is the angle of the third harmonic of the waveform before shifting, and 𝜃𝑛𝑒𝑤 is

the angle of the third harmonic of the waveform after shifting. According to (4.9), the angle of the

third harmonic of phase 'b' should be set to 𝜃𝑜𝑙𝑑 = 360 − 3 × 𝜃𝑎𝑏 prior to shifting. Similarly, the

angle of the third harmonic of phase 'c' should be set to 𝜃𝑜𝑙𝑑 = −360 + 3 × 𝜃𝑐𝑎 prior to shifting.

This is equivalent to making the following modifications to the original formulation [109],

3 phase (b )  3 phase ( a )  360  3   ab

(4.10)
3 phase ( c )  3 phase ( a )  360  3  ca

Considering the modifications reflected in (4.8) and (4.10), the final system of equations that needs

to be solved to reach all three aforementioned goals is [109],

 M a
 2  A1 phase ( a )

 M b  A
 2 1 phase ( b )


 M c  A1 phase ( c )
 2
 1 phase ( a )  1 phase ( b )  0

 1 phase ( c )  1 phase ( a )  0
 A3 phase ( a )  A3 phase ( b )  A3 phase( c ) (4.11)

 3 phase ( b )  3 phase ( a )  360  3   ab
   360  3   ca
 3 phase ( c ) 3 phase ( a )
 An  phase ( a )  An  phase ( b )  An  phase ( c )  0 for n  5, 7, 9,..., l  1
According to,
0   k   k 1  180

0   k   k 1  180 k  1, 2,3,..., l  1
 0      180
 k k 1

Similar to conventional SHE, the switching angles are calculated for a range of modulation indexes

using (4.11) prior to Inverter operation and are stored in a look up table on the Inverter’s digital

42
controller. In a practical application, in case of a single fault, the Inverter controller stops using

the normal SHE look up table and uses the look up table generated using (4.11) for fault-tolerant

operation [109].

Now, the fault-tolerant strategy is utilized to revamp the performance of the prototype that is shown

in figure 3.3. In this setup, the dc link terminal voltage of each H-bridge cell is equal to 12 V. The

problem of detecting a fault, finding the location and then taking appropriate action is the basis of

fault-tolerant control. Fortunately, many fault detection methods have been proposed over the last

few years [17]. However, the main challenge in this proposal is limited to take appropriate action

after fault diagnosis. In this dissertation, it is assumed that the type and location of the fault has

been detected by the proposed method in [109].

To provide a reference for comparison of the results throughout the remainder of the proposal, the

phase voltage waveforms for the normal (no fault) operation of the inverter are provided in figure

4.1(a). In addition, the generated line-to-line and load voltages for normal operation with the

conventional SHE are shown in figure 4.1(b) and 4.1(c), respectively. Using this imported data

from the oscilloscope, the amplitude of the fundamental component of the load voltages are

calculated for the normal operation as 41 V [109].

The first scenario analyzes the operation of the proposed method in the event of a single fault in

phase ‘a’ of the inverter. In case of a single faulty H-bridge cell in phase 'a', the voltage of this

phase will be limited to Vag = 2 p.u. while the voltages of phases ‘b’ and ‘c’ can reach to Vbg = Vcg

= 3 p.u. Accordingly, based on (2.11), the phase shift between the fundamental harmonics of the

inverter phase voltages need to be adjusted to 𝜃𝑎𝑏 = 𝜃𝑐𝑎 = 130.5°. These values along with Ma =

2, Mb = Mc = 3 should be substituted in the (4.11) and solved for switching angles. The solution

43
 (a) (b)

(c)
Figure 4.1. The experimental CHB inverter phase voltages in normal operation condition. (a) Inverter’s phase
voltages, (b) line-to-line voltages, and (c) load voltages [109].

for this set of equations is picked as the operating point of the prototype seven-level CHB inverter.

The generated phase voltages and the harmonic spectrum of the phase 'a' voltage of the inverter

for this scenario are shown in the scope shot of figure 4.2 [109].

As pictured, the faulty phase 'a' generates five voltage levels while the healthy phases generate all

seven-voltage levels. Due to the space limitations, the actual raw data from oscilloscope is

exported to MATLAB to generate more clear figures in small for the harmonic spectrum analysis.

The inverter’s phase, line-to-line and load voltages, as well as the harmonic spectrum of all three

load voltages, are plotted in figure 4.3. According to this figure, due to a fault in phase 'a', the

phase voltages are not balanced, as expected. However, according to the timings marked between

44
 Vbg Vcg
Vag

Fundamental
Harmonic

Third
Harmonic Eliminated
Harmonics

Figure 4.2. The experimental CHB Inverter voltages in the event of a single fault at phase 'a'. Top: Inverter phase
voltages. Bottom: Harmonic spectrum of phase 'a' voltage [109].

the three waveforms, the phase shifts between the waveforms very accurately match the intended

values of 𝜃𝑎𝑏 = 𝛼 = 130.5° , 𝜃𝑐𝑎 = 𝛾 = 130.5°, and 𝜃𝑏𝑐 = 𝛽 = 99 ° [109].

This confirms the competence of the proposed modified SHE strategy for manipulation of the

harmonic angles. The harmonic spectrum for the frequency range of 100 Hz to 800 Hz is illustrated

in separate zoomed-in windows in figure 4.3(d) for better visualization. According to the zoomed-

in plots, the amplitude of the third order harmonics in the 3-phase to ground voltages are equal as

intended and these harmonics are eliminated in the load voltages [109].

Additionally, the low order harmonics up to 750 Hz are eliminated as planned. It must be noticed

that there are three different voltages in which even the number of operating cells are not equal. It

is really normal that the generated voltages have different waveforms with differ switching

transients. It must be expected that the harmonic spectrums differ from the other phases. The THD

of the phase voltages are calculated from the harmonic spectrum by MATLAB. The calculated

THD for the load voltages is limited to 10.5% [109].

45
 Inverter’s Phase Voltage ‘ag’ (30 V/Div) Inverter’s Line Voltage ‘ab’ (75 V/Div)

120° = 6.6 mS
130.5° = 7.25 mS
Inverter’s Phase Voltage ‘bg’ (30 V/Div) Inverter’s Line Voltage ‘bc’ (75 V/Div)

120° = 6.6 mS
99° = 5.5 mS
Inverter’s Phase Voltage ‘cg’ (30 V/Div)
Inverter’s Line Voltage ‘ca’ (75 V/Div)

(a) (b)

Inverter’s Load Voltage ‘an’ (30 V/Div)

120° = 6.6 mS

Inverter’s Load Voltage ‘bn’ (30 V/Div)

120° = 6.6 mS

Inverter’s Load Voltage ‘cn’ (30 V/Div)

(c)
45 45 45
Harmonic Spectrum for Vag Harmonic Spectrum for Vbg 40
Harmonic Spectrum for Vcg
40 40
Harmonic Distortion Phase Distortion
'a' Harmonic Distortion Phase 'b' Harmonic Distortion Phase 'c'Distortion Phase 'c'
Harmonic Distortion Phase 'a'
35 77
Harmonic Distortion Phase 'b'
7 35
Harmonic Distortion Phase 'c' Harmonic Phase 'a'
7 7
Harmonic
35
Distortion Phase 'b'
77 7
Harmonic

7
7
77
66
6 6 66 6

30 Third harmonic
6
30 6
66 Third harmonic 30 Third harmonic
Amplitude

55 5 5 55 is 5almost 5.5 V
is almost 5.5 V 5
5
55 is almost 5.5 V
5

25 25 25 44
44 4
4 44
4 4 4
4

20 33
3 20 33 3 20 3
33
3 3 3

22 2 2 22 2 2 22 2
2
15 15 15
11 1 1 11 1
1 11 1
1

0 10 0 0
10 0
200
0
300 400
200 500
300 600
400 700
500 800
600
0
200
700 800
0
300 400
200 500
300 600
400
10 700
500 800
600
0
200
700 300
800
0
400
200 500
300 600
400 700
500 800
600 700 800
200 300 400 500 600 700 800 200 300 400 500 600 700 800 200 300 400 500 600 700 800
Frequency (Hz) Frequency (Hz) Frequency (Hz) Frequency (Hz) Frequency (Hz) Frequency (Hz)
Frequency (Hz) Frequency (Hz) Frequency (Hz)

5 5 5

00 0 00 500 Harmonic1000 1500 2000

500Harmonic1000
Distortion Load1500
'an' 2000 0 500 Harmonic1000 1500
Distortion Load 'bn' 2000 Distortion Load 'cn'
70 70 70
Harmonic Spectrum for Van Harmonic Spectrum for Vbn Harmonic Spectrum for Vcn
60 60 60

50 4.54.5
Harmonic Distortion
Harmonic Load
Distortion 'an' 'an'
Load
4.5 40 50
Harmonic Distortion
Distortion Load
Load 'cn'
'cn'
40
4.5
Harmonic
Harmonic Distortion Distortion
Load 'bn' Load 'bn'
4.5 50
Harmonic Distortion Load 'an'
4.5
Harmonic Distortion Load 'cn'
4.5
Harmonic Distortion Load 'bn'

4 4 4 4 4 4
35 35 4
Amplitude

3.53.5 3.5 3.5 3.5 3.5 3.5

40 3 3 3
30
40 30

3 3
40 3 3
25 25

2.52.5 2.5 2.5 2.5

Amplitude

2.5 2.5
20 20

30 2 2 2

15
30 15
2 2
30 2 2

1.51.5 1.5 1.5 1.5 1.5 1.5

10 10
1 1 1 1 1 1 1

20 0.50.5 0.5
5
20 5
0.5 0.5
20 0.5 0.5

0 0 0 0 00 0 0 0
200 200 300 300 400 400 500 500 600600 700700 800800 200 0 300 1 4002 5003 4
600 5
700 800 0 1
200 2
300 3
400 4500 5600 700 800 200 300 400 500 600 700 800 200 300 400 500 600 700 800 200 300 400 500 600 700 800
Frequency (Hz) Frequency (Hz) 4 Frequency (Hz) 4
Frequency (Hz) Frequency (Hz) Frequency (Hz)
Frequency (Hz) Frequency (Hz) x 10 Frequency (Hz)x 10
10 10 10

0 0
0 500 1000 1500 2000 0 500 1000 1500 2000 00 500 1000 1500 2000
Frequency (Hz) Frequency (Hz) Frequency (Hz)
(d)
Figure 4.3. The experimental CHB Inverter waveforms in the event of a single fault at phase 'a' (first Scenario): (a)
Inverter phase voltages, (b) line-to-line voltages, (c) load voltages, and (d) the harmonic spectrum of the phase and
load voltages [109].

46
The amplitude of the load voltages are all equal (36.3 V) and the phase shift between the voltage

waveforms are also equal (120°). This confirms the validity of the proposed fault-tolerant strategy

for generating balanced line-to-line voltages in the event of a bypassed faulty H-bridge. In

addition, the third order harmonics are eliminated naturally in the line voltages. This confirms the

proper placement of the third harmonic angles by the aforementioned innovative reformulation of

the SHE problem [109].

The second scenario analyzes the operation of the proposed method in the event of two faults, one

in phase ‘b’ and another in phase ‘c’. In this condition, the phase shifts of the inverter phase

voltages needs to be adjusted to 𝜃𝑎𝑏 = 𝛼 = 101.5° , 𝜃𝑐𝑎 = 𝛾 = 101.5°, and 𝜃𝑏𝑐 = 𝛽 = 157 °. To

emulate the fault condition, one switch in phase 'b' and another one in phase ‘c’ were manually

short circuited at t = t0. The faulty H-bridge cells are bypassed, and the fault-tolerant strategy is

applied at t = t1. The generated voltage waveforms in this fault scenario are shown in figure 4.4.

According to this figure, in the post-fault condition the amplitude of the phase ‘a’ voltage is equal

to 36 V, while the amplitudes of the voltages in the other two phases are equal to 24 V. However,

the phase shifts between the waveforms are accurately adjusted to 𝜃𝑎𝑏 = 𝛼 = 130.5°, 𝜃𝑐𝑎 = 𝛾 =

130.5°, and 𝜃𝑏𝑐 = 𝛽 = 99 °. Consequently, balanced load voltages with equal amplitudes of 30.4

V and phase shift of 120° are generated [109].

In the next scenario, the operation of the proposed method in the event of multiple faults in one

phase is investigated. In this scenario, there are two faulty cells in phase ‘a’. In this condition, the

phase shifts of the inverter phase voltages need to be adjusted to 𝜃𝑎𝑏 = 𝛼 = 140° , 𝜃𝑐𝑎 = 𝛾 =

140°, and 𝜃𝑏𝑐 = 𝛽 = 80 °.. The generated inverter waveforms in this fault scenario are shown in

figure 4.5. As pictured, the phase shifts between the phase voltages are correctly adjusted to

47
 Inverter’s Phase Voltage ‘bg’ (30 V/Div) Inverter’s Line Voltage ‘bc’ (75 V/Div)

120° = 6.6 mS
157° = 8.72 mS
Inverter’s Phase Voltage ‘cg’ (30 V/Div) Inverter’s Line Voltage ‘ca’ (75 V/Div)

120° = 6.6 mS
Inverter’s Phase Voltage ‘ag’ (30 V/Div)
101.5° = Inverter’s Line Voltage ‘ab’ (75 V/Div)
5.63 mS

(a) (b)
Inverter’s Load Voltage ‘cn’ (30 V/Div)

120° = 6.6 mS
Inverter’s Load Voltage ‘an’ (30 V/Div)

120° = 6.6 mS
Inverter’s Load Voltage ‘bn’ (30 V/Div)

(c)
Harmonic Spectrum for Van Harmonic Spectrum for Vbn Harmonic Spectrum for Vcn
40 40 40

35 35 35

30 30 30

25 25 25
Amplitude

20 20 20

15 15 15

10 10 10

5
Eliminated 5
Eliminated 5 Eliminated
Range Range Range
0 0 0
00 500
100 1000
200 1500
300 2000
400 0 500
100 1000
200 1500
300 2000
400 0 500
100 1000
200 1500
300 2000
400
Frequency (Hz) Frequency (Hz) Frequency (Hz)
(d)
Figure 4.4. The experimental CHB Inverter waveforms in the event of a fault at phase 'b' and a fault at phase ‘c’
(second scenario). (a) Inverter phase voltages, (b) line-to-line voltages, (c) load voltages, and (d) the harmonic
spectrum of the load voltages [109].

generate balanced line-to-line voltages. Also, balanced load voltages with equal amplitudes of 28.7

V and phase shift of 120° are generated [109].

The worst-case fault scenario is when different number of healthy cells remain in each phase. For

instance, in the event of a single fault in phase ‘a’, and double faults in phase ‘b’, the faulty H-

bridges in these phase are bypassed which limits the obtainable voltage levels by phase ‘a’ and

48
 Inverter’s Phase Voltage ‘ag’ (30 V/Div)

140° = 7.77 mS Inverter’s Line Voltage ‘ab’ (75 V/Div)

Inverter’s Phase Voltage ‘bg’ (30 V/Div)

120° = 6.6 mS

Inverter’s Line Voltage ‘bc’ (75 V/Div)

101.5° =
Inverter’s Phase Voltage ‘cg’ (30 V/Div) 5.63 mS
120° = 6.6 mS

Inverter’s Line Voltage ‘ca’ (75 V/Div)

(a) (b)
Inverter’s Load Voltage ‘an’ (30 V/Div)

120° = 6.6 mS
Inverter’s Load Voltage ‘bn’ (30 V/Div)

120° = 6.6 mS
Inverter’s Load Voltage ‘cn’ (30 V/Div)

(c)
Harmonic Spectrum for Van 40 Harmonic Spectrum for Vbn 40 Harmonic Spectrum for Vcn
40

35 35 35

30 30 30

25 25 25

20 20 20

15 15 15

10 10 10
Eliminated Eliminated Eliminated
5 5 5
Range Range Range
0 00 0
00 500
100 1000
200 1500
300 400 0
2000 500
100 1000
200 1500
300 400 0
2000 500
100 1000
200 1500
300 2000
400
Frequency (Hz) Frequency (Hz) Frequency (Hz)
(d)
Figure 4.5. The experimental CHB Inverter phase voltages in the event of double faults at phase 'a' (Third
Scenario). (a) Inverter’s phase voltages, (b) line-to-line voltages, (c) load voltages, and (d) the harmonic spectrum of
the load voltages [109].

phase ‘b’ to -2 to 2 p.u and -1 to 1 p.u, respectively [109].

As mentioned before, the obtainable voltage levels by the healthy phase (‘c’) ranges from –3 to 3

49
p.u. Setting Va, Vb, and Vc respectively to 2, 1, and 3 p.u. in (2.11), yields the modified phase

angles required to generate balanced line voltages, 𝜃𝑎𝑏 = 𝛼 = 179° , 𝜃𝑏𝑐 = 𝛽 = 108 °, and 𝜃𝑐𝑎 =

𝛾 = 73°. The last experiment analyzes the occurrence of this worst faulty scenario. In this

experiment, one switch in phase ‘a’ and two switches in phase ‘b’ are manually short circuited to

emulate the fault condition. In this case, the phase shifts of the inverter phase voltages need to be

adjusted to the calculated values. As mentioned above, the fault-tolerant strategy bypasses the

faulty cells and modifies the phase angles to generate balanced line voltages. The generated

voltage waveforms for this experiment are shown in figure 4.6. The balanced load voltages with

equal amplitudes of 27 V and phase shift of 120° are generated [109].

For all of the mentioned scenarios, the maximum achievable line voltages both in per unit system

and in Volts are given in Table. II for the proposed fault-tolerant method as well as the FPSC-

PWM method. For the faulty scenarios in which two phases of the Inverter have the same number

of operative cells, the maximum achievable voltage in per unit system of the inverter is almost

equal to what is reported in the literature for a PWM based FPSC method [12]. However, since the

base voltage in SHE is more than PWM based methods (because of more dc link utilization or

wider linear modulation range in SHE), the absolute value of maximum achievable line voltage

using the proposed method (62.8 V) is more than the conventional PWM based FPSC method

(55.4 V in [12]) in the event of a single faulty cell [109].

Table II. The Comparison of the Proposed Method with the Conventional FPSC-PWM method [109]
The Proposed Method The FPSC- PWM
Number of Number of Number of VL-L (P.U.) VL-L (V) VL-L (P.U.) VL-L (V) When
Operative Operative Operative When DC DC Link Voltage
Cells in Cells in Cells in Link Voltage = 12V.
Phase ‘a’ Phase ‘b’ Phase ‘c’ = 12V.
3 3 2 4.59 62.8 4.56 55.4
3 2 2 3.94 52.6 3.92 46.6
3 3 1 3.83 49.7 3.82 44
3 2 1 3.41 46.7 2.65 32.39

50
 Inverter’s Phase Voltage ‘bg’ (30 V/Div) Inverter’s Line Voltage ‘ab’ (75 V/Div)

179° = 9.94 mS
120° =
Inverter’s Phase Voltage ‘ag’ (30 V/Div) 6.6 mS

Inverter’s Line Voltage ‘ca’ (75 V/Div)

120° =
73° = 6.6 mS
4.05 mS
Inverter’s Phase Voltage ‘cg’ (30 V/Div)

Inverter’s Line Voltage ‘bc’ (75 V/Div)

(a) (b)

Inverter’s Load Voltage ‘an’ (30 V/Div)

120° = 6.6 mS
Inverter’s Load Voltage ‘bn’ (30 V/Div)

120° = 6.6 mS
Inverter’s Load Voltage ‘cn’ (30 V/Div)

(c)
Harmonic Spectrum for Van 40 Harmonic Spectrum for Vbn 40 Harmonic Spectrum for Vcn
40

35 35 35

30 30 30

25 25 25

20 20 20

15 15 15

10 10 10
Eliminated Eliminated Eliminated
5 5 5
Range Range Range
00 00 00
00 500
100 1000
200 1500
300 2000
400 0 500
100 1000
200 1500
300 400 00
2000 500
100 1000
200 1500
300 2000
400
Frequency (Hz) Frequency (Hz) Frequency (Hz)
(d)
Figure 4.6. The experimental CHB Inverter phase voltages in the event of double faults at phase 'a' and double
faults in phase ‘b’ (Fourth Scenario). (a) Inverter’s phase voltages, (b) line-to-line voltages, (c) load voltages, and
(d) the harmonic spectrum of the load voltages [109].

According to this Table, in the last scenario which is the investigation of completely asymmetrical

phases, the number of operative cells in each individual phases are unique values (the main

contribution of this proposal). The reason for different per unit values of obtained line voltages for
51
these two methods is the different values of calculated modified phase shifts in the SHE method

compared. Because of less flexibility provided by the PWM method, the calculated phase shifts in

the SHE method are not valid for the PWM method and if they are used in the PWM method the

load voltages contain a huge third and fifth order harmonics [109].

52
Chapter V: Proposed SVM based Fault-Tolerant Strategy
In this chapter, without loss of generality, the proposed modified SVM method is presented by

describing its application to a CHB inverter. The proposed technique modifies the conventional

SVM to implement the (FPSC) fault-tolerant strategy for an inverter with one or more faulty

switches [94].

As mentioned previously, so far the FPSC strategy has not been implemented using the SVM

technique. This is due to the particular mechanics of the SVM algorithm that make it difficult to

generate unbalanced phase-ground voltages. In this chapter, a modified SVM technique is

proposed that can be employed to implement the FPSC strategy for a MLI with a faulty phase.

The proposed SVM technique uses an altered space vector diagram and a reshaped path for the

rotation of the reference vector to generate phase-ground voltages with modified phase angles and

different amplitudes. The space vector diagram for the proposed method is structured by revising

(2.11) according to the modified phase angles. Working off the previous example and assuming

𝜃𝑎𝑏 =𝜃𝑐𝑎 =α and 𝜃𝑏𝑐 = β for a certain fault scenario, (2.2) is revised to [94],

V   Vag  Vbg e j  Vcg e j (5.1)

to shape a restructured space vector diagram for the inverter in the faulty condition.

⃗⃗⃗⃗′ ), all the possible switching states of the inverter (Sa, Sb, and
To generate the new space vectors (𝑉

Sc) in the faulty condition are substituted in (2.3) to find all the possible voltage states for the 3-

phases (Vag, Vbg, and Vcg) in the faulty condition. Then these voltages are substituted in (5.1) to

find the new space vectors. The restructured space vector diagram created using (5.1) for the

previous example is pictured in figure 5.1. As illustrated in figure 5.1, the space vector diagram

53
for the faulty inverter no longer resembles the conventional space vector diagram used by

traditional SVM algorithms [94].

There are three key distinctions to this new space vector diagram. First, the ‘b’ and ‘c’ axes are

replaced by ‘b′’ and ‘c′’ axes. The angle between the two new axes is changed to 𝜃𝑏𝑐 = β. Second,

the location of each new space vector (dots in figure 5.1) is different than in its conventional

counterpart. Third, unlike the conventional case, the redundant states are mapped to dispersed

space vectors. In other words, for each redundant state a distinct space vector is generated using

(5.1) [94].

The reshaped path for the rotation of the reference vector is found by transforming the desired 3-

phase voltages in the faulty condition to the stationary α-β reference frame using a modified

transformation. Again, working off the previous example and assuming a faulty H-bridge in phase

‘a’ for a certain fault scenario, the amplitude of the voltage generated by phase ‘a’ is reduced for

a (𝑚 − 1)⁄𝑚 factor. Accordingly, based on the FPSC method, the ‘b’ and ‘c’ phase shifts need

to be revised to 𝜃𝑎𝑏 =𝜃𝑐𝑎 =α in order to generate balanced line-line voltages. As a result, the desired

3-phase voltages that the inverter needs to generate in the faulty condition are (normalized to Vdc)

[94],

 * m 1
Vag  M  m  cos( wt )

 V *  M  cos( wt   ) (5.2)
 bg*
 Vcg  M  cos( wt   )

A modified α-β transformation is required to transform the set of unbalanced 3-phase voltages in

(5.2) to the stationary α-β reference frame. The standard α-β transformation is modified to the

54
following transformation for this purpose [94],

 
V  1 cos( ) cos( )  Vag* 
*

    * 
g

V*
 
g   0 sin(  ) sin(  )  Vbg  (5.3)
V 
*  1 1  V * 
  1
0g   cg 
 2cos( ) 2cos( ) 

substituting (5.2) in (5.3) yields the desired voltages in the stationary α-β reference frame [94],

V*g  A cos(wt )
 * (5.4)
V g  B sin( wt )

where [94],

  m  1  2M cos2 
A  M  
 m . (5.5)
 B  2M sin 2  


By careful inspection of (5.3) one can realize [94],

Vqg* 2 Vdg* 2
  1. (5.6)
A2 B 2

This equation describes an elliptical shape with major and minor axes coinciding with the

stationary α-β axes. In polar coordinates, with the origin at the center of the ellipse and angular

coordinate wt measured from the ellipse’s major axis, the rotating path can be described as [94],

55
 β-axis

b'-axis

α-axis
a-axis

c'-axis

Figure5.1 The elaborated space diagram and all of its possible space vectors for a seven-level inverter one faulty cell
in phase ‘a’ (the modified phase shift is α=130.5°) [94].

AB
*
V  e jwt . (5.7)
 A cos(wt )   ( B sin( wt )) 2
2

Suggesting that after the fault occurrence the reference vector for the SVM algorithm should be

made to follow the elliptical path described by (5.7), rather than the conventional circular path.

The elliptical path for the previous example is shown in figure 5.1 in red [94].

Other than restructuring of the space vector diagram and following a modified elliptical reference

vector path, the rest of the modified SVM implementation remains the same as the conventional

SVM. As illustrated in figure 5.2, the modified SVM algorithm needs to find the three nearest

voltage vectors to the reference vector in each step and switch between the three identified voltage

vectors during one switching period (Tsw). The amount of time spent at each space vector can be

found from (2.6) similar to conventional SVM. As mentioned previously, by using (5.1) the

redundant states generate distinct space vectors for the faulty inverter. Consequently, the three

identified nearest voltage vectors can be realized each with a unique inverter switching state.

Meaning that the SVM algorithm is no longer required to choose an appropriate switching state
56
 b'-axis

a-axis

B
w

c'-axis

Figure 5.2. The modified space vector diagram of an n-level inverter in faulty condition. The axes angles and rotating
vector are modified according to the proposed method to generate balanced line-to-line voltages with less voltage
reduction [94].

among the redundant states for a space vector. In fact, in the proposed method, the state

redundancy capacity of the inverter is leveraged for the fault-tolerant operation of the inverter to

squeeze more voltage vectors along the elliptical path of the reference vector [94].

Using the proposed method, the three nearest voltage vectors no longer shape equilateral triangle

anymore. However, the shape of these triangles is not important for calculating the time spent at

each of the vector. As mentioned above, the procedure for calculating the time spent at each vector

⃗⃗⃗𝑥 , ⃗⃗⃗
is the same as conventional SVM. In (2.6), the coordinates of three nearest vectors (𝑉 𝑉𝑦 and ⃗⃗⃗
𝑉𝑧

which are not vertices of an equilateral), are used in the coefficients matrix and the coordinates of

the reference vector is used in the constant matrix of the system. As long as the reference vector is

located inside this triangle, this system of equations has a valid solution which satisfies the

practical constraints (0 ≤ Ti ≤ Tsw,i = x, y, z) [94].

In the previous example it was assumed that the faulty phase of the inverter was phase ‘a’ and the

restructured space vector diagram and the reshaped rotating path in figure 5.1 were derived

accordingly. However, in general, the fault can occur on any of the 3-phases of the inverter.

57
 b-axis
b-axis
b'-axis

a-axis a-axis

a'-axis

c'-axis
c-axis
c-axis c'-axis
(a) (b)
b'-axis
b-axis

a'-axis

a-axis

c-axis

(c)
Figure 5.3. The modified space vector diagram of MLI in different faulty conditions: (a) one faulty cell in phase ‘a’,
(b) one faulty cell in phase ‘b’, and (c) one faulty cell in phase ‘c’. (Only one of the switching redundancies for each
space vector of normal operation is transferred to ‘abc’ plane to decrease the complexity of the space vector diagrams)
[94].

Correspondingly, the provided formulation in this chapter can be adapted to accommodate a fault

occurrence on any of the phases. The restructured space vector diagram and reshaped rotating

path for fault occurrence on each of the 3-phases of the inverter are compared in figure 5.3 [94].

At the end of this section, it is worth mentioning that the proposed fault-tolerant strategy is only

applicable to a faulty inverter with equal number of operative cells in at least two phases.

Considering a completely asymmetric faulty condition where the number of operative cells in

phase ‘a’, ‘b’ and ‘c’ are three, two and one, respectively the revised phase shift angles

(𝜃𝑎𝑏 , 𝜃𝑏𝑐 , 𝜃𝑐𝑎 ) cannot be equal. Therefore, the reshaped reference path is not elliptical anymore

and the proposed cannot be used. However, to work around this fault scenario, one of the operative

cells in phase ‘a’ can be simply bypassed to make the number of operative cells in two phases

(phases ‘a’ and ‘b’) equal. Subsequently, the proposed method can be easily applied to the inverter

58
[94].

Now, the performance of the proposed modified SVM method is compared to the conventional

fault-tolerant strategy of bypassing additional cells in the healthy phases of the inverter. The

performance comparison is provided in terms of both the maximum achievable voltage by the

inverter and the maximum inverter capacity utilization for power conversion in the faulty

condition. To examine the maximum achievable voltage by the inverter in the faulty condition, the

maximum feasible modulation index for the two methods should be compared. In case of no fault,
3
the voltages are generated using the reference vector of (2.5). The term 2 𝑚 in (2.5) is the radius

of the circular path of the reference vector. Since the circular path must remain inside the

hexagonal shaped boundary of the space vector diagram shown in figure 2.3, its maximum radius

value is equal to the radius of the inscribed circle of the hexagonal. The radius of the inscribed

√3(𝑛−1)
circle is equal to the apothem of the hexagonal, which is equal to for an n-level inverter
2

[17]. As a result, the maximum feasible voltage (normalized to Vdc) for the healthy inverter is equal

to [94],

n  1 2m
Vmax   (5.8)
3 3

In case of a fault occurrence in one of the phases, if additional cells are bypassed in the two healthy

phases to generate balanced voltages according to the conventional fault-tolerant method, the

hexagonal boundary of the space vector diagram is shrunk such that the length of its apothem is

√3(𝑛−1)
reduced to . As a result, the maximum feasible voltage using the conventional strategy is
2

equal to [94],

59
 n  3 2  m  1
V 'max   (5.9)
3 3

When using the proposed modified SVM to mitigate the fault, the maximum feasible voltage can

be found by substituting (m-1) p.u., m p.u., and m p.u. in (2.11) for Vag, Vbg, and Vcg , respectively

[94].

2 2
''
Vmax  m  m2  2m2 cos  (5.10)
3

Using (5.10) to modify phase angles leads to reduction of phase shifts between the healthy phases

(β) making the values less than 120° (the phase shifts in normal operation) and thus increase of α

to a value more than 120°. As a result, it can be concluded that [94],

V 'max  V "max  Vmax (5.11)

which means the maximum achievable voltage by the inverter using the proposed method is higher

than that achieved from the conventional bypass method [94].

To compare the maximum inverter capacity utilization, the area enclosed by the rotating reference

vector in the two methods should be compared. To this end, the space vector diagrams and the

path of the reference vectors for the healthy inverter, faulty inverter operating with the

conventional fault-tolerant method, and the faulty inverter operating with the proposed method are

plotted on the same graph in figure 5.4. In this figure, the black dots show the conventional space

vector diagram of the inverter, the red dots show the restructured space vector diagram, the large

green circle shows the largest possible circular path for the healthy inverter, the small blue circle

60
 b-axis b-axis
b'-axis

a-axis

a-axis

a'-axis

c'-axis
c-axis c-axis l=n-1

c'-axis
(a) (b)
b-axis b'-axis

a'-axis

a-axis

c-axis
(c)
Figure 5.4. Comparison of the rotating reference vectors: (a) one faulty cell in phase ‘a’, (b) one faulty cell in phase
‘b’, and (c) one faulty cell in phase ‘c’. The green path represents the normal operation with n voltage levels in each
phase. The blue path represents the faulty condition, the faulty cell, and two healthy cells bypassed. The red path is
the modified rotating vector according to the proposed method. The black dots represent the space vectors in ‘abc’
plane and the red dots represents the transformed dots in ‘abc’ plane [94].

shows the largest possible circular path for the faulty inverter operating with the conventional

fault-tolerant method, and the elliptical path shows the largest possible path for the faulty inverter

operating with the proposed method [94].

According to figure 5.4, not only is the area enclosed by the elliptical path greater than the area

enclosed by the blue circle, but also, more red space vectors are squeezed into the elliptical path.

This means more inverter states are utilized for power conversion using the proposed method. To

quantify the findings from figure 5.4, a utilization factor for the inverter is defined as the square

root of the ratio of the area enclosed by the largest possible reference vector path to the area of the

hexagonal that circumscribes the path [94],

61
 Apath
PEF  (5.12)
Ahexagonal

This utilization factor can be calculated for different fault-tolerant strategies to compare the

inverter capacity utilization. Assuming, the area of the hexagonal inscribed by the large circle,

small circle, and ellipse in figure 5.4 are termed as Ahh, Ahf, and Ahp and the area of the large circle,

small circle, and the ellipse are termed as Alc, Asc, and Ael respectively, the utilization factor for the

healthy inverter, the faulty inverter operating with the conventional fault-tolerant method, and the

faulty inverter operating with the proposed method are [94],


 A 
PEF1  lc 
 Ahh 2 3

 Asc   m 1 
2

 PEF2     (5.13)
 Ahf 2 3 m 

 Ael    m  1  2m cos 2    sin( )
 PEF3  
 Ahp 3m 1  cos   

The results in (5.13) are found by simple geometric analysis of the shapes in figure 5.4. According

to (5.13), PEF1 for the healthy inverter is always constant, PEF2 for the conventional method

depends only on the number of H-bridge cells (m), and PEF3 for the proposed method depends on

both the number of H-bridge cells (m) and the modified phase angle (α) in the faulty condition.

Therefore, PEF1, PEF2, and PEF3 should be compared based on the number of the cells and the

modified phase angle. Figure 5.5 compares PEF1, PEF2, and PEF3 for a scenario of a single fault

in one phase of an inverter with m H-bridge cells. According to this figure, for any number of

cells [94],

62
 Inverter’s Phase Voltage ‘a’ (120 V/Div)

Inverter’s Phase Voltage ‘b’ (120 V/Div)

Inverter’s Phase Voltage ‘c’ (120 V/Div)

Normal Operation t0 Faulty t1 Post-Fault Operation

Figure 5.6. The experimental CHB inverter phase voltages in normal operation of the inverter ( t  t0 ), during a
single fault ( t0  t  t1 ), and with a conventional fault-tolerant strategy ( t  t1 ) [94].

PEF 2  PEF 3  PEF1 (5.14)

In this chapter, the proposed fault-tolerant strategy is utilized to revamp the performance of the

prototype that is shown in figure 3.3. In this setup, the dc link terminal voltage of each H-bridge

cell is equal to 48 V and the output terminals of the CHB inverter are connected to a balanced 3-

phase load. To provide a reference for comparison of the results throughout the remaining of the

chapter, the waveforms for the normal operation of the inverter and the operation with a

conventional fault-tolerant strategy are provided in figure 5.6. To emulate the fault condition, one

of the switches in phase 'b' of the inverter is manually short circuited at t = t0. Subsequently the

H-bridge cell containing the faulty switch is bypassed, and the conventional fault-tolerant strategy

is applied at t = t1. The generated phase voltages of the inverter for normal operation (t ≤ t0),

during the faulty operation (t0 ≤ t ≤ t1), and for the post-fault operation (t ≥ t1) with the conventional

method are shown in figure 5.6. The amplitude of the fundamental component of the line-to-line

voltages are calculated for normal and post-fault operation as 274 V and 181 V, respectively [94].

The first scenario analyzes the operation of the proposed method in the event of a single fault in

phase ‘a’ of the inverter. In this condition, the number of operative cells in phase ‘a’, ‘b’, and ‘c’

63
are equal to two, three, and three respectively (Va = 2 p.u., Vb = Vc = 3 p.u.). In this case, based on

(2.11), the phase shifts between the inverter phase voltages needs to be adjusted to 𝜃𝑎𝑏 = 𝜃𝑐𝑎 =

𝛼 = 130.5° [94].

As pictured in figure 5.6, during the normal operation the phase voltages reach all seven levels,

while after fault occurrence phase ‘a’ only reaches six voltage levels. In the post-fault condition

which is shown in figure 5.7(a), due to bypassing of a cell in phase 'a', this phase generates five

voltage levels, while the healthy phases keep generating all seven voltage levels. In this condition,

the amplitude of the phase ‘a’ voltage is equal to 108 V, while the amplitudes of the voltages in

the healthy phases ‘b’ and ‘c’ are equal to 161 V and 163 V, respectively. According to the timings

marked between the three waveforms in the post fault condition, by applying the proposed method,

the phase shifts between the waveforms are accurately adjusted to the intended values of 𝜃𝑎𝑏 =

𝜃𝑐𝑎 = 𝛼 = 130.5° and 𝜃𝑏𝑐 = 𝛽 = 99°. This confirms the competence of the proposed modified

SVM strategy for manipulation of the phase shifts [94].

To verify generation of balanced line-to-line voltages in the post-fault condition, the line-to-line

voltages were traced by the oscilloscope, and similar to before, the raw data were imported to

MATLAB to plot figure 5.7(b). Additionally, the harmonic spectrum of the line-to-line voltages

were generated and shown in figure 5.7(c). According to these figures, the amplitudes of the line

voltages are all equal to 246 V, and the phase shifts between the voltage waveforms are all equal

to 120°. This confirms the capability of the proposed fault-tolerant strategy for generating

balanced line-to-line voltages in the event of a bypassed faulty H-Bridge [94].

64
 Post Fault Operation

+100
-100
+150

-150
+150

-150
t1

130.5°
130.5°

0.155 0.16 0.165 0.17

(a)
Post Fault Operation
+300

-300
+300

-300
+300

-300
1000

500
120°
0

120°
-500

-1000
0.12 0.125 0.13

Harmonic Spectrum of Vca

(b)
Harmonic Spectrum of Vbc Harmonic Spectrum Vab
300 300 300

250 250 250

200 200 200

Amplitude
Amplitude

Amplitude

150 150 150

100 100 100

50 50 50

0 0 0
0 5000 10000 15000 20000 0 5000 10000 15000 20000 0 5000 10000 15000 20000
Frequency (Hz) Frequency (Hz) Frequency (Hz)

(c)
Figure 5.7. The experimental CHB inverter voltages in the event of a single fault at phase 'a' (first scenario): (a) inverter
phase voltages, (b) inverter line voltages and (c) the harmonic spectrum of the line voltages in post fault operation
[94].

The second scenario analyzes the operation of the proposed method in the event of two faults, one

in phase ‘b’ and another in phase ‘c’. In this condition, the phase shifts of the inverter phase

65
 Post Fault Operation
+150

101.5°
-150

+100

-100
157°

+100

-100

0.1 0.12
(a)
Post Fault Operation
+300

-300 120°

+300

-300
120°

+300

-300
0.1 0.12
(b)
Harmonic Spectrum of Vab Harmonic Spectrum of Vbc Harmonic Spectrum of Vca
300 300 300

250 250 250

200 200 200

Amplitude

Amplitude

Amplitude

150 150 150

100 100 100

50 50 50

0 0 0
0 5000 10000 15000 20000 0 5000 10000 15000 20000 0 5000 10000 15000 20000
Frequency (Hz) Frequency (Hz) Frequency (Hz)

(c)
Figure 5.8. The experimental CHB inverter voltages in the event of double faults at phases ‘b’ and ‘c’ (second
scenario): (a) inverter phase voltages and (b) inverter line voltages, and (c) the harmonic spectrum of the line
voltages in post fault operation [94].

voltages needs to be adjusted to ab  ca    101.5 [94].

To emulate the fault condition, one switch in phase 'b' and another one in phase ‘c’ was manually

short circuited at t = t0. The faulty H-bridge cells are bypassed, and the fault-tolerant strategy is

applied at t=t1. The generated voltage waveforms in this fault scenario are shown in figure 5.8.

According to this figure, in the post-fault condition the amplitude of the phase ‘a’ voltage is equal

to 145 V, while the amplitudes of the voltages in the other two phases are equal to 97 V. However,

the phase shifts between the waveforms are accurately adjusted to ab  ca    101.5 and

66
 Post Fault Operation

+50
-50 140°

+150

80°
-150
+150

-150
0.1 0.12
(a)
Post Fault Operation
+300

-300 120°

+300

-300
120°
+300

-300
0.1 0.12
(b)
Harmonic Spectrum of Vab Harmonic Spectrum of Vbc Harmonic Spectrum of Vca
300 300 300

250 250 250

200 200 200

Amplitude

Amplitude
Amplitude

150 150 150

100 100 100

50 50 50

0 0 0
0 5000 10000 15000 20000 0 5000 10000 15000 20000 0 5000 10000 15000 20000
Frequency (Hz) Frequency (Hz) Frequency (Hz)
(c)
Figure 5.9 .The experimental CHB inverter voltages in the event of double faults at phase ‘a’ (third scenario): (a)
inverter phase voltages and (b) inverter line voltages, and (c) the harmonic spectrum of the line voltages in post
fault operation [94].

bc    157 . Consequently, balanced line-to-line voltages with equal amplitudes of 192 V and

phase shift of 120° are generated [94].

In the last scenario, the operation of the proposed method in the event of multiple faults in one

phase was investigated. In this scenario, there were two faulty cells in phase ‘a’. In this condition,

the phase shifts of the inverter phase voltages needs to be adjusted to ab  ca    140 . The

generated voltage waveforms in this fault scenario are shown in figure 5.9. As pictured, the phase

67
shifts between the phase voltages are correctly adjusted to generate balanced line-to-line voltages

[94].

68
Chapter VI: Proposed Z-source based Fault-Tolerant Strategy
6.1. Modulation Method
A large variety of modulation methods for multilevel inverters have been discussed in the literature

throughout the last decade [40, 41]. Several of these methods can be employed to control the

proposed qZSId-CHB inverter [43, 44]. However, the PS-PWM [17] is very well suited to

implement the proposed fault-tolerant strategy in this chapter [18]. For the purpose of this work,

the PS-PWM method is modified slightly to generate shoot-through switching states in addition to

traditional non-shoot-through states. Figure 6.1 illustrates the switching logic of the modified

PS-PWM technique for one of the qZSId cells in the qZSId-CHB inverter [80, 87].

The traditional PS-PWM uses two carrier signals with 180° phase shift for each H-bridge cell in a

CHB inverter (ci and c'i in figure 6.1) [23]. The relative phase angle of carrier signals for each

phase of the inverter depends on the number of H-bridge cells in each phase [80, 87],

 360
ci  (i  1) 
 2m i  1, 2 ,3 , ..., m . (6.1)
 c 'i  ci  180

A sinusoidal reference signal (mj) is compared with the two carrier signals associated with each

H-bridge cell in a inverter phase and the switching signals for the H-bridge switches are generated

accordingly. To generate the shoot-through states using the modified PS-PWM technique, a new

shoot-trough signal with amplitude of 1-D is introduced to the switching logic. This new signals

is represented as a green line in figure 6.1. In addition, the switching logic is modified so that

whenever the carrier signal is smaller than the shoot-through signal, the H-bridge stage in the

corresponding qZSId cell is short circuited by its switches. The generated shoot-through states are

depicted as shaded areas in figure 6.1 [80, 87]..

69
 mi +- 0
1

To Si1

ci +- 0
1

To Si3
1-D

To Si2
++ 0
1

-- 0
1
To Si4

(a)
θci
ci c'i
1-D
M m j

-M

θm
1

Si1
0
1

Si3
0
1

Si2
0
1
Si4
0
(b)
Figure 6.1. The modified PS-PWM strategy for qZSId-CHB inverter: (a) The switching logic for the modified
PS-PWM technique, (b) The generated switching signals for the ith cell; the reference (blue sinusoidal waveform, mj)
and carrier (triangular waveforms, c and c') signals that are used in the logic circuit to generate switching signals
(square-wave signals, Si1, Si2, Si3 and Si4) for the ith H-bridge cell are shown in this figure [80, 87].

6.2. Minimizing Voltage Stress on Switches

In a typical ZSI, the amplitude of the generated voltages can be increased by increasing the

duration of the shoot-through states. However, increasing the shoot-through leads to an increase

in the output voltage of the ZSI circuitry (the Vdc in figure 2.2) [80, 87]. This dc link voltage is the

70
voltage stress that the inverter switches need to tolerate. Therefore, when increasing the amplitude

of the generated voltages using shoot-through states, it is essential to ensure that the amplitude of

the dc link voltage does not exceed the stress rating of the switches [80, 87]. Additionally,

increasing the dc link voltage results in a significant increase in the current of the inductors in a Z-

source network [15]. As such, for any operating point, it is desirable to minimize the dc link

voltage and achieve the required output voltage level by increasing the modulation index rather

than the shoot-through.

As mentioned previously, in the qZSId cell of figure 2.2 the dc link voltage is equal to BVin, and

the upper limit of the dc link voltage is the voltage stress rating of the H-bridge switches (VBN),

BVin  VBN . (6.2)

Therefore, the maximum boost factor allowed is equal to VBN Vin . As a result, the maximum

allowed shoot-through is equal to [80, 87],

 VBN 
  1
Dmax   Vin 
. (6.3)
 VBN 
2 
 Vin 

This gives a hard upper limit on the amount of shoot-through that the proposed method can

generate [80, 87].

To minimize the dc link voltage for any inverter voltage gain (G), the amount of shoot-through

needs to be minimized while the modulation index is maximized. The modulation index (M) is

always greater than zero and less than (1-D). To maximize the modulation index and to minimize

71
the shoot-through ratio, the shoot-through ratio must be equaled to 1-M. According to the

formulations for a qZSId circuit [80, 87],

1
G  Bmin  M max   (1  Dmin ) . (6.4)
1  2 Dmin

By careful inspection of (6.4), one can realize the minimized shoot-through is [80, 87],

G 1
Dmin  (6.5)
2G  1

while the maximized modulation index will be equal to [80, 87],

M max  1  Dmin . (6.6)

The results in (6.5) and (6.6) will be used as the basis for balancing the shoot-thorough vs.

modulation index by the proposed method whenever necessary.

6.3. Fault-Tolerant Strategy

In this chapter, a fault-tolerant strategy for a qZSId-CHB inverter based on FPSC technique is

proposed. The proposed fault-tolerant strategy combines the voltage gain flexibility provided by

the qZSId-cells with the phase shifting property of the FPSC technique to fully recover the inverter

operation upon occurrence of single or multiple faults on inverter switches. The proposed fault-

tolerant strategy works in two stages to compensate for the faulty switches in the inverter. The

first stage involves bypassing the faulty cells while the second stage involves applying the FPSC

technique to recover the amplitude and balance the phase angles of the inverter voltages [80, 87].

In case there are one or more faulty switches in a qZSId-CHB inverter, based on the fault type and

the location of the faulty switches, the faulty qZSId-cells fail to generate all of the previously
72
mentioned feasible output terminal voltage levels in a non-shoot-through mode (Vdc, 0, -Vdc). As

a result, the inverter phases with faulty cells can no longer generate phase voltages that are

symmetric around the zero volt level. Therefore, the faulty phases of the inverter start generating

unbalanced phase voltages that contain dc offset components. In its first stage of operation, the

proposed method bypasses all of the faulty qZSId-cells to prevent generation of the dc offset by

making the phase voltages symmetric around zero volt level. However, in this condition the

amplitude of the voltages generated by all 3-phases of the inverter are no longer equal. The phases

with bypassed cells can no longer generate all of the voltage levels and thus the amplitude of the

voltages generated by these phases will be less than that of the healthy phases [80, 87].

To balance and increase the voltage amplitudes to the pre-fault condition, it is easy to come up

with the simple idea of increasing the voltage gain of the faulty phases by increasing their

associated shoot-through levels. However, this simple idea comes with two major drawbacks: by

increasing the shoot-through in the faulty phases, the voltage stress on all of remaining healthy

switches in the faulty phases increases significantly, leading to a higher possibility of a subsequent

fault in the already faulty phases; additionally, the current of the inductors on all remaining healthy

cells in the faulty phase increases considerably as well. In the previously mentioned 7-level qZSId-

CHB inverter with one faulty cell, to fully recover the inverter operation by increasing the shoot-

through of the faulty phase, the voltage gain of the faulty phase will be increased for a 1.5 factor

resulting to a considerable increase in voltage stress over the healthy switches in this phase. As a

result, rather than only increasing the shoot-through of the faulty cells, the proposed fault-tolerant

strategy employs the FPSC technique to evenly distribute the rise of voltage stress between all of

the inverter switches [80, 87].

The conventional FPSC technique is discussed in [26]. The FPSC technique modifies the phase

73
angles of the inverter phase voltages (θab, θbc, θca in figure 2.5) to generate balanced line-to-line

voltages. figure 2.5(c) demonstrates how modifying the phase angles of inverter voltages can lead

to balanced line-to-line voltages for a inverter with one bypassed faulty cell. According to this

figure, although the amplitude of the phase voltages (Vb, Vc) are not equal, by properly adjusting

the phase angles (θab, θbc, θca), the amplitude of the line-to-line voltages (Vab, Vbc, Vca) are made

all equal. Therefore, for generating balanced line-to-line voltages, the phase shifts between phase

voltages should be adjusted according to the obtained values. The phase angles of the inverter

phase voltages can be easily adjusted in PS-PWM through adjusting the phase angles of the

sinusoidal reference signals (mj) [80, 87].

Although by applying the FPSC technique to a qZSId-CHB inverter with faulty cells balanced

line-to-line voltages can be generated, however, the inverter operation is not fully recovered

because the amplitude of the generated line-to-line voltages are less than those of a healthy

inverter. In the 7-level qZSId-CHB inverter of above for instance, the amplitude of the line-to-

line voltages before fault occurrence is equal to 3√3 =5.19 p.u., however, after application of the

FPSC the amplitude of the line-to-line voltages is reduced to 4.6 p.u (according to (2.11)). To

recover the line-to-line voltages, the proposed method increases the post-fault inverter voltage gain

(Gfault) to [80, 87],

G pre fault
G fault  (6.7)
KG

where Gpre-fault is the inverter voltage gain before fault occurrence and KG is a performance

reduction factor found from [80, 87],

74
 Im
Vb = 3.387
p.u.

Vbc = 5.19 p.u.

θab = 130.5º Re
θbc = 99º

θca = 130.5º Va = 2.258

p.u.

Vc = 3.387
p.u.
Figure 6.2. The phasor diagram of phase voltages in a qZSId-CHB inverter: The faulty condition in which the faulty
cell is bypassed. The phase angles are modified according to the FPSC strategy to generate balanced line-to-line
voltages and voltage gain is modified by changing the shoot-through ratio to compensate for the line-to-line voltage
reduction in the post-fault condition [80, 87].

VLL
KG  fault
. (6.8)
VLL pre  fault

In (6.8), VLL fault

and VLL pre  fault
are the amplitudes of the line-to-line voltages of the inverter post

and pre-fault condition, respectively. For the 7-level qZSId-CHB inverter of above,

VLL pre  fault

 5.19 p.u. and VLL fault
 4.6 p.u. which results in a performance reduction factor of

KG  0.885 . According to (6.7), this means that the inverter voltage gain should be increased by

a factor of KG1  1.129 after applying the FPSC in order to fully recover the inverter operation.

The resulting phasor diagram for this post-fault condition is shown in figure 6.2. This figure clearly

demonstrates that in the post-fault condition, by applying the proposed method, despite having

unbalanced phase voltages, the inverter line-to-line voltages are fully recovered to their pre-fault

condition. It is worth mentioning that typically the correct line-to-line voltages fully satisfy the

requirements of the load and result in uninterrupted operation of the inverter system [80, 87].

As mentioned before, for any operating point of the inverter the shoot-through (and thus the voltage

75
stress of the switches) should be minimized while modulation index is maximized. The minimum

shoot-through that will result in the required post-fault gain (Gfault) can be found from (6.5),

G fault  1
Dfault,min  (6.9)
2G fault  1

while the modulation index in this condition can be calculated from (6.6) [80, 87],

M fault,max  1  Dfault,min . (6.10)

Finally, the value of Dfault,min from (6.9) is compared to the upper limit Dmax in (6.3) to make sure

the switches will not get damaged in the post-fault condition. As long as the Dfault,min is found to

be less than Dmax , the proposed method can fully recover the inverter operation regardless of the

type and place of the faults. A flowchart of the proposed fault-tolerant strategy is depicted in figure

6.3 [80, 87].

As expressed earlier, one advantage of the proposed method is that rather than only increasing the

shoot-through of the faulty cells and thus increasing the voltage stress of the switches considerably

in the faulty phases, it evenly increases the voltage stress on all inverter switches for a small

amount. In the previously mentioned 7-level qZSId-CHB inverter with one faulty cell, to fully

recover the inverter operation by only increasing the shoot-through of the faulty phase, the voltage

gain of two remaining cells must be increased by a 1.5 factor. Assuming the inverter is operating

with M = 0.85 and D = 0.15, using (2.1) and (6.4) the boost factor and the voltage gain in normal

operation are found as B = 1.42 and G = 1.21. As mentioned, after fault occurrence the voltage

gain on remaining cells needs to be increased to Gfault = 1.5×1.21 = 1.82 which results in Dfault =

0.31 and Bfault = 2.64. Therefore, the voltage stress on the switches in the faulty phase is increased

76
 Start

Yes
Generate the Generate the
Dfault = Dmax; Is Dfault > Find the Gfault and the
switching signals Initialization switching signals
Mfault=1-Dfault; Dmax Dfault (III)
regarding II.B regarding II.B

Find the No
required
voltage gain
G
Dmin = Dmax;
Mmax=1-Dmin;
Calculate the
Dmin and the
Mmax (II.C)
Yes

Fault diagnosis
Any Faulty strategy based on the
Is Dmin > Dmax Voltage Measurment
No No Switch? Principle Component
Analysis (PCA) [46]
Yes

Find the number and

location of faulty cells
then bypass them (III)

Find the Find the

Yes number of Yes number of Yes Find the number of
Any fault in Any fault in Any fault in
operative operative operative cells in
phase ‘a’? phase ‘b’? phase ‘c’?
cells in phase cells in phase phase ‘c’, (Vc)
‘a’, (Va) ‘b’, (Vb)
No
No No
The number of
operative cells in
phase ‘c’, (Vc) is m
The number The number Yes Find the number of
of operative of operative Any fault in
operative cells in
cells in phase cells in phase phase ‘c’?
‘a’, (Va) is m phase ‘b’, (Vc)
‘b’, (Vb) is m
No
Plug (Va), (Vb) and
The number of (Vc) into (10),
operative cells in Revise θab, θbc, and
phase ‘c’, (Vc) is m θca (III)
Find the Find the
Yes number of number of
Is fault in Any fault in Yes
operative operative
Phase ‘b’? phase ‘c’?
cells in phase cells in phase
‘b’, (Vb) ‘c’, (Vc)
No
No
The number
of operative
cells in phase
‘c’, (Vc) is m

Find the
The number
number of
of operative
operative
cells in phase
cells in phase
‘b’, (Vb) is m
‘c’ (Vc)

Figure 6.3. Flowchart of the proposed fault-tolerant strategy.

for a factor of Bfault /B = 1.85.

In the other words, the voltage stress on the switches in the faulty phase increases for 85% but it

remains the same for the switches in the healthy phases. In contrast, using the proposed fault-

77
Figure 6.4. The prototype 3-phase seven-level qZSId-CHB inverter and 12 V batteries [80, 87].

tolerant strategy, the voltage gain of all of the healthy cells of the inverter increase by a factor

KG1  1.129 . Following the same calculations as before using 1.129 for voltage gain, it can be

concluded that the voltage stress on the inverter switches increases for only 20% in this condition.

This greatly reduces the possibility of a subsequent fault in the already faulty inverter [80, 87].

Now, this section provides experimental results generated through utilizing the proposed fault-

tolerant strategy to restore the operation of a prototype seven-level qZSId-CHB inverter to the pre-

fault conditions, in case of three different fault scenarios. The experimental setup is shown in figure

6.4.

In this setup, the input side of each Z-Source network is connected to a 12 V battery (Vin = 12) and

the output side is connected to the dc link terminal of each H-bridge cell. The power semiconductor

devices used in this prototype are power MOSFETs with drain to source voltage rating of 100 V

(VBN = 100). The Z-Source components are C1 = C2 = 2200 μF, and L1 = L2 = 500 μH. The output

terminals of the qZSId-CHB inverter are connected to a 3-phase inductive load with a 0.9 power

factor assembled using a 7 Ω resistor in series with a 1.2 mH inductor in each phase. In the

78
 Inverter’s Phase Voltage ‘a’ (40 V/Div) Inverter’s Line Voltage ‘ab’
(100 V/Div)

Inverter’s Phase Voltage ‘b’ (40 V/Div) Inverter’s Line Voltage ‘bc’
(100 V/Div)

Inverter’s Phase Voltage ‘c’ (40 V/Div) Inverter’s Line Voltage ‘ca’
(100 V/Div)

(a) (b)
Inverter’s Load Voltage ‘a’ (40 V/Div)

H-Bridge’s DC Link Voltage or Voltage

Stress over the switches (10 V/Div)
Inverter’s Load Voltage ‘b’ (40 V/Div)

Inverter’s Load Voltage ‘c’ (40 V/Div)

(c) (d)
Figure 6.5. The qZSId-CHB’s voltages in normal operating condition: (a) Inverter’s phase voltages, (b) line-to-line
voltages, (c) load voltages, and (d) the dc link voltage of one H-Bridge cell (the voltage across H-Bridge’s switches)
[80, 87].

operating point used for generating the results (Vload = 44 V, Iload = 6 A), in order to minimize the

voltage stress on the switches, the modulation index and the shoot-through ratio are set to 0.85 and

0.15, respectively. By substituting these values in (6.4), the voltage gain in normal operation (GPre-

fault) is found as 1.21. The fundamental and switching frequencies of the PS-PWM method are 50

Hz, and 2 kHz; respectively. The phase voltages, line-to-line voltages, load voltages and the dc

link voltage of one H-bridge cell of the inverter for the pre-fault condition are shown in figure 6.5.

According to figure 6.5, in this operating point, the amplitudes of phase voltages, line-to-line

voltages, load voltages, and the dc link voltage of each H-bridge cell are equal to 44 V, 76 V, 44

V, and 17V, respectively. The THD of the load voltages in this condition is calculated as 9.5%

[80, 87].

79
The first experiment analyzes the occurrence of a single fault in phase ‘b’. In this case, according

to the flowchart of figure 6.3, the faulty cell is bypassed at the first step. Therefore, the number of

operative cells in phase ‘b’ is reduced to 2 cells (Vb = 2 p.u., Va = Vc = 3 p.u.). In this condition,

to generate balanced line-to-line voltages, based on (2.11) the phase shifts between the inverter

phase voltages need to be adjusted to bc  cb    130.5 . The performance reduction factor

(KG) and the voltage gain in the faulty condition (Gfault) in this experiment are calculated from

(6.7), (6.8) as 0.885 and 1.37, respectively. Subsequently, the new modulation index and shoot-

through ratio that compensate the loss of one operative cell in phase ‘b’, while keeping the voltage

stress across the switches at minimum can be calculated from (6.5). These parameters (M and D)

are found to be equal to 0.78 and 0.22, respectively. The calculated shoot-through ratio is checked

against the maximum applicable shoot-through ratio found from (6.3) as Dmax = 0.44 to make sure

the voltage stress will not exceed the limitations of the switches as a result of implementing the

proposed fault-tolerant strategy. The new values of M and D along with the adjusted phase shifts

are used by the PS-PWM algorithm to generate modified switching commands to restore the

operation of the inverter to the pre-fault conditions [80, 87].

To emulate the fault condition, one of the switches in phase 'b' of the inverter was manually short

circuited at t = t0. Subsequently, the H-bridge cell containing the faulty switch was bypassed and

the proposed fault-tolerant strategy was applied at t = t1. The generated phase voltages of the

inverter during the normal operation ( t  t0 ), the fault recovery period ( t0  t  t1 ), and the post-

fault operation ( t  t1 ) are shown in figure 6.6(a). Due to the inferior quality of the waveforms in

this scope shot, the actual raw data from the oscilloscope were exported to MATLAB to generate

figure 6.6(a). As pictured in figure 6.6(a), during the normal operation ( t  t0 ) the phase voltages

80
reach all seven levels, however, during the fault recovery period ( t0  t  t1 ) and upon bypassing

the faulty cell in phase ‘b’, this phase only generates five voltage levels. In this condition, the

amplitude of the phase ‘b’ voltage is equal to 35.1 V, while the amplitude of the voltages in the

healthy phases ‘a’ and ‘c’ are equal to 52.55 V and 52.6 V, respectively [80, 87].

At this point ( t  t1 ), the proposed fault-tolerant strategy is triggered to restore the operation of the

inverter to the pre-fault conditions. According to the readings provided on figure 6.6(a) for the

waveforms in the post-fault condition, the phase shifts between the waveforms are accurately

adjusted to the intended values of bc  ab    130.5 by the proposed strategy. To verify

generation of balanced line-to-line voltages, the raw data from figure 6.6(b) were imported to

MATLAB to plot figure 6.6(b). According to this figure, the amplitudes of the line-to-line voltages

are all equal to 76.5 V, and the phase shifts between these voltages are also all equal to 120°. This

confirms the validity of the proposed fault-tolerant strategy for generating balanced line-to-line

voltages in the event of a bypassed faulty H-bridge [80, 87].

The waveforms plotted in figure 6.6(c) confirm generation of balanced load voltages in the post-

fault condition as well. Figure 6.6(d) shows the dc link voltage of one of the H-bridge power cells

during this experiment. According to this figure, the value of the dc link voltages are increased for

only 3.5 V in the post-fault condition. The harmonic spectrums of the load voltage for the post-

fault condition is shown in figure 6.6(e). The THD of the load voltages are calculated using the

data imported from the oscilloscope as 10%, 11% and 10% for the Van, Vbn and Vcn, respectively.

This shows a negligible increase of THD in the post-fault condition. Finally, the load currents in

the event of a single faulty phase is given in figure 6.6(f). As it can be seen the amplitude of the

current in the post fault operation of the inverter is equal to the amplitude of this current in normal

81
operation of the inverter. However, the THD of the current is slightly increased in the post fault

operation. The current THD is increased from 2.9% to 3.3% due to fault occurrence [80, 87].

Normal Operation Faulty Post-Fault Operation

50
Inverter’s Phase Voltages

0
130.5°
-50
50

-50 130.5°
50

-50
t0 t1
0.04 0.06 t0 = 0.08 t1= 0.1 0.12 0.14 0.16 0.18
Figure 6.6(a)
Normal Operation Faulty Post-Fault Operation
100
Inverter’s Line Voltages

0
120°
-100
100 120°

-100
100

-100
t0 t1
0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18
Figure 6.6(b)
Normal Operation Faulty Post-Fault Operation
50
Inverter’s Load Voltages

-50 120°
50 120°

-50
50

-50

t0 t1
0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18
Figure 6.6(c)

82
 25
DC Link Voltage
20
+3.5 Volts

15

10

-5
0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18
Figure 6.6(d)

50 50 50

Harmonic Spectrum of Van Harmonic Spectrum of Vbn Harmonic Spectrum of Vcn

40 40 40
THD=10%
THD=10% THD=11%
30 30 30

20 20 20

10 10 10

0 0 0
0 5000 10000 15000 20000 0 5000 10000 15000 20000 0 5000 10000 15000 20000
Frequency (Hz) Frequency (Hz) Frequency (Hz)
Figure 6.6(e)
10
Normal Operation Faulty Post-Fault Operation
ia ib ic
5
Load Currents

-5

-10
0.05 0.07 0.09 0.11 0.13 0.15 0.17
Figure 6.6(f)
Figure 6.6. The qZSId-CHB voltage and current waveforms in the event of a faulty switch in phase ‘b’ (first
experiment): (a) Inverter’s phase voltages, (b) line-to-line voltages, (c) load voltages, (d) dc link voltage of one H-
bridge cell, (e) the harmonic spectrum of the load voltages, and (f) the load currents [80, 87].

The second experiment analyzes the case of two faulty switches, one in phase ‘b’ and another one

in phase ‘c’. In this condition, the phase shifts of the inverter phase voltages need to be adjusted

to ab  ca    101.5 . To emulate the fault condition, one switch in phase 'b' and another one in

83
phase ‘c’ were manually short circuited at t = t0 [80, 87].

Normal Operation Faulty Post-Fault Operation

50
Inverter’s Phase Voltages

0
101.5°

-50
50

0
157°
50

-50
0.02 0.04 0.06 t0 0.08 0.1 t1 0.12 0.14 0.16 0.18
Figure 6.7(a)

Normal Operation Faulty Post-Fault Operation

100
Inverter’s Line Voltages

-100 120° 120°

100

-100
100

-100

0.02 0.04 0.06 t0 0.08 0.1 t1 0.12 0.14 0.16 0.18

Figure 6.7(b)

Normal Operation Faulty Post-Fault Operation

Inverter’s Load Voltages

50

0
120° 120°
-50
50

-50
50

-50

0.02 0.04 0.06 t0 0.08 0.1 t1 0.12 0.14 0.16 0.18

Figure 6.7(c)

84
 DC Link Voltage
24
+7 Volts
17

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Figure 6.7(d)
50 50 50

45 45 45
Harmonic Spectrum of Van Harmonic Spectrum of Vbn Harmonic Spectrum of Vcn
40 40 40
THD=11% THD=12% THD=12%
35 35 35

30 30 30
25 25 25
20 20 20
15 15 15
10 10 10
5 5 5
0 0 0
0 5000 10000 15000 20000 0 5000 10000 15000 20000 0 5000 10000 15000 20000
Frequency (Hz) Frequency (Hz) Frequency (Hz)
Figure 6.7(e)
10 Normal Faulty Post-Fault Operation
Operation
5
Load Currents

-5
ib ic ia
-10
0.05 0.07 0.09 0.11 0.13 0.15 0.17
Figure 6.7(f)
Figure 6.7. The qZSId-CHB voltage and current waveforms in the event of a faulty switch in phase ‘b’ and another
faulty switch in phase ‘c’ (Second experiment): (a) Inverter’s phase voltages, (b) line-to-line voltages, (c) load
voltages, (d) dc link voltage of one H-bridge cell, (e) the harmonic spectrum of the load voltages, and (f) the load
currents [80, 87].

The faulty H-bridge cells were bypassed, and the fault-tolerant strategy was triggered at t = t1. The

generated voltage waveforms for this experiment are shown in figure 6.7. According to figure

6.7(a), in the fault recovery period the amplitude of the phase ‘a’ voltage is equal to 60.58 V, while

85
the amplitudes of the voltages in the other two phases are reduced to 41.1 V and 41.2 V. Similar

to before, upon triggering the proposed fault-tolerant strategy the phase shifts between the

waveforms are accurately adjusted to ab  ca    101.5 . Consequently, balanced line-to-line

voltages with equal amplitudes of 76 V and phase shift of 120° were generated. The THD of load

voltage are calculated in this experiment as 11%, 12% and 12% for the Van, Vbn and Vcn,

respectively. The value of the dc link voltage is increased by 7 V in the post-fault condition in this

experiment. The current THD is increased to 3.5% due to fault occurrence [80, 87].

The third experiment analyzes the occurrence of multiple faults in one phase of the inverter. In

this experiment, two switches in phase ‘b’ are manually short circuited to emulate the fault

condition. In this case, the phase shifts of the inverter phase voltages need to be adjusted to

ab  bc    140 . Similar to the previous experiments, the fault-tolerant strategy bypasses the

faulty cells and modifies the phase angles and shoot-through ratio to generate balanced line-to-line

voltages. The generated voltage waveforms for this experiment are shown in figure 6.8. Similar

to the two previous experiments, the waveforms presented in figure 6.8 confirm generation of

balanced line and load voltages with equal amplitudes and phase shifts in the post-fault condition

[80, 87].

Normal Operation Faulty Post-Fault Operation

50
Inverter’s Phase Voltages

0
140°
-50
50

0
140°
-50
50

-50

0.04 0.06 0.08 t0 0.1 0.12 t1 0.14 0.16 0.18

Figure 6.8(a)

86
 Normal Operation Faulty Post-Fault Operation
100
120°
Inverter’s Line Voltages

-100
100 120°

-100
100

-100

0.04 0.06 0.08 t0 0.1 0.12 t1 0.14 0.16 0.18

Figure 6.8(b)

Normal Operation Faulty Post-Fault Operation

50
Inverter’s Load Voltages

-50
50 120°

-50 120°
50

-50

0.04 0.06 0.08 t0 0.1 0.12 t1 0.14 0.16 0.18

Figure 6.8(c)
DC Link Voltage
25
+8 Volts
17

8
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Figure 6.8(d)

87
 50 50 50
50
45 45 45
45
Harmonic Spectrum of Van Harmonic Spectrum of Vbn Harmonic Spectrum of Vcn
40 40 40 Harmonic Spectrum of Vbn
THD=10% 40
THD=13% THD=10%
35 35 35
35
30 30 30
30
25 25 25
25
20 20 20
20
15 15 15
15

10 10 10
10

5 5 55

0 0 00
0 5000 10000 15000 20000 0 5000 10000 15000 20000 00 5000
5000 10000
10000 15000
15000 20000
20000
Frequency (Hz) Frequency (Hz) Frequency (Hz)

Figure 6.8(e)
10 Normal Faulty Post-Fault Operation
Operation

5
Load Currents

-5
ib ic ia
-10
0.05 0.07 0.09 0.11 0.13 0.15 0.17
Figure 6.8(f)
Figure 6.8. The qZSId-CHB voltages in the event of two faulty switches in phase ‘b’ (Third experiment): (a) Inverter’s
phase voltages, (b) line-to-line voltages, (c) load voltages, (d) dc link voltage of one H-bridge cell and (e) the harmonic
spectrum of the load voltages [80, 87].

88
Chapter VII: Conclusions and Future Research
The multilevel power inverters have successfully found their place in industrial applications with

medium to high voltage and power conversion requirements. They offer improved characteristics

such as lower total harmonic distortion, higher efficiency, and lower switching voltage stress

compared to conventional two-level inverters. These superior characteristics come at the price of

wrapped inverter topology with more power electronics devices, and more complicated control

and modulation strategy.

This dissertation focused on two main aspects of control in the multilevel power inverter. First,

proposing a novel high frequency modulation method for the normal operation of the inverter.

Second, proposing promising fault-tolerant strategies in the areas, which are not well explored by

the researchers such as selective harmonic elimination, space vector modulation and z-source

networks.

Our research findings can be summarized as follows:

1) In this dissertation a new modulation technique for MLI was proposed. This modulation

method is simple and easy to implement digitally and the computational efforts made in

this method is much simpler compared to the other modulation methods such as space

vector modulation. The proposed method extends the utilization of the dc link voltage in

MLIs because of the wider linear modulation range. The more utilization of dc link voltage

means the ability of multilevel inverter is improved to convert the dc to ac power. The

proposed method minimizes the dv/dt of the switches and keeps it only one voltage

transitions. The total harmonic distortion of the voltages generated by this method are well

89
 within the acceptable industrial limits and comparable to the commonly used modulation

methods.

2) In the next attempt, a fault-tolerant strategy based on the half-wave symmetrical selective

harmonic elimination was proposed to improve the performance of a MLI under faulty

condition. The proposed method rebalances the line-to-line voltages, makes the best use

of inverter capacity by keeping all healthy cells operational, and limits the total harmonic

distortions of the inverter waveforms even in a faulty situation. The proposed strategy can

easily be implemented on various types of MLIs without limitation on the number of

voltage levels.

3) Later, a new fault-tolerant technique based on space vector modulation for improving the

performance of a MLI under faulty conditions was proposed. Using the proposed method,

the inverter generated balanced line-to-line voltages, even with one or more faulty

switches. Using the conventional fault-tolerant strategies, the maximum achievable line-

to-line voltages for a seven-level CHB inverter with a single faulty switch is reduced by

more than 30%; however, the reduction in the voltage using the proposed method was only

around 10%. Although the proposed strategy can easily be implemented on various types

of MLIs without limitation on the number of voltage levels, at least two of the phases must

have equal number of the operative cells. If the inverter has completely asymmetric legs,

the number of operative cells in two of the inverter phases must be equalized by bypassing

one or more operative cells. Dealing with a completely asymmetric fault condition will be

discussed in a future work.

90
 4) Finally, a new fault-tolerant strategy for improving the performance of a qZSId-CHB

inverter under faulty condition was proposed. Using the proposed method, only the faulty

qZSId cell was bypassed and the remaining healthy cells were remained operative to use

the maximum capacity of the inverter. By adopting the FPSC method, instead of just

increasing the voltage gain in the faulty phase, the voltage gain of all the operative cells

were increased evenly to minimize the voltage stress over the healthy switches. Even in

the event of multiple faulty switches, the inverter can generate balanced line-to-line

voltages with the same amplitude as the healthy inverter. The total harmonic distortion of

the post-fault voltages generated using the proposed method does not increase

considerably. The proposed strategy can be easily implemented on any MLI with an

incorporated Z-Source network without limitation on the topology or the number of

inverter voltage levels.

There are many research opportunities looking ahead in this area of multilevel power inverters:

1) A novel fault-tolerant strategy by using the proposed high frequency modulation method

can be developed in future. The main advantage of this idea is to increase the dc link

utilization of the inverter and compensate the voltage drop in the event of a fault.

2) Exploring the Modular Multilevel Inverter topology and applying the unbalanced space

vector modulation on this topology for the fault-tolerant purposes.

3) Implementing the space vector modulation on the Z-source network connected CHB

inverters to take the advantages of both worlds.

91
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