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14 views19 pages

f Unit - III (3.4)

Uploaded by

anupatil7576
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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3.

4 Minimum mode and maximum


mode configuration of 8086, timing
diagrams concept
TLO 3.4 :

Compare minimum mode and maximum mode of 8086 features.


8086 Operating Modes
The 8086 microprocessor can operate in two distinct modes, each
suited for different system configurations and applications:
• Minimum Mode
• Maximum Mode
 Minimum Mode Configuration

• Definition: The 8086 operates in minimum mode when the


MN/MX# (pin 33) is connected to a high voltage level (logic 1). This
mode is designed for systems with a single 8086 microprocessor.

• Configuration: The 8086 directly controls the system's buses, and


all the control signals are generated internally by the microprocessor.

• Applications: Ideal for simple systems like embedded systems,


single-user computers, and control systems where a single CPU is
sufficient.
Minimum Mode Circuit:
 Maximum Mode Configuration

• Definition: The 8086 operates in maximum mode when the


MN/MX# pin is connected to a low voltage level (logic 0). This mode
supports systems that include additional processors like coprocessors or
other 8086/8087 processors.

• Configuration: The 8086 works with an external bus controller


(8288) that generates the necessary control signals for coordinating
multiple processors. This allows for more complex system designs.

• Applications: Used in multi-processor systems, servers, and systems


requiring advanced multitasking capabilities
Maximum Mode Circuit:
Comparison Of Minimum
Mode Configuration and
Maximum Mode
Configuration
Minimum mode Maximum Mode
Parameters
configuration Configuration

1. Control Signal Generated internally Managed by the


Generation by the 8086. external bus
controller (8288).
2. System Simpler, fewer More complex,
Complexity components, easier supports multiple
to implement. processors and
peripherals
3. Performance Suitable for lower- Capable of handling
performance, single- higher-performance
processor systems. requirements due to
support for multiple
processors.
Timing Diagram Concepts for 8086 in
Minimum Mode
• Bus Cycle:
A sequence of events when the 8086 communicates with an external device,
such as reading from or writing to memory or I/O devices.

• Time States:
Each clock cycle is called a t-state. A bus cycle consists of four t-states: T1, T2,
T3, and T4, collectively known as a Machine Cycle.

• Instruction Cycle:
The total time needed to fetch and execute an instruction, consisting of one or
more machine cycles
Timing Diagram Concepts for 8086 in
Minimum Mode
Memory Read Cycle:
• T1:
• 8086 outputs the 20-bit address and BHE (Bus High Enable) on the
address/data bus.
• ALE (Address Latch Enable) signal is generated to latch the address.
• M/IO is set to 1 (indicating a memory operation), DT/R is set to 0
(data reception).
• T2:
• Status bits (S3-S6) are output, address/data bus lines AD0-AD7 enter
high-Z state.
• RD (Read) is activated (logic 0) to start reading data.
• DEN (Data Enable) is set to 0 to allow data transfer from memory to the
8086.
• T3:
• The memory places valid data on the bus, which the 8086 reads.

• T4:
• RD and DEN signals are deactivated, ending the read operation.
MEMORY READ CYCLE FOR 8086 IN
MINIMUM MODE
Timing Diagram Concepts for 8086 in
Minimum Mode
Memory Write Cycle:
• T1:
• Address and BHE are output, and ALE latches the address.

• M/IO is set to 1 (indicating a memory operation), DT/R is set to 0


(data transmission).
• T2:
• WR (Write) is activated (logic 0) to indicate a write operation.
• The 8086 places data on the bus.
• DEN enables data transfer from the 8086 to memory.

• T3 and T4:
• Data remains valid on the bus, completing the write operation.
MEMORY WRITE TIMING FOR 8086 IN
MINIMUM MODE
Timing Diagram Concepts for 8086 in
Maximum Mode
• Coordination with 8288 Bus Controller:
In maximum mode, the 8086 works with the 8288 bus controller to manage
control signals for multi-processor support.

• Status Signals (S0, S1, S2):


Indicate the type of operation (memory read/write, I/O, etc.).

• Bus Arbitration:
Process of managing multiple processors and devices sharing the system bus.
• Bus Control Signals:
• M/IO: Memory or I/O operation.
• RD#: Read signal.
• WR#: Write signal.
• LOCK#: Ensures bus control for critical sections.
MEMORY READ TIMING FOR 8086 IN
MAXIMUM MODE
Thank You

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