LINEALIZATION TECHNIQUE USING The Digital Cartesian loop transmitter consists of a Cartesian

DIGITAL CARTESIAN LOOP loop transmitter, well-known linear transmitter architecture

[1-4], but it takes part digital signal processing. The
TRANSMITTER Cartesian loop is a system in which a conventional linear or
non-linear RF amplifier is improved, in terms of its distortion
Paloma García Dúcar, Jesús de Mingo, Antonio Valdovinos performance, in order to meet a given specification. This is
achieved with a minimal impact on the overall power
Centro Politécnico Superior consumption and power efficiency of the system, and with a
Universidad de Zaragoza minimum of added complexity.
50015 Zaragoza, Spain The principle of a Cartesian loop is based on the feedback of
the amplifier power output signal, previously demodulated,
ABSTRACT and its comparison with the base-band input signal. The
technique takes baseband signals, in I and Q format, and
The study of a Digital Cartesian loop transmitter as power translates these sign als to an RF carrier frequency at a high
amplifier linearization technique is presented. It is based power level. By this mechanism, AM-AM and AM -PM non-
on Cartesian loop architecture but introducing the linearities in the up-converter and driver amplifier chain are
advantages and possibilities of using digital solutions. linearised, in addition to the RF power amplifier. If an
Stability is assured by including some adjustment elements intermediate frequency is employed in the up-conversion
in the loop and th e digital implementation avoids process, then non -linearities in this block are also removed.
modulator and demodulator impairments and provides an As with all feedback systems, its performance is limited by
accurate control and compensation of loop delay. the delay around the loop and hence the linearity
improvement which can be obtained depends upon the
I. INTRODUCTION bandwidth over which the feedback must operate. This
bandwidth is usually limited to a single RF channel or a
The growing demand for mobile communications services number of closely-spaced channels. It also depends upon
and the limit of frequency spectrum has forced the use of the type of amplifier employed. Fig. 1 shows a simplified
more spectrally efficient modulations, the most of which base-band equivalent model of a Cartesian Loop trans mitter.
having non -constant envelope. The nonlinearities of the DA +NA
transmitter (mainly the power amplifier) cause the expansion
of the transmitted signal spectrum into adjacent channels,
this effect is known as ACI (Adjacent Channel Interference). x + A + y
Some systems, such as Terrestrial Trunked Radio (TETRA), -
are very restrictive with regard to the spurious emission in
the adjacent channel. TETRA system requires the spurious
emission in the first adjacent channel to be less than –60
B +
dBc, and –70 dBc in the second and third adjacent channels.
A possible solution for achieving linear amplification is the
use of a class A power amplifier operating far below DB+NB
saturation with an appropriate back-off, but this supposes a
low power efficiency, and therefore it is unsuitable for Fig 1. Simplified Cartesian Loop transmitter base-band model
equipment with restrictive battery capacity requirements.
Class AB, B or C power amplifiers can be used in order to It is based in a forward amplifier with gain A and a feedback
obtain high power efficiency, but they present higher non - network with gain B. The gain A represents the product of
linear characteristics. This problem can be solved by a the gain in the forward path, including the non -linear
linearization process. In this paper we present the achieved amplifier. Noise and distortion that are generated in the
work in the design process of a Digital Cartesian loop system are also included in the figure, where DA denotes the
transmitter. Thorough simulations have been carried out in distortion and NA the noise in the forward path, and DB the
MatLAB allowing the evaluation of several options. distortion and NB, the noise in the feedback path. The output
Computational load and memory usage issues have been signal y is given by
studied prior to a successful implementation in a Ax D + N A AB (DB + N B )
TMS320LC54x, a DSP from TEXAS Instruments. Finally, two y= + A − (1)
boards that implement the whole Digital Cartesian Loop have 1 + AB 1 + AB 1 + AB
been designed.
If the open loop gain AB>>1 the expression is given by
II. CARTESIAN LOOP

0-7803-7589-0/02/$17.00 ©2002 IEEE PIMRC 2002

 x D A + NA
− ( D B + NB )
manipulations, [2], [4], it can be obtained the next phase
y≈ + (2) margin expression:
B AB
π
PM ≈ − AB ω nτ (7)
for (1), the closed loop gain can be defined as 2
A In order to guarantee the stability in the system, the phase
(3) margin has to a positive value and it implies that the
1 + AB
multiplication open loop gain-bandwidth-delay has to be:
and the relation 1+ A ⋅ B is defined as attenuation
π
distortion factor (ATD). A⋅ B ⋅ ω n ⋅ τ < (8)
2
The non-linearities and other distortions in the forward path Several requirements have to be taken into account in some
can be controlled and reduced in a proportional factor to the adjustment elements of the loop, such as A, B and ω n in
open loop gain (1). And finally, the introduced distortion and
order to guarantee this stability limit (or another with a lesser
the generated noise in the feedback path are led to the
phase margin) and also the maximum allowed delay. The last
output signal. Therefore, it would be necessary to get a
feedback path with a good feature of linearity. expression can be shown as (GBW ) , with G the open τ
loop gain (G = AB ) , BW the low-pass filter 3-dB
III. STABILITY
bandwidth in Hz and τ
, the overall loop delay. So, the
stability in a cartesian loop transmitter is kept while the
As all close loop systems, this is a conditionally stable
system, that is, the stability is not guaranteed and it is multiplication open loop gain -bandwidth-delay (GBW ) τ
necessary to carry out a research about the stability is lesser than a constant value. This value depends on the
conditions in order to find out the limitations in the features of all non-linear components, mainly the power
transmitter design. The stability research is concentrated in amplifier.
the search of two critical points in the frequency transfer
function. Supposing a first order system open loop this IV. DESCRIPTION
frequency response is
Non-linear characteristics of the transmitter can be made up
A ⋅ β ⋅ ω n − j ωτ for the digital processing. The main non -linear stage is the
H (ω ) = ⋅e (4) power amplifier but there are others stages with non -
ω n + jω linearities such modulator and demodulator. Therefore the
Digital Cartesian loop must solve all non-linearities of the
Two critical points can be defined in relation with the open transmitter. In this method a Digital Signal Processor (DSP) is
loop frequency response, [2 -4]: “gain crossover applied to carry out the linealization process. An important
frequency”, ω gc , where the open loop gain is equal to one; part of this proces s in order to avoid the non-linearities is the
implementation of the digital modulator and demodulator I/Q.
and the “phase crossover frequency”, ω pc , where the open The digital signal processing is made up of three blocks:
loop phase is 180° (π radians). In relation to these two points, first, the π/4-DQPSK signal generation; second, the forward
it can be also defined the “gain margin” (GM) and the “phase branch of the Cartesian loop and, finally, the feedback
margin” (PM) as branch. This research is aimed at TETRA equipments,
1 therefore, the generated signal is π/4-DQPSK filtered by a
GM =
H (ω pc )
(5) square -root raised cosine with 0.35 roll-off factor. This
signal, consisting of in-phase (x I) and quadrature (x Q)
components, is introduced in the Cartesian loop to linearize
PM = ∠H (ω gc ) + π (6) the transmitter.
Fig 2 shows a block diagram of the π/4-DQPSK signal
Therefore, the stability is guaranteed when GM>1. The generation.
phase margin between the point in which the open loop gain
module is equal to one and the point in which the open loop Symbol I xI
Square-root Interpolator
gain phase is 180º (in absolute value) can be shown as a π/4-DQPSK raised filter
Bit generator
security phase margin. cosine filter
α=0.35
16

From expression (4), it can be defined the frequency Symbol Q

H (ω ) ∠ H (ω )
xQ
response in module and phase of the
Fig 2. π/4-DQPSK signal generation
open loop gain for a first order low-pass filter. After some
The second block of the digital processing in the transmitter behaviour of the amplifier power from AM/AM and AM/PM
linearization process is achieved in the Cartesian loop measurements of a M68749 power module from Mitsubishi
forward path. The components x I and xQ of the π/4-DQPSK with a driver at 390 MHz and the up and down RF converter
signal are introduced in the Cartesian loop where a have been simulated, because they are the least linear
substraction between these signals and the I/Q signals from stages. Another important parameter, the total delay
feedback path is carried out. After the subtraction, the I/Q introduced by the Digital Cartesian loop, has been simulated
output signals are passed through a low-pass digital filter. and a research has been carried out about the influence of
The design of this filter depends on the characteristics of the these factors on the transmitter linearization.
Cartesian loop, being an important parameter in the stability
of the loop. ADJUSTMENT PARAMETERS IN THE CARTESIAN LOOP
Finally, in the forward path a digital modulator I/Q is carried
out by means of a Numerical Control Oscillator (NCO). This • ATTENUATION DISTORTION FACTOR (ATD).
signal is sent to the DAC and then it is passed through the From expression (1) and (4) , the output signal frequency
transmitter stage to convert it in a RF signal. In the feedback response is
AQ(ω ) (D (ω ) + N A (ω ))
Y (ω ) = ⋅ X (ω ) + A
path, the samples from the Analog-Digital converter (ADC)
1 + ABQ (ω )e 1 + ABQ(ω )e − j ωτ
are converted to base-band signals by a digital demodulator − j ωτ
I/Q. These I, Q components are subtracted from the original
x I and xQ signals. This is the point where the Cartesian loop (
ABQ(ω )e − jωτ Dβ (ω ) + N β (ω ) )
−
1 + ABQ (ω )e
is closed. It is necessary to include a phase adjustment − j ωτ
stage, in order to repair the phase difference between the
forward path and the feedback path signals. In a (9)
conventional Cartesian Loop architecture, this compensation ωn
is achieved in the analogue domain by using a variable where, Q(ω ) = , is the first order low-pass filter
phase adjustment block applied to the local oscillator of ω n + jω
modulator and demodulator. In this architecture, the phase frequency response.
adjustment can be included in the digital modulator I/Q, thus The distortion in the output signal associated to the amplifier
been capable of compensating the phase difference and the noise introduced in the main path can be defined as
introduced in the whole Digital Cartesian loop. The NCO of
(D A (ω ) + N A (ω ))
Y D (ω ) =
the digital modulator I/Q is modified in such a way that the
1 + ABQ (ω )e − j ωτ
sine and cosine signals include a phase factor. This phase (10)
factor depends on the Cartesian loop delay and it is
calculated in an initial calibration process. The distortion in the output signal produced by the main
Fig.3 shows a block diagram of the Digital Cartesian Loop. path can be reduced, if it is increased the attenuation
distortion factor, defined as:
vI ATD = 1 + ABQ (ω )e− jωτ (11)
xI + V(mT)
V(t) ypb
coef D/A
Ate1 xQ wI-
+ -
Its value is indicated by the low-pass filter response and the
( )
Low- pass
Filter
wQ - vQ
open loop gain AB .
β
For smaller frequencies (ω << ABω n ) , and in the case
ABQ(ω) >>1 ,
NCO

Y(mT)
the attenuation distortion factor can take
A/D Y(t) B the expression
ABω n
ATD ≈ (12)
DSP ω n2 + ω 2
Fig 3. Digital Cartesian loop Therefore, ATD will take its maximum value by maximizing
the multiplication gain-bandwidth ( ABω n ) or minimizing
V. SIMULATION
the low-pass filter bandwidth. For a fixed loop delay, the
Simulations of the design of Digital Cartesian loop have maximum value of the factor gain -bandwidth ( ABω n ) is
been carried out in Matlab. Simulations include the digital limited by the stability condition. If the factor gain -
signal processing blocks, that afterwards will be bandwidth ( ABω n ) is replaced by a constant K, the ATD
implemented in a DSP, and the analogue blocks. Mainly, the
definition can be seen as:
 K • Output power 3W, with a TETRA input signal.
ATD ≈ (13) • Spurious emission in the first adjacent channel to
2
 K  be less than –60 dBc, and –70 dBc in the second
  +ω
2

 AB  and third adjacent channels.

Therefore, the design parameters are A = coef ⋅ c 0 =200
For a fixed frequency, if the factor gain-bandwidth
(where coef is an adjust driver, gain or attenuation, in the
( ABω n ) is kept constant, ATD increases asympthotycally forward branch). In this first realization is selected to be 1),
with the open loop gain AB . This implies that ATD has a B=0.085, fn=20 KHz, and to meet the stability limit (8), the
K maximum loop delay has to be 735 ns, as it is shown in figure
greater dependence on the loop gain when AB << than 4.
ω
The following values can be obtained for these parameters:
K ωgc = 2.1326e+006 rad/s (339.41 KHz)
for AB >> . The maximum value of ATD, which
ω ωpc = 2.2143e+006 rad/s (352.42 KHz)
depends on the frequency, is reached when the loop gain PM = 3.5641º
goes to infinite, th e low-pass filter bandwidth goes to zero. GM = 1.0382
K 90 2
ATD max ≈ (14) 120 60
ω 1.6
• BANDWITH 3-dB ( ω n ). H(ωpc ) 1.2
150 1 30
From expression (12), the reduction of main inter-modulation 0.8
distortion (IMD) factor will get attenuation levels greater 0.4
when the bandwidth 3-dB increases. However, the
attenuation level has no effect in the IMD of frequency 180 0
PM
smaller than ω n when the bandwidth 3-dB grows. However,
H(ωgc)
an increase in the low-pass filter bandwidth causes a
decrease in the open loop gain in order to meet the loop 210 330
stability limit.
H(ω)
240 300
• LOOP DELAY 270
The loop delay is a very important parameter in the Cartesian
loop design, because the loop stability limit depends on this
Fig 4. Nyquist Diagram in open loop with a first order filter
factor. An increase in the loop delay involves a decrease in
and a loop delay (A=200, B=0.085, fn=20 KHz, τ=735 ns.).
the maximum allowed value for GBW and a reduction in the
linearized ability of the Cartesian transmitter. Therefore, it is
The stability limit for these design parameters is
very important to get a loop delay as small as possible.
small in sense of loop delay. The loop delay depends on the
delay in the digital processing, the AD and DA converters
STABILITY RESEARCH IN THE DIGITAL CARTESIAN
and mainly the baseband components in the hardware
LOOP DESIGN.
design.
Also, it is necessary to include a phase adjustment stage,
From several researches of non-linear systems,
which repairs the phase difference between the signals of the
mainly in radio -frequency systems, it can be come to that the
forward and feedback paths. The phase adjustment is
effect associated to a without memory pass-band system is a
included in the digital modulator I/Q. Therefore, it can repair
variation in amplitude and in phase of the input signal.
the phase difference introduced in all Digital Cartesian loop.
Therefore, the distortion introduced in the cartesian loop
The NCO of the digital modulator I/Q is modified and the
may be shown as a complex gain in the power amplifier
G( v ) = M ( v ) ⋅ e
sine and cosine signals in clude a phase factor. This phase
jf ( v )
(15) factor depends on the Cartesian loop delay and it is

M ( v ) and f ( v ) are the AM/AM and AM/PM real

calculated in an initial calibration process. This effect and its
Where solution have been also introduced in the simulations. The
functions of the power amplifier M68749 from Mitsubishi following figures show the performance obtained in the
simulated as a sixth order polinomy. Matlab simulations. Fig. 5 compares the normalised output
From simulations carried out in Matlab, the main design power spectrum density with open loop, that is, without
parameters have been chosen in order to meet the following Digital Cartesian Loop, with close loop for a 3 Watt. output
specifications power.
The simulation shows that the Digital Cartesian Loop the ADC is sampled, all digital processes, of the forward and
improves the adjacent channel interference around 20-25 dB. feedback path, have to be done and the processing sample
This simulation is carried out with a delay loop approximately must be sent to the DAC. Therefore, the calculation speed
of 450ns, but in a real system, the delay introduced by the must be capable of fulfilling all digital processes between
loop usually is higher. Fig.6 represents the output amplifier sample and sample, that is the sampling time T= 1/fs. This
power spectrum density with different delays. When the implies the maximum optimization in the implementation of
delay increases the performance makes worse, therefore the these algorithms approaching the DSP features, such as
delay being limited by a maximum value. speed or special instructions for signal processing. The
0 algorithms must be researched in order to decrease the
Open loop
Close loop number of instructions and so, to reduce the computational
-20 load and to introduce the minimum delay in the system. In
order to analyse the delay influence, we can introduce
-40 additional delay in the digital domain by oversampling the
signal. Also, the RF board has been designed to introduce
-60 the minimum delay, since this factor is critical in order to
obtain good performance. A 14-bit DAC and a 12-bit ADC
-80
have been chosen in the RF board.

-100
0 0.5 1 1.5 2 2.5 3 3.5 4 VII. CONCLUSIONS.
Fig.5 Output Amplifier Normalised Power Spectrum Density
This paper presents the research of the linealization of a
(dB) versus Normalised frequency (fT). (Cartesian Loop
transmitter by Digital Cartesian Loop. It is based on the
Delay = 450ns and with digital compensation phase factor)
linealization method by Cartesian Loop but introducing the
advantages and possibilities of a digital solution. This
0
Delay 450ns
Digital Cartesian Loop architecture avoids the most of
Delay 1.3us
analog imperfections and provides a better control and
-20
compensation of loop delay. It has been successfully
implemented, achieving the required performance in terms of
-40
ACI. Finally, it is still pending the integration into a
-60
complete TETRA Mobile or Base Station.

-80
Acknowledgements

-100 This work has been supported by the Spanish Science and
0 0.5 1 1.5 2 2.5 3 3.5 4
Technology Ministry and FEDER under grants TIC99-0941
Fig. 6 Output Amplifier Normalised Power Spectrum Density and TIC2001-2481 a nd 2DF97-1070.
(dB) versus Normalised frequency (fT) Cartesian Loop Delay
of 450ns and 1.3 µs References

In order to meet the stability limit, the design parameters [1] Johansson, M. and T. Mattsson, “Transmitter
hav e been changed to obtain 3W in the output power linearization using cartesian feedback for linear TDMA
coef=1.2, A=240, B=0.16, fn=5 KHz, modulation”, IEEE Vehicular Tech. Conf. , St. Louis,
Now the new loop delay limit is τ<1.3 µs. Missouri, USA, 19-22 May 1991, pp. 439-444.
[2] M. Boolorian, J.P. McGeehan, "The Frequency-Hopped
VI. CIRCUIT SPECIFICATION AND DESIGN. Cartesian Feedback Linear Transmitter", IEEE Trans. on
Veh. Tech., Vol. 45, No. 4, November 1996, pp. 688-706 .
Two boards that implement the whole digital cartesian loop [3] J. de Mingo, A. Valdovinos, F. Gutiérrez, “Cartesian Loop
have been designed. The first implements all digital stages Transmitter for TETRA”, IEEE VTC 1999-FALL,
and the second contains the converters (DAC&ADC) and september 1 999, pp. 1511-1515.
RF design. The simulated digital blocks have been [4] P. B. Kenington, “High-Linerity RF Amplifier Design”,
implemented in a fixed-pint DSP (16 bits) and computational Artech House, 2000
load and memory usage issues have been taken into
account. The forward and feedback digital processing must
be carried out in real time, that is, every time the signal from